2019
|
151. | Koyo Minamikawa, Shinya Takamaeda-Yamazaki, Masayuki Ikebe, Masato Motomura, Tetsuya Asai FPGA-Based FORCE Learning Accelerator towards Real-Time Online Reservoir Computing Proceedings Article In: RISP International Workshop on Nonlinear Circuits, Communications and Signal Processing, Honolulu, USA, 2019. @inproceedings{motomura_00046b,
title = {FPGA-Based FORCE Learning Accelerator towards Real-Time Online Reservoir Computing},
author = {Koyo Minamikawa and Shinya Takamaeda-Yamazaki and Masayuki Ikebe and Masato Motomura and Tetsuya Asai},
year = {2019},
date = {2019-03-01},
booktitle = {RISP International Workshop on Nonlinear Circuits, Communications and Signal Processing},
address = {Honolulu, USA},
keywords = {Conference Papers},
pubstate = {published},
tppubtype = {inproceedings}
}
|
152. | 本村 真人 コンピューティングアーキテクチャ Book JST CRDS 研究開発の俯瞰報告書 2019年版, 2019. @book{motomura-jstcrds-2019,
title = {コンピューティングアーキテクチャ},
author = {本村 真人},
year = {2019},
date = {2019-03-01},
publisher = {JST CRDS 研究開発の俯瞰報告書 2019年版},
keywords = {Books},
pubstate = {published},
tppubtype = {book}
}
|
153. | Masato Motomura [Invited] Intelligence at the Edge: Frontiers for Energy-Efficient Hardware Architectures Presentation Riken International Workshop on Neuromorphic Computing (R-WoNC), Kobe, Japan, 01.03.2019. @misc{motomura_00043,
title = {[Invited] Intelligence at the Edge: Frontiers for Energy-Efficient Hardware Architectures},
author = {Masato Motomura},
year = {2019},
date = {2019-03-01},
address = {Riken International Workshop on Neuromorphic Computing (R-WoNC), Kobe, Japan},
keywords = {Invited Talks},
pubstate = {published},
tppubtype = {presentation}
}
|
154. | Masato Motomura [Invited] AI Computing: The Promised Land for Hardware? Presentation Multimedia Workshop, Tokyo, Japan, 01.03.2019. @misc{motomura_00041,
title = {[Invited] AI Computing: The Promised Land for Hardware?},
author = {Masato Motomura},
year = {2019},
date = {2019-03-01},
address = {Multimedia Workshop, Tokyo, Japan},
keywords = {Invited Talks},
pubstate = {published},
tppubtype = {presentation}
}
|
155. | Tatsuya Kaneko, Masayuki Ikebe, Shinya Takamaeda-Yamazaki, Masato Motomura, Tetsuya Asai Ternarized Backpropagation: A Hardware-Oriented Optimization Algorithm for Edge-Oriented AI Devices Proceedings Article In: RIEC International Symposium on Brain Functions and Brain Computer, Sendai, Japan, 2019. @inproceedings{motomura_00047,
title = {Ternarized Backpropagation: A Hardware-Oriented Optimization Algorithm for Edge-Oriented AI Devices},
author = {Tatsuya Kaneko and Masayuki Ikebe and Shinya Takamaeda-Yamazaki and Masato Motomura and Tetsuya Asai},
year = {2019},
date = {2019-02-01},
booktitle = {RIEC International Symposium on Brain Functions and Brain Computer},
address = {Sendai, Japan},
keywords = {Conference Papers},
pubstate = {published},
tppubtype = {inproceedings}
}
|
156. | Seunggoo Rim, Shunya Suzuki, Shinya Takamaeda-Yamazaki, Masayuki Ikebe, Masato Motomura, Tetsuya Asai Approach to Reservoir Computing with Schmitt Trigger Oscillator-Based Analog Neural Circuits Proceedings Article In: Japan-Korea Joint Workshop on Complex Communication Sciences, Pyengonchang, Korea, 2019. @inproceedings{motomura_00049,
title = {Approach to Reservoir Computing with Schmitt Trigger Oscillator-Based Analog Neural Circuits},
author = {Seunggoo Rim and Shunya Suzuki and Shinya Takamaeda-Yamazaki and Masayuki Ikebe and Masato Motomura and Tetsuya Asai},
year = {2019},
date = {2019-01-01},
booktitle = {Japan-Korea Joint Workshop on Complex Communication Sciences},
address = {Pyengonchang, Korea},
keywords = {Conference Papers},
pubstate = {published},
tppubtype = {inproceedings}
}
|
157. | Ryutaro Doi, Jaehoon Yu, Masanori Hashimoto Sneak Path Free Reconfiguration with Minimized Programming Steps for Via-switch Crossbar Based FPGA Journal Article In: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, pp. 1-1, 2019, ISSN: 1937-4151. @article{8935433,
title = {Sneak Path Free Reconfiguration with Minimized Programming Steps for Via-switch Crossbar Based FPGA},
author = {Ryutaro Doi and Jaehoon Yu and Masanori Hashimoto},
issn = {1937-4151},
year = {2019},
date = {2019-01-01},
journal = {IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems},
pages = {1-1},
keywords = {Journal Papers},
pubstate = {published},
tppubtype = {article}
}
|
158. | Thiem Van Chu, Kenji Kise LEF: An Effective Routing Algorithm for Two-Dimensional Meshes Journal Article In: IEICE Transactions on Information and Systems, vol. E102-D, no. 10, pp. 1925–1941, 2019. @article{thiem-ieice2019,
title = {LEF: An Effective Routing Algorithm for Two-Dimensional Meshes},
author = {Thiem Van Chu and Kenji Kise},
year = {2019},
date = {2019-01-01},
journal = {IEICE Transactions on Information and Systems},
volume = {E102-D},
number = {10},
pages = {1925--1941},
keywords = {Journal Papers},
pubstate = {published},
tppubtype = {article}
}
|
159. | Salita Sombatsiri, Seiya Shibata, Yuki Kobayashi, Hiroaki Inoue, Takashi Takenaka, Takeo Hosomi, Jaehoon Yu, Yoshinori Takeuchi Parallelism-Flexible Convolution Core for Sparse Convolutional Neural Networks on FPGA Journal Article In: vol. 12, pp. 22–37, 2019. @article{sombatsiri2019parallelism,
title = {Parallelism-Flexible Convolution Core for Sparse Convolutional Neural Networks on FPGA},
author = {Salita Sombatsiri and Seiya Shibata and Yuki Kobayashi and Hiroaki Inoue and Takashi Takenaka and Takeo Hosomi and Jaehoon Yu and Yoshinori Takeuchi},
year = {2019},
date = {2019-01-01},
volume = {12},
pages = {22--37},
keywords = {Journal Papers},
pubstate = {published},
tppubtype = {article}
}
|
160. | Tai-Yu Cheng, Jaehoon Yu, Masanori Hashimoto Minimizing Energy for Neural Network Training with Logarithm-Approximate Floating-Point Multiplier Proceedings Article In: International Symposium on Power and Timing Modeling, Optimization and Simulation, pp. 91–96, 2019. @inproceedings{cheng-patmos-2019,
title = {Minimizing Energy for Neural Network Training with Logarithm-Approximate Floating-Point Multiplier},
author = {Tai-Yu Cheng and Jaehoon Yu and Masanori Hashimoto},
year = {2019},
date = {2019-01-01},
booktitle = {International Symposium on Power and Timing Modeling, Optimization and Simulation},
pages = {91--96},
keywords = {},
pubstate = {published},
tppubtype = {inproceedings}
}
|
161. | Kodai Ueyoshi, Kota Ando, Kazutoshi Hirose, Shinya Takamaeda-Yamazaki, Mototsugu Hamada, Tadahiro Kuroda, Masato Motomura QUEST: Multi-Purpose Log-Quantized DNN Inference Engine Stacked on 96-MB 3-D SRAM Using Inductive Coupling Technology in 40-nm CMOS Journal Article In: IEEE Journal of Solid-State Circuits, vol. 54, no. 1, pp. 186-196, 2019. @article{motomura_00006,
title = {QUEST: Multi-Purpose Log-Quantized DNN Inference Engine Stacked on 96-MB 3-D SRAM Using Inductive Coupling Technology in 40-nm CMOS},
author = {Kodai Ueyoshi and Kota Ando and Kazutoshi Hirose and Shinya Takamaeda-Yamazaki and Mototsugu Hamada and Tadahiro Kuroda and Masato Motomura},
year = {2019},
date = {2019-01-01},
journal = {IEEE Journal of Solid-State Circuits},
volume = {54},
number = {1},
pages = {186-196},
keywords = {Journal Papers},
pubstate = {published},
tppubtype = {article}
}
|
162. | 本村 真人 深層学習プロセッサの展望 Book 映像メディア学会誌「データ科学を支えるアクセラレーション技術」特集, 2019. @book{motomura-jstcrds-2019b,
title = {深層学習プロセッサの展望},
author = {本村 真人},
year = {2019},
date = {2019-01-01},
publisher = {映像メディア学会誌「データ科学を支えるアクセラレーション技術」特集},
keywords = {Books},
pubstate = {published},
tppubtype = {book}
}
|
2018
|
163. | Kota Ando, Kodai Ueyoshi, Yuka Oba, Kazutoshi Hirose, Ryota Uematsu, Takumi Kudo, Masayuki Ikebe, Tetsuya Asai, Shinya Takamaeda-Yamazaki, Masato Motomura Dither NN: An Accurate Neural Network with Dithering for Low Bit-Precision Hardware Proceedings Article In: International Conference on Field-Programmable Technology (FPT), Naha, Japan, 2018. @inproceedings{motomura_00050,
title = {Dither NN: An Accurate Neural Network with Dithering for Low Bit-Precision Hardware},
author = {Kota Ando and Kodai Ueyoshi and Yuka Oba and Kazutoshi Hirose and Ryota Uematsu and Takumi Kudo and Masayuki Ikebe and Tetsuya Asai and Shinya Takamaeda-Yamazaki and Masato Motomura},
year = {2018},
date = {2018-12-01},
booktitle = {International Conference on Field-Programmable Technology (FPT)},
address = {Naha, Japan},
keywords = {Conference Papers},
pubstate = {published},
tppubtype = {inproceedings}
}
|
164. | Prasoon Ambalathankandy, Takeshi Shimada, Shinya Takamaeda-Yamazaki, Masato Motomura, Tetsuya Asai, Masayuki Ikebe Analysis of Smoothed LHE Methods for Processing Images with Optical Illusions Proceedings Article In: IEEE International Conference on Visual Communications and Image Processing, Taichung, Taiwan, 2018. @inproceedings{motomura_00052,
title = {Analysis of Smoothed LHE Methods for Processing Images with Optical Illusions},
author = {Prasoon Ambalathankandy and Takeshi Shimada and Shinya Takamaeda-Yamazaki and Masato Motomura and Tetsuya Asai and Masayuki Ikebe},
year = {2018},
date = {2018-12-01},
booktitle = {IEEE International Conference on Visual Communications and Image Processing},
address = {Taichung, Taiwan},
keywords = {Conference Papers},
pubstate = {published},
tppubtype = {inproceedings}
}
|
165. | Prasoon Ambalathankandy, Shinya Takamaeda-Yamazaki, Masato Motomura, Tetsuya Asai, Masayuki Ikebe, Hotaka Kusano Real-time HDTV to 4K and 8K-UHD Conversions Using Anti-Aliasing Based Super Resolution Algorithm on FPGA Journal Article In: Microprocessors and Microsystems, vol. 60, 2018. @article{motomura_00007,
title = {Real-time HDTV to 4K and 8K-UHD Conversions Using Anti-Aliasing Based Super Resolution Algorithm on FPGA},
author = {Prasoon Ambalathankandy and Shinya Takamaeda-Yamazaki and Masato Motomura and Tetsuya Asai and Masayuki Ikebe and Hotaka Kusano},
year = {2018},
date = {2018-12-01},
journal = {Microprocessors and Microsystems},
volume = {60},
keywords = {Journal Papers},
pubstate = {published},
tppubtype = {article}
}
|
166. | Masato Motomura [Invited] Structure-Oriented Computing: Where Software Redefines Hardware Architecture Presentation Future Chips Forum, Beijing, China, 01.12.2018. @misc{motomura_00051,
title = {[Invited] Structure-Oriented Computing: Where Software Redefines Hardware Architecture},
author = {Masato Motomura},
year = {2018},
date = {2018-12-01},
address = {Future Chips Forum, Beijing, China},
keywords = {Invited Talks},
pubstate = {published},
tppubtype = {presentation}
}
|
167. | Masato Motomura [Invited] Intelligence at the Edge: Frontiers for Energy-Efficient Hardware Architectures Presentation International IoT Solid-State Circuits Workshop, Hshinchu, Taiwan, 01.11.2018. @misc{motomura_00055,
title = {[Invited] Intelligence at the Edge: Frontiers for Energy-Efficient Hardware Architectures},
author = {Masato Motomura},
year = {2018},
date = {2018-11-01},
address = {International IoT Solid-State Circuits Workshop, Hshinchu, Taiwan},
keywords = {Invited Talks},
pubstate = {published},
tppubtype = {presentation}
}
|
168. | Akram Ben Ahmed, Daichi Fujiki, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano [Best Paper Nomination] AxNoC: Low-power Approximate Network-on-Chips using Critical-Path Isolation Proceedings Article In: International Symposium on Networks-on-Chip (NOCS), 2018. @inproceedings{nocs-2018,
title = {[Best Paper Nomination] AxNoC: Low-power Approximate Network-on-Chips using Critical-Path Isolation},
author = {Akram Ben Ahmed and Daichi Fujiki and Hiroki Matsutani and Michihiro Koibuchi and Hideharu Amano},
year = {2018},
date = {2018-10-04},
booktitle = {International Symposium on Networks-on-Chip (NOCS)},
keywords = {Awards, Conference Papers},
pubstate = {published},
tppubtype = {inproceedings}
}
|
169. | Tatsuya Kaneko, Masayuki Ikebe, Shinya Takamaeda-Yamazaki, Masato Motomura, Tetsuya Asai A Study on Ternary Back Propagation Algorithm for Embedded Egde-AI Processing Proceedings Article In: Joint Workshop of UCL-ICN, NTT, UCL-Gatsby and AIBS: Analysis and Synthesis for Human/Artificial Cognition and Behaviour, Okinawa, Japan, 2018. @inproceedings{motomura_00057,
title = {A Study on Ternary Back Propagation Algorithm for Embedded Egde-AI Processing},
author = {Tatsuya Kaneko and Masayuki Ikebe and Shinya Takamaeda-Yamazaki and Masato Motomura and Tetsuya Asai},
year = {2018},
date = {2018-10-01},
booktitle = {Joint Workshop of UCL-ICN, NTT, UCL-Gatsby and AIBS: Analysis and Synthesis for Human/Artificial Cognition and Behaviour},
address = {Okinawa, Japan},
keywords = {Conference Papers},
pubstate = {published},
tppubtype = {inproceedings}
}
|
170. | Kazutoshi Hirose, Ryota Uematsu, Kota Ando, Kodai Ueyoshi, Masayuki Ikebe, Tetsuya Asai, Masato Motomura, Shinya Takamaeda-Yamazaki Quantization Error-Based Regularization for Hardware-Aware Neural Network Training Journal Article In: Nonlinear Theory and Its Applications, vol. E9-N, no. 4, pp. 453-465, 2018. @article{motomura_00008,
title = {Quantization Error-Based Regularization for Hardware-Aware Neural Network Training},
author = {Kazutoshi Hirose and Ryota Uematsu and Kota Ando and Kodai Ueyoshi and Masayuki Ikebe and Tetsuya Asai and Masato Motomura and Shinya Takamaeda-Yamazaki},
year = {2018},
date = {2018-10-01},
journal = {Nonlinear Theory and Its Applications},
volume = {E9-N},
number = {4},
pages = {453-465},
keywords = {Journal Papers},
pubstate = {published},
tppubtype = {article}
}
|
171. | Takumi Kudo, Kodai Ueyoshi, Kota Ando, Kazutoshi Hirose, Ryota Uematsu, Yuka Oba, Masayuki Ikebe, Tetsuya Asai, Masato Motomura, Shinya Takamaeda-Yamazaki Area and Energy Optimization for Bit-Serial Log-Quantized DNN Accelerator with Shared Accumulators Proceedings Article In: IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, Hanoi, Vietnam, 2018. @inproceedings{motomura_00061,
title = {Area and Energy Optimization for Bit-Serial Log-Quantized DNN Accelerator with Shared Accumulators},
author = {Takumi Kudo and Kodai Ueyoshi and Kota Ando and Kazutoshi Hirose and Ryota Uematsu and Yuka Oba and Masayuki Ikebe and Tetsuya Asai and Masato Motomura and Shinya Takamaeda-Yamazaki},
year = {2018},
date = {2018-09-01},
booktitle = {IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip},
address = {Hanoi, Vietnam},
keywords = {Conference Papers},
pubstate = {published},
tppubtype = {inproceedings}
}
|
172. | Masanori Hashimoto, Yuki Nakazawa, Jaehoon Yu Interconnect Delay Analysis for RRAM Crossbar Based FPGA Proceedings Article In: IEEE Computer Society Annual Symposium on VLSI (ISVLSI), pp. 522-527, 2018. @inproceedings{yu-isvlsi-2018,
title = {Interconnect Delay Analysis for RRAM Crossbar Based FPGA},
author = {Masanori Hashimoto and Yuki Nakazawa and Jaehoon Yu},
year = {2018},
date = {2018-07-08},
booktitle = {IEEE Computer Society Annual Symposium on VLSI (ISVLSI)},
pages = {522-527},
keywords = {Conference Papers},
pubstate = {published},
tppubtype = {inproceedings}
}
|
173. | Taro Fujii, Takao Toi, Teruhito Tanaka, Katsumi Togawa, Toshiro Kitaoka, Kengo Nishino, Noritsugu Nakamura, Hiroki Nakahara, Masato Motomura New Generation Dynamically Reconfigurable Processor Technology for Accelerating Embedded AI Applications Proceedings Article In: Symposia on VLSI Technology and Circuits, Hawaii, USA, 2018. @inproceedings{motomura_00062,
title = {New Generation Dynamically Reconfigurable Processor Technology for Accelerating Embedded AI Applications},
author = {Taro Fujii and Takao Toi and Teruhito Tanaka and Katsumi Togawa and Toshiro Kitaoka and Kengo Nishino and Noritsugu Nakamura and Hiroki Nakahara and Masato Motomura},
year = {2018},
date = {2018-06-01},
booktitle = {Symposia on VLSI Technology and Circuits},
address = {Hawaii, USA},
keywords = {Conference Papers},
pubstate = {published},
tppubtype = {inproceedings}
}
|
174. | Masato Motomura [Invited] Hardware-Oriented Approaches for Accelerating “AI” Workloads Presentation Symposium on VLSI Circuits, Short Course, Hololulu, USA, 01.06.2018. @misc{motomura_00063,
title = {[Invited] Hardware-Oriented Approaches for Accelerating “AI” Workloads},
author = {Masato Motomura},
year = {2018},
date = {2018-06-01},
address = {Symposium on VLSI Circuits, Short Course, Hololulu, USA},
keywords = {Invited Talks},
pubstate = {published},
tppubtype = {presentation}
}
|
175. | Takeshi Shimada, Masayuki Ikebe, Prasoon Ambalathankandy, Shinya Takamaeda-Yamazaki, Masato Motomura, Tetsuya Asai Sparse Disparity Estimation Using Global Phase Only Correlation for Stereo Matching Acceleration Proceedings Article In: IEEE International Conference on Acoustics, Speech and Signal Processing, Alberta, Canada, 2018. @inproceedings{motomura_00071,
title = {Sparse Disparity Estimation Using Global Phase Only Correlation for Stereo Matching Acceleration},
author = {Takeshi Shimada and Masayuki Ikebe and Prasoon Ambalathankandy and Shinya Takamaeda-Yamazaki and Masato Motomura and Tetsuya Asai},
year = {2018},
date = {2018-04-01},
booktitle = {IEEE International Conference on Acoustics, Speech and Signal Processing},
address = {Alberta, Canada},
keywords = {Conference Papers},
pubstate = {published},
tppubtype = {inproceedings}
}
|
176. | Kota Ando, Kodai Ueyoshi, Kentaro Orimo, Haruyoshi Yonekawa, Shimpei Sato, Hiroki Nakahara, Shinya Takamaeda-Yamazaki, Masayuki Ikebe, Tetsuya Asai, Tadahiro Kuroda, Masato Motomura BRein Memory: A Single-Chip Binary/Ternary Reconfigurable In-Memory Deep Neural Network Accelerator Achieving 1.4TOPS at 0.6W Journal Article In: IEEE Journal of Solid-State Circuits, vol. 53, no. 4, pp. 983-994, 2018. @article{motomura_00009,
title = {BRein Memory: A Single-Chip Binary/Ternary Reconfigurable In-Memory Deep Neural Network Accelerator Achieving 1.4TOPS at 0.6W},
author = {Kota Ando and Kodai Ueyoshi and Kentaro Orimo and Haruyoshi Yonekawa and Shimpei Sato and Hiroki Nakahara and Shinya Takamaeda-Yamazaki and Masayuki Ikebe and Tetsuya Asai and Tadahiro Kuroda and Masato Motomura},
year = {2018},
date = {2018-04-01},
journal = {IEEE Journal of Solid-State Circuits},
volume = {53},
number = {4},
pages = {983-994},
keywords = {Journal Papers},
pubstate = {published},
tppubtype = {article}
}
|
177. | Ryota Uematsu, Kota Ando, Kodai Ueyoshi, Kazutoshi Hirose, Masayuki Ikebe, Tetsuya Asai, Shinya Takamaeda-Yamazaki, Masato Motomura Exploring CNN Accelerator Design Space on a Dynamically Reconfigurable Hardware Platform Proceedings Article In: Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI), Matsue, Japan, 2018. @inproceedings{motomura_00072,
title = {Exploring CNN Accelerator Design Space on a Dynamically Reconfigurable Hardware Platform},
author = {Ryota Uematsu and Kota Ando and Kodai Ueyoshi and Kazutoshi Hirose and Masayuki Ikebe and Tetsuya Asai and Shinya Takamaeda-Yamazaki and Masato Motomura},
year = {2018},
date = {2018-03-01},
booktitle = {Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI)},
address = {Matsue, Japan},
keywords = {Conference Papers},
pubstate = {published},
tppubtype = {inproceedings}
}
|
178. | Naoto Iwamaru, Shinya Takamaeda-Yamazaki, Masayuki Ikebe, Masato Motomura, Tetsuya Asai A Novel Iris-Center Detection Algorithm towards Gaze Estimation Targeting Molecular Cellular Automata Proceedings Article In: International Workshop on Molecular Architectonics, Osaka, Japan, 2018. @inproceedings{motomura_00074,
title = {A Novel Iris-Center Detection Algorithm towards Gaze Estimation Targeting Molecular Cellular Automata},
author = {Naoto Iwamaru and Shinya Takamaeda-Yamazaki and Masayuki Ikebe and Masato Motomura and Tetsuya Asai},
year = {2018},
date = {2018-03-01},
booktitle = {International Workshop on Molecular Architectonics},
address = {Osaka, Japan},
keywords = {Conference Papers},
pubstate = {published},
tppubtype = {inproceedings}
}
|
179. | Kodai Ueyoshi, Kota Ando, Kazutoshi Hirose, Shinya Takamaeda-Yamazaki, Junichiro Kadomoto, Tomoki Miyata, Mototsugu Hamada, Tadahiro Kuroda, Masato Motomura QUEST: A 7.49-TOPS Multi-Purpose Log-Quantized DNN Inference Engine Stacked on 96MB 3D SRAM using Inductive-Coupling Technology in 40nm CMOS Proceedings Article In: International Solid-State Circuits Conference (ISSCC 2018), San Francisco, US, 2018. @inproceedings{motomura_00076,
title = {QUEST: A 7.49-TOPS Multi-Purpose Log-Quantized DNN Inference Engine Stacked on 96MB 3D SRAM using Inductive-Coupling Technology in 40nm CMOS},
author = {Kodai Ueyoshi and Kota Ando and Kazutoshi Hirose and Shinya Takamaeda-Yamazaki and Junichiro Kadomoto and Tomoki Miyata and Mototsugu Hamada and Tadahiro Kuroda and Masato Motomura},
year = {2018},
date = {2018-02-01},
booktitle = {International Solid-State Circuits Conference (ISSCC 2018)},
address = {San Francisco, US},
keywords = {Conference Papers},
pubstate = {published},
tppubtype = {inproceedings}
}
|
180. | Aoi Tanibata, Alexandre Schmid, Shinya Takamaeda-Yamazaki, Masayuki Ikebe, Masato Motomura, Tetsuya Asai Proto-Computing Architecture over A Digital Medium Aiming at Real-Time Video Processing Journal Article In: Complexity, vol. 2018, pp. 3618621-1-11, 2018. @article{motomura_00010,
title = {Proto-Computing Architecture over A Digital Medium Aiming at Real-Time Video Processing},
author = {Aoi Tanibata and Alexandre Schmid and Shinya Takamaeda-Yamazaki and Masayuki Ikebe and Masato Motomura and Tetsuya Asai},
year = {2018},
date = {2018-02-01},
journal = {Complexity},
volume = {2018},
pages = {3618621-1-11},
keywords = {Journal Papers},
pubstate = {published},
tppubtype = {article}
}
|
181. | Tomoki Sugiura, Jaehoon Yu, Yoshinori Takeuchi Phase Locking Value Calculator based on Hardware-oriented Mathematical Expression Journal Article In: vol. 101, no. 12, pp. 2254–2261, 2018. @article{sugiura2018phase,
title = {Phase Locking Value Calculator based on Hardware-oriented Mathematical Expression},
author = {Tomoki Sugiura and Jaehoon Yu and Yoshinori Takeuchi},
year = {2018},
date = {2018-01-01},
volume = {101},
number = {12},
pages = {2254--2261},
keywords = {Journal Papers},
pubstate = {published},
tppubtype = {article}
}
|
182. | Koichi Mitsunari, Yoshinori Takeuchi, Masaharu Imai, Jaehoon Yu Decomposed Vector Histograms of Oriented Gradients for Efficient Hardware Implementation Journal Article In: IEICE_J_FECACS, vol. 101, no. 11, pp. 1766–1775, 2018, ((被引用件数: 1)). @article{mitsunari2018decomposed,
title = {Decomposed Vector Histograms of Oriented Gradients for Efficient Hardware Implementation},
author = {Koichi Mitsunari and Yoshinori Takeuchi and Masaharu Imai and Jaehoon Yu},
year = {2018},
date = {2018-01-01},
journal = {IEICE_J_FECACS},
volume = {101},
number = {11},
pages = {1766--1775},
note = {(被引用件数: 1)},
keywords = {Journal Papers},
pubstate = {published},
tppubtype = {article}
}
|
183. | Hiroyuki Ochi, Kosei Yamaguchi, Tetsuaki Fujimoto, Junshi Hotate, Takashi Kishimoto, Toshiki Higashi, Takashi Imagawa, Ryutaro Doi, Munehiro Tada, Tadahiko Sugibayashi, Wataru Takahashi, Kazutoshi Wakabayashi, Hidetoshi Onodera, Yukio Mitsuyama, Jaehoon Yu, Masanori Hashimoto Via-Switch FPGA: Highly Dense Mixed-Grained Reconfigurable Architecture with Overlay Via-Switch Crossbars Journal Article In: no. 99, pp. 1–14, 2018, ((IF: 1.744, 被引用件数: 3)). @article{ochi2018via,
title = {Via-Switch FPGA: Highly Dense Mixed-Grained Reconfigurable Architecture with Overlay Via-Switch Crossbars},
author = {Hiroyuki Ochi and Kosei Yamaguchi and Tetsuaki Fujimoto and Junshi Hotate and Takashi Kishimoto and Toshiki Higashi and Takashi Imagawa and Ryutaro Doi and Munehiro Tada and Tadahiko Sugibayashi and Wataru Takahashi and Kazutoshi Wakabayashi and Hidetoshi Onodera and Yukio Mitsuyama and Jaehoon Yu and Masanori Hashimoto},
year = {2018},
date = {2018-01-01},
number = {99},
pages = {1--14},
note = {(IF: 1.744, 被引用件数: 3)},
keywords = {Journal Papers},
pubstate = {published},
tppubtype = {article}
}
|
184. | Koichi Mitsunari, Jaehoon Yu, Takao Onoye, Masanori Hashimoto Hardware Architecture for High-Speed Object Detection Using Decision Tree Ensemble Journal Article In: IEICE_J_FECACS, vol. 101, no. 9, pp. 1298–1307, 2018, ((被引用件数: 1)). @article{mitsunari2018hardware,
title = {Hardware Architecture for High-Speed Object Detection Using Decision Tree Ensemble},
author = {Koichi Mitsunari and Jaehoon Yu and Takao Onoye and Masanori Hashimoto},
year = {2018},
date = {2018-01-01},
journal = {IEICE_J_FECACS},
volume = {101},
number = {9},
pages = {1298--1307},
note = {(被引用件数: 1)},
keywords = {Journal Papers},
pubstate = {published},
tppubtype = {article}
}
|
185. | Koichi Mitsunari, Jaehoon Yu, Masanori Hashimoto Hardware Architecture for Fast General Object Detection Using Aggregated Channel Features Proceedings Article In: pp. 55-58, 2018. @inproceedings{mitsunari2018hardware-asscc,
title = {Hardware Architecture for Fast General Object Detection Using Aggregated Channel Features},
author = {Koichi Mitsunari and Jaehoon Yu and Masanori Hashimoto},
year = {2018},
date = {2018-01-01},
pages = {55-58},
keywords = {Conference Papers},
pubstate = {published},
tppubtype = {inproceedings}
}
|
186. | Ryutaro Doi, Jaehoon Yu, Masanori Hashimoto Sneak Path Free Reconfiguration of Via-switch Crossbars Based FPGA Proceedings Article In: pp. 68:1–68:8, 2018. @inproceedings{doi2018sneak,
title = {Sneak Path Free Reconfiguration of Via-switch Crossbars Based FPGA},
author = {Ryutaro Doi and Jaehoon Yu and Masanori Hashimoto},
year = {2018},
date = {2018-01-01},
pages = {68:1--68:8},
keywords = {Conference Papers},
pubstate = {published},
tppubtype = {inproceedings}
}
|
187. | Kenshi Ito, Jaehoon Yu, Masanori Hashimoto Adapting Soft Cascade to MAC Operations of Convolutional Neural Networks Proceedings Article In: International Symposium on Multimedia and Communication Technology, pp. 101–104, 2018. @inproceedings{ito2018adapting,
title = {Adapting Soft Cascade to MAC Operations of Convolutional Neural Networks},
author = {Kenshi Ito and Jaehoon Yu and Masanori Hashimoto},
year = {2018},
date = {2018-01-01},
booktitle = {International Symposium on Multimedia and Communication Technology},
pages = {101--104},
keywords = {Conference Papers},
pubstate = {published},
tppubtype = {inproceedings}
}
|
188. | Masanori Hashimoto, Yuki Nakazawa, Ryutaro Doi, Jaehoon Yu Interconnect Delay Analysis for RRAM Crossbar Based FPGA Proceedings Article In: pp. 522–527, 2018. @inproceedings{hashimoto2018interconnect,
title = {Interconnect Delay Analysis for RRAM Crossbar Based FPGA},
author = {Masanori Hashimoto and Yuki Nakazawa and Ryutaro Doi and Jaehoon Yu},
year = {2018},
date = {2018-01-01},
pages = {522--527},
keywords = {Conference Papers},
pubstate = {published},
tppubtype = {inproceedings}
}
|
189. | 中澤祐希, 土井龍太郎, 劉載勲, 橋本昌宜 ビアスイッチ FPGA 向け配線解析手法の検討 (VLSI 設計技術) Proceedings Article In: 電子情報通信学会技術研究報告= IEICE technical report: 信学技報, pp. 187–192, 2018. @inproceedings{中澤祐希2018ビアスイッチ,
title = {ビアスイッチ FPGA 向け配線解析手法の検討 (VLSI 設計技術)},
author = {中澤祐希 and 土井龍太郎 and 劉載勲 and 橋本昌宜},
year = {2018},
date = {2018-01-01},
booktitle = {電子情報通信学会技術研究報告= IEICE technical report: 信学技報},
volume = {117},
number = {455},
pages = {187--192},
keywords = {Conference Papers},
pubstate = {published},
tppubtype = {inproceedings}
}
|
190. | 土井龍太郎, 劉載勲, 橋本昌宜, others ビアスイッチ FPGA 再構成時のスニークパス問題を回避するプログラミング順決定手法 Proceedings Article In: DA シンポジウム 2018 論文集, pp. 3–8, 2018. @inproceedings{土井龍太郎2018ビアスイッチ,
title = {ビアスイッチ FPGA 再構成時のスニークパス問題を回避するプログラミング順決定手法},
author = {土井龍太郎 and 劉載勲 and 橋本昌宜 and others},
year = {2018},
date = {2018-01-01},
booktitle = {DA シンポジウム 2018 論文集},
volume = {2018},
pages = {3--8},
keywords = {Conference Papers},
pubstate = {published},
tppubtype = {inproceedings}
}
|
2017
|
191. | Itaru Hida, Kodai Ueyoshi, Shinya Takamaeda-Yamazaki, Masayuki Ikebe, Masato Motomura, Tetsuya Asai Sign-Invariant Unsupervised Learning Facilitates Weighted-Sum Computation in Analog Neural-Network Devices Proceedings Article In: International Symposium on Nonlinear Theory and Its Applications, Cancun, Mexico, 2017. @inproceedings{motomura_00082,
title = {Sign-Invariant Unsupervised Learning Facilitates Weighted-Sum Computation in Analog Neural-Network Devices},
author = {Itaru Hida and Kodai Ueyoshi and Shinya Takamaeda-Yamazaki and Masayuki Ikebe and Masato Motomura and Tetsuya Asai},
year = {2017},
date = {2017-12-01},
booktitle = {International Symposium on Nonlinear Theory and Its Applications},
address = {Cancun, Mexico},
keywords = {Conference Papers},
pubstate = {published},
tppubtype = {inproceedings}
}
|
192. | Masato Motomura [Invited] Trends toward Reconfigurable and in-Memory Processing Architectures for Deep Neural Networks Presentation Future Chips Forum, Beijing, China, 01.12.2017. @misc{motomura_00079,
title = {[Invited] Trends toward Reconfigurable and in-Memory Processing Architectures for Deep Neural Networks},
author = {Masato Motomura},
year = {2017},
date = {2017-12-01},
address = {Future Chips Forum, Beijing, China},
keywords = {Invited Talks},
pubstate = {published},
tppubtype = {presentation}
}
|
193. | Shinya Takamaeda-Yamazaki, Kodai Ueyoshi, Kota Ando, Ryota Uematsu, Kazutoshi Hirose, Masayuki Ikebe, Tetsuya Asai, Masato Motomura Accelerating Deep Learning by Binarized Hardware Proceedings Article In: Asia-Pacific Signal and Information Processing Association Annual Summit and Conference (APSIPA ASC), Kuala Lumpur, Malaysia, 2017. @inproceedings{ando_00015,
title = {Accelerating Deep Learning by Binarized Hardware},
author = {Shinya Takamaeda-Yamazaki and Kodai Ueyoshi and Kota Ando and Ryota Uematsu and Kazutoshi Hirose and Masayuki Ikebe and Tetsuya Asai and Masato Motomura},
year = {2017},
date = {2017-12-01},
booktitle = {Asia-Pacific Signal and Information Processing Association Annual Summit and Conference (APSIPA ASC)},
address = {Kuala Lumpur, Malaysia},
keywords = {Conference Papers},
pubstate = {published},
tppubtype = {inproceedings}
}
|
194. | Kazutoshi Hirose, Kota Ando, Kodai Ueyoshi, Masayuki Ikebe, Tetsuya Asai, Masato Motomura, Shinya Takamaeda-Yamazaki Quantization Error-based Regularization in Neural Networks Proceedings Article In: SGAI International Conference on Artificial Intelligence (SGAI), Cambridge, England, 2017. @inproceedings{ando_00016,
title = {Quantization Error-based Regularization in Neural Networks},
author = {Kazutoshi Hirose and Kota Ando and Kodai Ueyoshi and Masayuki Ikebe and Tetsuya Asai and Masato Motomura and Shinya Takamaeda-Yamazaki},
year = {2017},
date = {2017-12-01},
booktitle = {SGAI International Conference on Artificial Intelligence (SGAI)},
address = {Cambridge, England},
keywords = {Conference Papers},
pubstate = {published},
tppubtype = {inproceedings}
}
|
195. | Kazutoshi Hirose, Ryota Uematsu, Kota Ando, Kentaro Orimo, Kodai Ueyoshi, Masayuki Ikebe, Tetsuya Asai, Shinya Takamaeda-Yamazaki, Masato Motomura Logarithmic Compression for Memory Footprint Reduction in Neural Network Training Proceedings Article In: International Workshop on Computer Systems and Architectures (CSA), Aomori, Japan, 2017. @inproceedings{ando_00017,
title = {Logarithmic Compression for Memory Footprint Reduction in Neural Network Training},
author = {Kazutoshi Hirose and Ryota Uematsu and Kota Ando and Kentaro Orimo and Kodai Ueyoshi and Masayuki Ikebe and Tetsuya Asai and Shinya Takamaeda-Yamazaki and Masato Motomura},
year = {2017},
date = {2017-11-01},
booktitle = {International Workshop on Computer Systems and Architectures (CSA)},
address = {Aomori, Japan},
keywords = {Conference Papers},
pubstate = {published},
tppubtype = {inproceedings}
}
|
196. | Masato Motomura [Invited] Research Activity on Deep Neural Network Accelerators Presentation Tsinghua University Workshop, Beijing, China, 01.10.2017. @misc{motomura_00087,
title = {[Invited] Research Activity on Deep Neural Network Accelerators},
author = {Masato Motomura},
year = {2017},
date = {2017-10-01},
address = {Tsinghua University Workshop, Beijing, China},
keywords = {Invited Talks},
pubstate = {published},
tppubtype = {presentation}
}
|
197. | Masato Motomura [Invited] Trends toward Reconfigurable and in-Memory Processing Architectures for Deep Neural Networks Presentation Chinese Academy of Science (CAS) Distinguished Lecture, Beijing, China, 01.10.2017. @misc{motomura_00088,
title = {[Invited] Trends toward Reconfigurable and in-Memory Processing Architectures for Deep Neural Networks},
author = {Masato Motomura},
year = {2017},
date = {2017-10-01},
address = {Chinese Academy of Science (CAS) Distinguished Lecture, Beijing, China},
keywords = {Invited Talks},
pubstate = {published},
tppubtype = {presentation}
}
|
198. | Kazutoshi Hirose, Ryota Uematsu, Kota Ando, Kodai Ueyoshi, Masayuki Ikebe, Tetsuya Asai, Masato Motomura, Shinya Takamaeda-Yamazaki A Regularization Approach for Quantized Neural Networks Proceedings Article In: International Workshop on Highly Efficient Neural Networks Design (HENND), Seoul, Korea, 2017. @inproceedings{ando_00018,
title = {A Regularization Approach for Quantized Neural Networks},
author = {Kazutoshi Hirose and Ryota Uematsu and Kota Ando and Kodai Ueyoshi and Masayuki Ikebe and Tetsuya Asai and Masato Motomura and Shinya Takamaeda-Yamazaki},
year = {2017},
date = {2017-10-01},
booktitle = {International Workshop on Highly Efficient Neural Networks Design (HENND)},
address = {Seoul, Korea},
keywords = {Conference Papers},
pubstate = {published},
tppubtype = {inproceedings}
}
|
199. | Aoi Tanibata, Alexandre Schmid, Shinya Takamaeda-Yamazaki, Masayuki Ikebe, Masato Motomura, Tetsuya Asai FPGA Implementation of Edge-Guided Pattern Generation for Motion-Vector Estimation of Textureless Objects (Demo Night) Proceedings Article In: International Conference on Field-Programmable Logic and Applications (FPL), Ghent, Belgium, 2017. @inproceedings{motomura_00091,
title = {FPGA Implementation of Edge-Guided Pattern Generation for Motion-Vector Estimation of Textureless Objects (Demo Night)},
author = {Aoi Tanibata and Alexandre Schmid and Shinya Takamaeda-Yamazaki and Masayuki Ikebe and Masato Motomura and Tetsuya Asai},
year = {2017},
date = {2017-09-01},
booktitle = {International Conference on Field-Programmable Logic and Applications (FPL)},
address = {Ghent, Belgium},
keywords = {Conference Papers},
pubstate = {published},
tppubtype = {inproceedings}
}
|
200. | Kota Ando, Kodai Ueyoshi, Kazutoshi Hirose, Kentaro Orimo, Haruyoshi Yonekawa, Shimpei Sato, Hiroki Nakahara, Masayuki Ikebe, Shinya Takamaeda-Yamazaki, Tetsuya Asai, Tadahiro Kuroda, Masato Motomura In-Memory Area-Efficient Signal Streaming Processor Design for Binary Neural Networks Proceedings Article In: IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), Boston, USA, 2017. @inproceedings{ando_00020,
title = {In-Memory Area-Efficient Signal Streaming Processor Design for Binary Neural Networks},
author = {Kota Ando and Kodai Ueyoshi and Kazutoshi Hirose and Kentaro Orimo and Haruyoshi Yonekawa and Shimpei Sato and Hiroki Nakahara and Masayuki Ikebe and Shinya Takamaeda-Yamazaki and Tetsuya Asai and Tadahiro Kuroda and Masato Motomura},
year = {2017},
date = {2017-08-01},
booktitle = {IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)},
address = {Boston, USA},
keywords = {Conference Papers},
pubstate = {published},
tppubtype = {inproceedings}
}
|