469 entries « 4 of 10 »

2019

151.

Shunya Suzuki, Seunggoo Rim, Shinya Takamaeda-Yamazaki, Masayuki Ikebe, Masato Motomura, Tetsuya Asai

Experimental Demonstration of Physical Reservoir Computing with Nonlinear Electronic Devices Proceedings Article

In: RISP International Workshop on Nonlinear Circuits, Communications and Signal Processing, Honolulu, USA, 2019.

BibTeX | Tags: Conference Papers

152.

Koyo Minamikawa, Shinya Takamaeda-Yamazaki, Masayuki Ikebe, Masato Motomura, Tetsuya Asai

FPGA-Based FORCE Learning Accelerator towards Real-Time Online Reservoir Computing Proceedings Article

In: RISP International Workshop on Nonlinear Circuits, Communications and Signal Processing, Honolulu, USA, 2019.

BibTeX | Tags: Conference Papers

153.

本村 真人

コンピューティングアーキテクチャ Book

JST CRDS 研究開発の俯瞰報告書 2019年版, 2019.

BibTeX | Tags: Books

154.

Masato Motomura

[Invited] Intelligence at the Edge: Frontiers for Energy-Efficient Hardware Architectures Presentation

Riken International Workshop on Neuromorphic Computing (R-WoNC), Kobe, Japan, 01.03.2019.

BibTeX | Tags: Invited Talks

155.

Masato Motomura

[Invited] AI Computing: The Promised Land for Hardware? Presentation

Multimedia Workshop, Tokyo, Japan, 01.03.2019.

BibTeX | Tags: Invited Talks

156.

Tatsuya Kaneko, Masayuki Ikebe, Shinya Takamaeda-Yamazaki, Masato Motomura, Tetsuya Asai

Ternarized Backpropagation: A Hardware-Oriented Optimization Algorithm for Edge-Oriented AI Devices Proceedings Article

In: RIEC International Symposium on Brain Functions and Brain Computer, Sendai, Japan, 2019.

BibTeX | Tags: Conference Papers

157.

Seunggoo Rim, Shunya Suzuki, Shinya Takamaeda-Yamazaki, Masayuki Ikebe, Masato Motomura, Tetsuya Asai

Approach to Reservoir Computing with Schmitt Trigger Oscillator-Based Analog Neural Circuits Proceedings Article

In: Japan-Korea Joint Workshop on Complex Communication Sciences, Pyengonchang, Korea, 2019.

BibTeX | Tags: Conference Papers

158.

Ryutaro Doi, Jaehoon Yu, Masanori Hashimoto

Sneak Path Free Reconfiguration with Minimized Programming Steps for Via-switch Crossbar Based FPGA Journal Article

In: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, pp. 1-1, 2019, ISSN: 1937-4151.

BibTeX | Tags: Journal Papers

159.

Thiem Van Chu, Kenji Kise

LEF: An Effective Routing Algorithm for Two-Dimensional Meshes Journal Article

In: IEICE Transactions on Information and Systems, vol. E102-D, no. 10, pp. 1925–1941, 2019.

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160.

Salita Sombatsiri, Seiya Shibata, Yuki Kobayashi, Hiroaki Inoue, Takashi Takenaka, Takeo Hosomi, Jaehoon Yu, Yoshinori Takeuchi

Parallelism-Flexible Convolution Core for Sparse Convolutional Neural Networks on FPGA Journal Article

In: vol. 12, pp. 22–37, 2019.

BibTeX | Tags: Journal Papers

161.

Tai-Yu Cheng, Jaehoon Yu, Masanori Hashimoto

Minimizing Energy for Neural Network Training with Logarithm-Approximate Floating-Point Multiplier Proceedings Article

In: International Symposium on Power and Timing Modeling, Optimization and Simulation, pp. 91–96, 2019.

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162.

Kodai Ueyoshi, Kota Ando, Kazutoshi Hirose, Shinya Takamaeda-Yamazaki, Mototsugu Hamada, Tadahiro Kuroda, Masato Motomura

QUEST: Multi-Purpose Log-Quantized DNN Inference Engine Stacked on 96-MB 3-D SRAM Using Inductive Coupling Technology in 40-nm CMOS Journal Article

In: IEEE Journal of Solid-State Circuits, vol. 54, no. 1, pp. 186-196, 2019.

BibTeX | Tags: Journal Papers

163.

本村 真人

深層学習プロセッサの展望 Book

映像メディア学会誌「データ科学を支えるアクセラレーション技術」特集, 2019.

BibTeX | Tags: Books

2018

164.

Kota Ando, Kodai Ueyoshi, Yuka Oba, Kazutoshi Hirose, Ryota Uematsu, Takumi Kudo, Masayuki Ikebe, Tetsuya Asai, Shinya Takamaeda-Yamazaki, Masato Motomura

Dither NN: An Accurate Neural Network with Dithering for Low Bit-Precision Hardware Proceedings Article

In: International Conference on Field-Programmable Technology (FPT), Naha, Japan, 2018.

BibTeX | Tags: Conference Papers

165.

Prasoon Ambalathankandy, Takeshi Shimada, Shinya Takamaeda-Yamazaki, Masato Motomura, Tetsuya Asai, Masayuki Ikebe

Analysis of Smoothed LHE Methods for Processing Images with Optical Illusions Proceedings Article

In: IEEE International Conference on Visual Communications and Image Processing, Taichung, Taiwan, 2018.

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166.

Prasoon Ambalathankandy, Shinya Takamaeda-Yamazaki, Masato Motomura, Tetsuya Asai, Masayuki Ikebe, Hotaka Kusano

Real-time HDTV to 4K and 8K-UHD Conversions Using Anti-Aliasing Based Super Resolution Algorithm on FPGA Journal Article

In: Microprocessors and Microsystems, vol. 60, 2018.

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167.

Masato Motomura

[Invited] Structure-Oriented Computing: Where Software Redefines Hardware Architecture Presentation

Future Chips Forum, Beijing, China, 01.12.2018.

BibTeX | Tags: Invited Talks

168.

Masato Motomura

[Invited] Intelligence at the Edge: Frontiers for Energy-Efficient Hardware Architectures Presentation

International IoT Solid-State Circuits Workshop, Hshinchu, Taiwan, 01.11.2018.

BibTeX | Tags: Invited Talks

169.

Akram Ben Ahmed, Daichi Fujiki, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano

[Best Paper Nomination] AxNoC: Low-power Approximate Network-on-Chips using Critical-Path Isolation Proceedings Article

In: International Symposium on Networks-on-Chip (NOCS), 2018.

BibTeX | Tags: Awards, Conference Papers

170.

Tatsuya Kaneko, Masayuki Ikebe, Shinya Takamaeda-Yamazaki, Masato Motomura, Tetsuya Asai

A Study on Ternary Back Propagation Algorithm for Embedded Egde-AI Processing Proceedings Article

In: Joint Workshop of UCL-ICN, NTT, UCL-Gatsby and AIBS: Analysis and Synthesis for Human/Artificial Cognition and Behaviour, Okinawa, Japan, 2018.

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171.

Kazutoshi Hirose, Ryota Uematsu, Kota Ando, Kodai Ueyoshi, Masayuki Ikebe, Tetsuya Asai, Masato Motomura, Shinya Takamaeda-Yamazaki

Quantization Error-Based Regularization for Hardware-Aware Neural Network Training Journal Article

In: Nonlinear Theory and Its Applications, vol. E9-N, no. 4, pp. 453-465, 2018.

BibTeX | Tags: Journal Papers

172.

Takumi Kudo, Kodai Ueyoshi, Kota Ando, Kazutoshi Hirose, Ryota Uematsu, Yuka Oba, Masayuki Ikebe, Tetsuya Asai, Masato Motomura, Shinya Takamaeda-Yamazaki

Area and Energy Optimization for Bit-Serial Log-Quantized DNN Accelerator with Shared Accumulators Proceedings Article

In: IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, Hanoi, Vietnam, 2018.

BibTeX | Tags: Conference Papers

173.

Masanori Hashimoto, Yuki Nakazawa, Jaehoon Yu

Interconnect Delay Analysis for RRAM Crossbar Based FPGA Proceedings Article

In: IEEE Computer Society Annual Symposium on VLSI (ISVLSI), pp. 522-527, 2018.

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174.

Taro Fujii, Takao Toi, Teruhito Tanaka, Katsumi Togawa, Toshiro Kitaoka, Kengo Nishino, Noritsugu Nakamura, Hiroki Nakahara, Masato Motomura

New Generation Dynamically Reconfigurable Processor Technology for Accelerating Embedded AI Applications Proceedings Article

In: Symposia on VLSI Technology and Circuits, Hawaii, USA, 2018.

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175.

Masato Motomura

[Invited] Hardware-Oriented Approaches for Accelerating “AI” Workloads Presentation

Symposium on VLSI Circuits, Short Course, Hololulu, USA, 01.06.2018.

BibTeX | Tags: Invited Talks

176.

Takeshi Shimada, Masayuki Ikebe, Prasoon Ambalathankandy, Shinya Takamaeda-Yamazaki, Masato Motomura, Tetsuya Asai

Sparse Disparity Estimation Using Global Phase Only Correlation for Stereo Matching Acceleration Proceedings Article

In: IEEE International Conference on Acoustics, Speech and Signal Processing, Alberta, Canada, 2018.

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177.

Kota Ando, Kodai Ueyoshi, Kentaro Orimo, Haruyoshi Yonekawa, Shimpei Sato, Hiroki Nakahara, Shinya Takamaeda-Yamazaki, Masayuki Ikebe, Tetsuya Asai, Tadahiro Kuroda, Masato Motomura

BRein Memory: A Single-Chip Binary/Ternary Reconfigurable In-Memory Deep Neural Network Accelerator Achieving 1.4TOPS at 0.6W Journal Article

In: IEEE Journal of Solid-State Circuits, vol. 53, no. 4, pp. 983-994, 2018.

BibTeX | Tags: Journal Papers

178.

Ryota Uematsu, Kota Ando, Kodai Ueyoshi, Kazutoshi Hirose, Masayuki Ikebe, Tetsuya Asai, Shinya Takamaeda-Yamazaki, Masato Motomura

Exploring CNN Accelerator Design Space on a Dynamically Reconfigurable Hardware Platform Proceedings Article

In: Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI), Matsue, Japan, 2018.

BibTeX | Tags: Conference Papers

179.

Naoto Iwamaru, Shinya Takamaeda-Yamazaki, Masayuki Ikebe, Masato Motomura, Tetsuya Asai

A Novel Iris-Center Detection Algorithm towards Gaze Estimation Targeting Molecular Cellular Automata Proceedings Article

In: International Workshop on Molecular Architectonics, Osaka, Japan, 2018.

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180.

Kodai Ueyoshi, Kota Ando, Kazutoshi Hirose, Shinya Takamaeda-Yamazaki, Junichiro Kadomoto, Tomoki Miyata, Mototsugu Hamada, Tadahiro Kuroda, Masato Motomura

QUEST: A 7.49-TOPS Multi-Purpose Log-Quantized DNN Inference Engine Stacked on 96MB 3D SRAM using Inductive-Coupling Technology in 40nm CMOS Proceedings Article

In: International Solid-State Circuits Conference (ISSCC 2018), San Francisco, US, 2018.

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181.

Aoi Tanibata, Alexandre Schmid, Shinya Takamaeda-Yamazaki, Masayuki Ikebe, Masato Motomura, Tetsuya Asai

Proto-Computing Architecture over A Digital Medium Aiming at Real-Time Video Processing Journal Article

In: Complexity, vol. 2018, pp. 3618621-1-11, 2018.

BibTeX | Tags: Journal Papers

182.

Tomoki Sugiura, Jaehoon Yu, Yoshinori Takeuchi

Phase Locking Value Calculator based on Hardware-oriented Mathematical Expression Journal Article

In: vol. 101, no. 12, pp. 2254–2261, 2018.

BibTeX | Tags: Journal Papers

183.

Koichi Mitsunari, Yoshinori Takeuchi, Masaharu Imai, Jaehoon Yu

Decomposed Vector Histograms of Oriented Gradients for Efficient Hardware Implementation Journal Article

In: IEICE_J_FECACS, vol. 101, no. 11, pp. 1766–1775, 2018, ((被引用件数: 1)).

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184.

Hiroyuki Ochi, Kosei Yamaguchi, Tetsuaki Fujimoto, Junshi Hotate, Takashi Kishimoto, Toshiki Higashi, Takashi Imagawa, Ryutaro Doi, Munehiro Tada, Tadahiko Sugibayashi, Wataru Takahashi, Kazutoshi Wakabayashi, Hidetoshi Onodera, Yukio Mitsuyama, Jaehoon Yu, Masanori Hashimoto

Via-Switch FPGA: Highly Dense Mixed-Grained Reconfigurable Architecture with Overlay Via-Switch Crossbars Journal Article

In: no. 99, pp. 1–14, 2018, ((IF: 1.744, 被引用件数: 3)).

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185.

Koichi Mitsunari, Jaehoon Yu, Takao Onoye, Masanori Hashimoto

Hardware Architecture for High-Speed Object Detection Using Decision Tree Ensemble Journal Article

In: IEICE_J_FECACS, vol. 101, no. 9, pp. 1298–1307, 2018, ((被引用件数: 1)).

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186.

Koichi Mitsunari, Jaehoon Yu, Masanori Hashimoto

Hardware Architecture for Fast General Object Detection Using Aggregated Channel Features Proceedings Article

In: pp. 55-58, 2018.

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187.

Ryutaro Doi, Jaehoon Yu, Masanori Hashimoto

Sneak Path Free Reconfiguration of Via-switch Crossbars Based FPGA Proceedings Article

In: pp. 68:1–68:8, 2018.

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188.

Kenshi Ito, Jaehoon Yu, Masanori Hashimoto

Adapting Soft Cascade to MAC Operations of Convolutional Neural Networks Proceedings Article

In: International Symposium on Multimedia and Communication Technology, pp. 101–104, 2018.

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189.

Masanori Hashimoto, Yuki Nakazawa, Ryutaro Doi, Jaehoon Yu

Interconnect Delay Analysis for RRAM Crossbar Based FPGA Proceedings Article

In: pp. 522–527, 2018.

BibTeX | Tags: Conference Papers

190.

中澤祐希, 土井龍太郎, 劉載勲, 橋本昌宜

ビアスイッチ FPGA 向け配線解析手法の検討 (VLSI 設計技術) Proceedings Article

In: 電子情報通信学会技術研究報告= IEICE technical report: 信学技報, pp. 187–192, 2018.

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191.

土井龍太郎, 劉載勲, 橋本昌宜, others

ビアスイッチ FPGA 再構成時のスニークパス問題を回避するプログラミング順決定手法 Proceedings Article

In: DA シンポジウム 2018 論文集, pp. 3–8, 2018.

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2017

192.

Shinya Takamaeda-Yamazaki, Kodai Ueyoshi, Kota Ando, Ryota Uematsu, Kazutoshi Hirose, Masayuki Ikebe, Tetsuya Asai, Masato Motomura

Accelerating Deep Learning by Binarized Hardware Proceedings Article

In: Asia-Pacific Signal and Information Processing Association Annual Summit and Conference (APSIPA ASC), Kuala Lumpur, Malaysia, 2017.

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193.

Kazutoshi Hirose, Kota Ando, Kodai Ueyoshi, Masayuki Ikebe, Tetsuya Asai, Masato Motomura, Shinya Takamaeda-Yamazaki

Quantization Error-based Regularization in Neural Networks Proceedings Article

In: SGAI International Conference on Artificial Intelligence (SGAI), Cambridge, England, 2017.

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194.

Itaru Hida, Kodai Ueyoshi, Shinya Takamaeda-Yamazaki, Masayuki Ikebe, Masato Motomura, Tetsuya Asai

Sign-Invariant Unsupervised Learning Facilitates Weighted-Sum Computation in Analog Neural-Network Devices Proceedings Article

In: International Symposium on Nonlinear Theory and Its Applications, Cancun, Mexico, 2017.

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195.

Masato Motomura

[Invited] Trends toward Reconfigurable and in-Memory Processing Architectures for Deep Neural Networks Presentation

Future Chips Forum, Beijing, China, 01.12.2017.

BibTeX | Tags: Invited Talks

196.

Kazutoshi Hirose, Ryota Uematsu, Kota Ando, Kentaro Orimo, Kodai Ueyoshi, Masayuki Ikebe, Tetsuya Asai, Shinya Takamaeda-Yamazaki, Masato Motomura

Logarithmic Compression for Memory Footprint Reduction in Neural Network Training Proceedings Article

In: International Workshop on Computer Systems and Architectures (CSA), Aomori, Japan, 2017.

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197.

Kazutoshi Hirose, Ryota Uematsu, Kota Ando, Kodai Ueyoshi, Masayuki Ikebe, Tetsuya Asai, Masato Motomura, Shinya Takamaeda-Yamazaki

A Regularization Approach for Quantized Neural Networks Proceedings Article

In: International Workshop on Highly Efficient Neural Networks Design (HENND), Seoul, Korea, 2017.

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198.

Masato Motomura

[Invited] Research Activity on Deep Neural Network Accelerators Presentation

Tsinghua University Workshop, Beijing, China, 01.10.2017.

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199.

Masato Motomura

[Invited] Trends toward Reconfigurable and in-Memory Processing Architectures for Deep Neural Networks Presentation

Chinese Academy of Science (CAS) Distinguished Lecture, Beijing, China, 01.10.2017.

BibTeX | Tags: Invited Talks

200.

Aoi Tanibata, Alexandre Schmid, Shinya Takamaeda-Yamazaki, Masayuki Ikebe, Masato Motomura, Tetsuya Asai

FPGA Implementation of Edge-Guided Pattern Generation for Motion-Vector Estimation of Textureless Objects (Demo Night) Proceedings Article

In: International Conference on Field-Programmable Logic and Applications (FPL), Ghent, Belgium, 2017.

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469 entries « 4 of 10 »