2025
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1. | Hiroaki Ito, Jiale Yan, Kazushi Kawamura, Masato Motomura, Thiem Van Chu, Daichi Fujiki TF-GNN: Memory-Efficient GNNs via Tensor Train Decomposition and Network Folding Conference COOL Chips 28, Japan, 2025. @conference{nokey,
title = {TF-GNN: Memory-Efficient GNNs via Tensor Train Decomposition and Network Folding},
author = {Hiroaki Ito and Jiale Yan and Kazushi Kawamura and Masato Motomura and Thiem Van Chu and Daichi Fujiki},
year = {2025},
date = {2025-03-20},
urldate = {2025-03-20},
booktitle = {COOL Chips 28},
address = {Japan},
keywords = {Conference Papers},
pubstate = {published},
tppubtype = {conference}
}
|
2024
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2. | Yuki Kameyama, Naoya Niwa, Daichi Fujiki, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano (Ed.) The Case for Coherence Directories in Memory Cubes Conference 2024 17th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC-2024), 2024. @conference{nokey,
title = {The Case for Coherence Directories in Memory Cubes},
editor = {Yuki Kameyama and Naoya Niwa and Daichi Fujiki and Hiroki Matsutani and Michihiro Koibuchi and Hideharu Amano},
year = {2024},
date = {2024-12-12},
urldate = {2024-12-12},
booktitle = {2024 17th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC-2024)},
keywords = {Conference Papers},
pubstate = {published},
tppubtype = {conference}
}
|
3. | Akihiro Shioda, Ángel López García-Arias, Hikari Otsuka, Yuki Ichikawa, Yasuyuki Okoshi, Kazushi Kawamura, Thiem Van Chu, Daichi Fujiki, Masato Motomura Exploiting N: M Sparsity in Quantized-Folded ResNets: Signed Multicoat Supermasks and Iterative Pruning-Quantization Conference 2024 Twelfth International Symposium on Computing and Networking (CANDAR), 2024. @conference{nokey,
title = {Exploiting N: M Sparsity in Quantized-Folded ResNets: Signed Multicoat Supermasks and Iterative Pruning-Quantization},
author = {Akihiro Shioda and Ángel López García-Arias and Hikari Otsuka and Yuki Ichikawa and Yasuyuki Okoshi and Kazushi Kawamura and Thiem Van Chu and Daichi Fujiki and Masato Motomura},
url = {https://ieeexplore.ieee.org/abstract/document/10818255},
year = {2024},
date = {2024-12-03},
urldate = {2024-12-03},
booktitle = {2024 Twelfth International Symposium on Computing and Networking (CANDAR)},
keywords = {Conference Papers},
pubstate = {published},
tppubtype = {conference}
}
|
4. | Yasuyuki Okoshi, Ángel López García-Arias, Jaehoon Yu, Junnnosuke Suzuki, Hikari Otsuka, Thiem Van Chu, Kazushi Kawamura, Daichi Fujiki, Masato Motomura
WhiteDwarf: 12.24 TFLOPS/W 40 nm Versatile Neural Inference Engine for Ultra-Compact Execution of CNNs and MLPs Through Triple Unstructured Sparsity Exploitation and Triple Model Compression Conference 2024 IEEE Asian Solid-State Circuits Conference (A-SSCC), 2024. @conference{nokey,
title = {WhiteDwarf: 12.24 TFLOPS/W 40 nm Versatile Neural Inference Engine for Ultra-Compact Execution of CNNs and MLPs Through Triple Unstructured Sparsity Exploitation and Triple Model Compression},
author = {Yasuyuki Okoshi and Ángel López García-Arias and Jaehoon Yu and Junnnosuke Suzuki and Hikari Otsuka and Thiem Van Chu and Kazushi Kawamura and Daichi Fujiki and Masato Motomura
},
url = {https://ieeexplore.ieee.org/document/10849314
},
year = {2024},
date = {2024-11-18},
urldate = {2024-11-18},
booktitle = {2024 IEEE Asian Solid-State Circuits Conference (A-SSCC)},
keywords = {Conference Papers},
pubstate = {published},
tppubtype = {conference}
}
|
5. | Kyo Kuroki, Satoru Jimbo, Thiem Van Chu, Masato Motomura, Kazushi Kawamura Classical Thermodynamics-based Parallel Annealing Algorithm for High-speed and Robust Combinatorial Optimization Proceedings Article In: The Genetic and Evolutionary Computation Conference (GECCO), 2024. @inproceedings{kuroki-gecco-2024,
title = {Classical Thermodynamics-based Parallel Annealing Algorithm for High-speed and Robust Combinatorial Optimization},
author = {Kyo Kuroki and Satoru Jimbo and Thiem Van Chu and Masato Motomura and Kazushi Kawamura},
year = {2024},
date = {2024-07-14},
booktitle = {The Genetic and Evolutionary Computation Conference (GECCO)},
keywords = {Conference Papers},
pubstate = {published},
tppubtype = {inproceedings}
}
|
6. | Tsukasa Yamakura, Kazushi Kawamura, Masato Motomura, Thiem Van Chu ETreeNet: Ensemble Model Fusing Decision Trees and Neural Networks for Small Tabular Data Proceedings Article In: International Joint Conference on Neural Networks (IJCNN), 2024. @inproceedings{yamakura-ijcnn-2024,
title = {ETreeNet: Ensemble Model Fusing Decision Trees and Neural Networks for Small Tabular Data},
author = {Tsukasa Yamakura and Kazushi Kawamura and Masato Motomura and Thiem Van Chu},
year = {2024},
date = {2024-06-30},
booktitle = {International Joint Conference on Neural Networks (IJCNN)},
keywords = {Conference Papers},
pubstate = {published},
tppubtype = {inproceedings}
}
|
7. | Junnosuke Suzuki, Mari Yasunaga, Kazushi Kawamura, Thiem Van Chu, Masato Motomura Progressive Variable Precision DNN with Bitwise Ternary Accumulation Proceedings Article In: International Conference on Artificial Intelligence Circuits and Systems (AICAS), 2024. @inproceedings{suzuki-aicas-2024,
title = {Progressive Variable Precision DNN with Bitwise Ternary Accumulation},
author = {Junnosuke Suzuki and Mari Yasunaga and Kazushi Kawamura and Thiem Van Chu and Masato Motomura},
year = {2024},
date = {2024-04-23},
booktitle = {International Conference on Artificial Intelligence Circuits and Systems (AICAS)},
keywords = {Conference Papers},
pubstate = {published},
tppubtype = {inproceedings}
}
|
8. | Hikari Otsuka, Yasuyuki Okoshi, Ángel López García-Arias, Kazushi Kawamura, Thiem Van Chu, Masato Motomura Ramanujan Edge-Popup: Finding Strong Lottery Tickets with Ramanujan Graph Properties for Efficient DNN Inference Execution Proceedings Article In: Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI), 2024. @inproceedings{otsuka-sasimi-2024,
title = {Ramanujan Edge-Popup: Finding Strong Lottery Tickets with Ramanujan Graph Properties for Efficient DNN Inference Execution},
author = {Hikari Otsuka and Yasuyuki Okoshi and Ángel López García-Arias and Kazushi Kawamura and Thiem Van Chu and Masato Motomura},
year = {2024},
date = {2024-03-12},
booktitle = {Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI)},
keywords = {Conference Papers},
pubstate = {published},
tppubtype = {inproceedings}
}
|
9. | YC Chen, S Ando, D Fujiki, S Takamaeda-Yamazaki, K Yoshioka OSA-HCIM: On-The-Fly Saliency-Aware Hybrid SRAM CIM with Dynamic Precision Configuration Proceedings 2024 29th Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 539-544, 2024. @proceedings{asp-dac_2024_dfujiki,
title = {OSA-HCIM: On-The-Fly Saliency-Aware Hybrid SRAM CIM with Dynamic Precision Configuration},
author = {YC Chen, S Ando, D Fujiki, S Takamaeda-Yamazaki, K Yoshioka},
year = {2024},
date = {2024-01-25},
urldate = {2024-01-25},
howpublished = {2024 29th Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 539-544},
keywords = {Conference Papers},
pubstate = {published},
tppubtype = {proceedings}
}
|
10. | Yuta Nagahara, Jiale Yan, Kazushi Kawamura, Masato Motomura, Thiem Van Chu Sparse-Sparse Matrix Multiplication Accelerator on FPGA featuring Distribute-Merge Product Dataflow Proceedings Article In: Asia and South Pacific Design Automation Conference (ASP-DAC), 2024. @inproceedings{asp-dac-2024,
title = {Sparse-Sparse Matrix Multiplication Accelerator on FPGA featuring Distribute-Merge Product Dataflow},
author = {Yuta Nagahara and Jiale Yan and Kazushi Kawamura and Masato Motomura and Thiem Van Chu},
year = {2024},
date = {2024-01-25},
booktitle = {Asia and South Pacific Design Automation Conference (ASP-DAC)},
keywords = {Conference Papers},
pubstate = {published},
tppubtype = {inproceedings}
}
|
11. | Masato Watanabe, Shungo Kumazawa, Thiem Van Chu, Kazushi Kawamura, Jaehoon Yu, Masato Motomura Exploration of Hyperdimensional Computing Using Locality-Sensitive Hashing Mechanism on FPGA Proceedings Article In: International Conference on Consumer Electronics (ICCE), 2024. @inproceedings{icce-2024-04,
title = {Exploration of Hyperdimensional Computing Using Locality-Sensitive Hashing Mechanism on FPGA},
author = {Masato Watanabe and Shungo Kumazawa and Thiem Van Chu and Kazushi Kawamura and Jaehoon Yu and Masato Motomura},
year = {2024},
date = {2024-01-05},
booktitle = {International Conference on Consumer Electronics (ICCE)},
keywords = {Conference Papers},
pubstate = {published},
tppubtype = {inproceedings}
}
|
12. | Mari Yasunaga, Junnosuke Suzuki, Masato Watanabe, Kazushi Kawamura, Thiem Van Chu, Masato Motomura High Throughput Datapath Design for Vision Permutator FPGA Accelerator Proceedings Article In: International Conference on Consumer Electronics (ICCE), 2024. @inproceedings{icce-2024-03,
title = {High Throughput Datapath Design for Vision Permutator FPGA Accelerator},
author = {Mari Yasunaga and Junnosuke Suzuki and Masato Watanabe and Kazushi Kawamura and Thiem Van Chu and Masato Motomura},
year = {2024},
date = {2024-01-05},
urldate = {2024-01-05},
booktitle = {International Conference on Consumer Electronics (ICCE)},
keywords = {Conference Papers},
pubstate = {published},
tppubtype = {inproceedings}
}
|
13. | Yuki Ichikawa, Akihiro Shioda, Kazushi Kawamura, Thiem Van Chu, Masato Motomura An Accurate FPGA-Based ORB Feature Extractor for SLAM with Row-Wise Keypoint Selection Proceedings Article In: International Conference on Consumer Electronics (ICCE), 2024. @inproceedings{icce-2024-02,
title = {An Accurate FPGA-Based ORB Feature Extractor for SLAM with Row-Wise Keypoint Selection},
author = {Yuki Ichikawa and Akihiro Shioda and Kazushi Kawamura and Thiem Van Chu and Masato Motomura},
year = {2024},
date = {2024-01-05},
booktitle = {International Conference on Consumer Electronics (ICCE)},
keywords = {Conference Papers},
pubstate = {published},
tppubtype = {inproceedings}
}
|
14. | Yuta Nagahara, Jiale Yan, Kazushi Kawamura, Masato Motomura, Thiem Van Chu Efficient COO to CSR Conversion for Accelerating Sparse Matrix Processing on FPGA Proceedings Article In: International Conference on Consumer Electronics (ICCE), 2024. @inproceedings{icce-2024-01,
title = {Efficient COO to CSR Conversion for Accelerating Sparse Matrix Processing on FPGA},
author = {Yuta Nagahara and Jiale Yan and Kazushi Kawamura and Masato Motomura and Thiem Van Chu},
year = {2024},
date = {2024-01-05},
booktitle = {International Conference on Consumer Electronics (ICCE)},
keywords = {Conference Papers},
pubstate = {published},
tppubtype = {inproceedings}
}
|
2023
|
15. | Mari Yasunaga, Junnosuke Suzuki, Masato Watanabe, Kazushi Kawamura, Thiem Van Chu, Jaehoon Yu, Masato Motomura A Highly Accurate and Parallel Vision MLP FPGA Accelerator based on FP7/8 SIMD Operations Proceedings Article In: International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC), 2023. @inproceedings{mcsoc-2023-yasunaga,
title = {A Highly Accurate and Parallel Vision MLP FPGA Accelerator based on FP7/8 SIMD Operations},
author = {Mari Yasunaga and Junnosuke Suzuki and Masato Watanabe and Kazushi Kawamura and Thiem Van Chu and Jaehoon Yu and Masato Motomura},
year = {2023},
date = {2023-12-18},
booktitle = {International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC)},
keywords = {Conference Papers},
pubstate = {published},
tppubtype = {inproceedings}
}
|
16. | Alireza Khadem, Daichi Fujiki, Nishil Talati, Scott A. Mahlke, Reetuparna Das [Best Paper Nomination] Vector-Processing for Mobile Devices: Benchmark and Analysis Proceedings Article In: IEEE International Symposium on Workload Characterization, 2023. @inproceedings{iiswc-2023,
title = {[Best Paper Nomination] Vector-Processing for Mobile Devices: Benchmark and Analysis},
author = {Alireza Khadem and Daichi Fujiki and Nishil Talati and Scott A. Mahlke and Reetuparna Das},
year = {2023},
date = {2023-10-02},
booktitle = {IEEE International Symposium on Workload Characterization},
keywords = {Awards, Conference Papers},
pubstate = {published},
tppubtype = {inproceedings}
}
|
17. | Junnosuke Suzuki, Jaehoon Yu, Mari Yasunaga, Ángel López García-Arias, Yasuyuki Okoshi, Shungo Kumazawa, Kota Ando, Kazushi Kawamura, Thiem Van Chu, Masato Motomura Pianissimo: A Sub-mW Class DNN Accelerator with Progressive Bit-by-Bit Datapath Architecture for Adaptive Inference at Edge Conference Symposium on VLSI Technology and Circuits, 2023, 2023. @conference{suzuki-vssympo-2023,
title = {Pianissimo: A Sub-mW Class DNN Accelerator with Progressive Bit-by-Bit Datapath Architecture for Adaptive Inference at Edge},
author = {Junnosuke Suzuki and Jaehoon Yu and Mari Yasunaga and Ángel López García-Arias and Yasuyuki Okoshi and Shungo Kumazawa and Kota Ando and Kazushi Kawamura and Thiem Van Chu and Masato Motomura},
year = {2023},
date = {2023-06-14},
booktitle = {Symposium on VLSI Technology and Circuits, 2023},
keywords = {Conference Papers},
pubstate = {published},
tppubtype = {conference}
}
|
18. | Thiem Van Chu, Yu Mizutani, Yuta Nagahara, Shungo Kumazawa, Kazushi Kawamura, Jaehoon Yu, Masato Motomura Decision Forest Training Accelerator Based on Binary Feature Decomposition Proceedings Article In: International Symposium on Field-Programmable Custom Computing Machines (FCCM), 2023. @inproceedings{fccm-2023-thiem,
title = {Decision Forest Training Accelerator Based on Binary Feature Decomposition},
author = {Thiem Van Chu and Yu Mizutani and Yuta Nagahara and Shungo Kumazawa and Kazushi Kawamura and Jaehoon Yu and Masato Motomura},
year = {2023},
date = {2023-05-09},
booktitle = {International Symposium on Field-Programmable Custom Computing Machines (FCCM)},
keywords = {Conference Papers},
pubstate = {published},
tppubtype = {inproceedings}
}
|
19. | Genta Inoue, Daiki Okonogi, Thiem Van Chu, Jaehoon Yu, Masato Motomura, Kazushi Kawamura Flexibly Controllable Dynamic Cooling Methods for Solid-State Annealing Processors to Improve Combinatorial Optimization Performance Proceedings Article In: IEEE Symposium on Low-Power and High-Speed Chips and Systems, COOL Chips 26, 2023. @inproceedings{inoue-coolchips2023,
title = {Flexibly Controllable Dynamic Cooling Methods for Solid-State Annealing Processors to Improve Combinatorial Optimization Performance},
author = {Genta Inoue and Daiki Okonogi and Thiem Van Chu and Jaehoon Yu and Masato Motomura and Kazushi Kawamura},
year = {2023},
date = {2023-04-21},
urldate = {2023-04-21},
booktitle = {IEEE Symposium on Low-Power and High-Speed Chips and Systems, COOL Chips 26},
keywords = {Conference Papers},
pubstate = {published},
tppubtype = {inproceedings}
}
|
20. | Jiale Yan, Masato Motomura [Best Poster Award] Optimized Deep MLP for Tensor Train-based Inference Engine Proceedings Article In: IEEE Symposium on Low-Power and High-Speed Chips and Systems (COOL Chips), 2023. @inproceedings{jiale-coolchips2023,
title = {[Best Poster Award] Optimized Deep MLP for Tensor Train-based Inference Engine},
author = {Jiale Yan and Masato Motomura},
year = {2023},
date = {2023-04-21},
urldate = {2023-04-21},
booktitle = {IEEE Symposium on Low-Power and High-Speed Chips and Systems (COOL Chips)},
keywords = {Awards, Conference Papers},
pubstate = {published},
tppubtype = {inproceedings}
}
|
21. | Kazushi Kawamura, Jaehoon Yu, Daiki Okonogi, Satoru Jimbo, Genta Inoue, Akira Hyodo, Ángel López García-Arias, Kota Ando, Bruno Hideki Fukushima-Kimura, Ryota Yasudo, Thiem Van Chu, Masato Motomura
Amorphica: 4-Replica 512 Fully Connected Spin 336MHz Metamorphic Annealer with Programmable Optimization Strategy and Compressed-Spin-Transfer Multi-Chip Extension Proceedings Article In: International Solid-State Circuits Conference (ISSCC), 2023. @inproceedings{amorphica-isscc2023,
title = {Amorphica: 4-Replica 512 Fully Connected Spin 336MHz Metamorphic Annealer with Programmable Optimization Strategy and Compressed-Spin-Transfer Multi-Chip Extension},
author = {Kazushi Kawamura and Jaehoon Yu and Daiki Okonogi and Satoru Jimbo and Genta Inoue and Akira Hyodo and Ángel López García-Arias and Kota Ando and Bruno Hideki Fukushima-Kimura and Ryota Yasudo and Thiem Van Chu and Masato Motomura
},
year = {2023},
date = {2023-02-19},
urldate = {2023-02-19},
booktitle = {International Solid-State Circuits Conference (ISSCC)},
keywords = {Conference Papers},
pubstate = {published},
tppubtype = {inproceedings}
}
|
2022
|
22. | Masafumi Tanaka, Jaehoon Yu, Masaki Nakagawa, Naoya Tate, Masanori Hashimoto Investigating Small Device Implementation of FRET-based Optical Reservoir Computing Proceedings Article In: The IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), 2022. @inproceedings{mwscas2022,
title = {Investigating Small Device Implementation of FRET-based Optical Reservoir Computing},
author = {Masafumi Tanaka and Jaehoon Yu and Masaki Nakagawa and Naoya Tate and Masanori Hashimoto},
year = {2022},
date = {2022-08-07},
booktitle = {The IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)},
keywords = {Conference Papers},
pubstate = {published},
tppubtype = {inproceedings}
}
|
23. | Yasuyuki Okoshi, Ángel López García-Arias, Kazutoshi Hirose, Kota Ando, Kazushi Kawamura, Thiem Van Chu, Masato Motomura, Jaehoon Yu Multicoated Supermasks Enhance Hidden Networks Proceedings Article In: International Conference on Machine Learning (ICML), 2022. @inproceedings{icml2022-okoshi,
title = {Multicoated Supermasks Enhance Hidden Networks},
author = {Yasuyuki Okoshi and Ángel López García-Arias and Kazutoshi Hirose and Kota Ando and Kazushi Kawamura and Thiem Van Chu and Masato Motomura and Jaehoon Yu},
year = {2022},
date = {2022-07-23},
booktitle = {International Conference on Machine Learning (ICML)},
keywords = {Conference Papers},
pubstate = {published},
tppubtype = {inproceedings}
}
|
24. | Satida Sookpong, Teerasit Kasetkasem, Teera Phatrapornnant, Jaehoon Yu A Unhealthy Plant Identification System Using a Generative Adversarial Network Proceedings Article In: International Conference on Electrical Engineering/Electronics, Computer, Telecommunications and Information Technology (ECTI-CON), 2022. @inproceedings{ecticon2022,
title = {A Unhealthy Plant Identification System Using a Generative Adversarial Network},
author = {Satida Sookpong and Teerasit Kasetkasem and Teera Phatrapornnant and Jaehoon Yu},
year = {2022},
date = {2022-05-25},
booktitle = {International Conference on Electrical Engineering/Electronics, Computer, Telecommunications and Information Technology (ECTI-CON)},
keywords = {Conference Papers},
pubstate = {published},
tppubtype = {inproceedings}
}
|
25. | Kazutoshi Hirose, Jaehoon Yu, Kota Ando, Yasuyuki Okoshi, Ángel López García-Arias, Junnosuke Suzuki, Thiem Van Chu, Kazushi Kawamura, Masato Motomura Hiddenite: 4K-PE Hidden Network Inference 4D-Tensor Engine Exploiting On-Chip Model Construction Achieving 34.8-to-16.0TOPS/W for CIFAR-100 and ImageNet Proceedings Article In: International Solid-State Circuits Conference (ISSCC), 2022. @inproceedings{hiddenite-isscc2022,
title = {Hiddenite: 4K-PE Hidden Network Inference 4D-Tensor Engine Exploiting On-Chip Model Construction Achieving 34.8-to-16.0TOPS/W for CIFAR-100 and ImageNet},
author = {Kazutoshi Hirose and Jaehoon Yu and Kota Ando and Yasuyuki Okoshi and Ángel López García-Arias and Junnosuke Suzuki and Thiem Van Chu and Kazushi Kawamura and Masato Motomura},
year = {2022},
date = {2022-02-20},
booktitle = {International Solid-State Circuits Conference (ISSCC)},
keywords = {Conference Papers},
pubstate = {published},
tppubtype = {inproceedings}
}
|
2021
|
26. | Thiem Van Chu, Ryuichi Kitajima, Kazushi Kawamura, Jaehoon Yu, Masato Motomura [Best Paper Award] A High-Performance and Flexible FPGA Inference Accelerator for Decision Forests Based on Prior Feature Space Partitioning Proceedings Article In: International Conference on Field-Programmable Technology (FPT), 2021. @inproceedings{thiem-fpt2021,
title = {[Best Paper Award] A High-Performance and Flexible FPGA Inference Accelerator for Decision Forests Based on Prior Feature Space Partitioning},
author = {Thiem Van Chu and Ryuichi Kitajima and Kazushi Kawamura and Jaehoon Yu and Masato Motomura},
year = {2021},
date = {2021-12-06},
urldate = {2021-12-06},
booktitle = {International Conference on Field-Programmable Technology (FPT)},
keywords = {Awards, Conference Papers},
pubstate = {published},
tppubtype = {inproceedings}
}
|
27. | Ángel López García-Arias, Masanori Hashimoto, Masato Motomura, Jaehoon Yu Hidden-Fold Networks: Random Recurrent Residuals Using Sparse Supermasks Proceedings Article In: The British Machine Vision Conference (BMVC), 2021. @inproceedings{lopez-bmvc2021,
title = {Hidden-Fold Networks: Random Recurrent Residuals Using Sparse Supermasks},
author = {Ángel López García-Arias and Masanori Hashimoto and Masato Motomura and Jaehoon Yu},
year = {2021},
date = {2021-11-22},
booktitle = {The British Machine Vision Conference (BMVC)},
keywords = {Conference Papers},
pubstate = {published},
tppubtype = {inproceedings}
}
|
28. | Kota Ando, Jaehoon Yu, Kazutoshi Hirose, Hiroki Nakahara, Kazushi Kawamura, Thiem Van Chu, Masato Motomura Edge Inference Engine for Deep & Random Sparse Neural Networks with 4-bit Cartesian-Product MAC Array and Pipelined Activation Aligner Proceedings Article In: Hot Chips 33 (Poster), 2021. @inproceedings{ando-hotchips-2021,
title = {Edge Inference Engine for Deep & Random Sparse Neural Networks with 4-bit Cartesian-Product MAC Array and Pipelined Activation Aligner},
author = {Kota Ando and Jaehoon Yu and Kazutoshi Hirose and Hiroki Nakahara and Kazushi Kawamura and Thiem Van Chu and Masato Motomura},
year = {2021},
date = {2021-08-24},
booktitle = {Hot Chips 33 (Poster)},
keywords = {Conference Papers},
pubstate = {published},
tppubtype = {inproceedings}
}
|
29. | Takashi Imagawa, Jaehoon Yu, Masanori Hashimoto, Hiroyuki Ochi MUX Granularity-Oriented Iterative Technology Mapping for Implementing Compute-Intensive Applications on Via-Switch FPGA Proceedings Article In: Design, Automation and Test in Europe Conference (DATE), 2021. @inproceedings{yu-date-2021,
title = {MUX Granularity-Oriented Iterative Technology Mapping for Implementing Compute-Intensive Applications on Via-Switch FPGA},
author = {Takashi Imagawa and Jaehoon Yu and Masanori Hashimoto and Hiroyuki Ochi},
year = {2021},
date = {2021-02-01},
booktitle = {Design, Automation and Test in Europe Conference (DATE)},
keywords = {Conference Papers},
pubstate = {published},
tppubtype = {inproceedings}
}
|
2020
|
30. | Shungo Kumazawa, Kazushi Kawamura, Thiem Van Chu, Masato Motomura, Jaehoon Yu ExtraFerns: Fully Parallel Ensemble Learning Technique with Non-Greedy yet Minimal Memory Access Training Proceedings Article In: International Symposium on Computing and Networking (CANDAR), 2020. @inproceedings{kumazawa-candar2020,
title = {ExtraFerns: Fully Parallel Ensemble Learning Technique with Non-Greedy yet Minimal Memory Access Training},
author = {Shungo Kumazawa and Kazushi Kawamura and Thiem Van Chu and Masato Motomura and Jaehoon Yu},
year = {2020},
date = {2020-11-24},
booktitle = {International Symposium on Computing and Networking (CANDAR)},
keywords = {Conference Papers},
pubstate = {published},
tppubtype = {inproceedings}
}
|
31. | Junnosuke Suzuki, Kota Ando, Kazutoshi Hirose, Kazushi Kawamura, Thiem Van Chu, Masato Motomura, Jaehoon Yu ProgressiveNN: Achieving Computational Scalability without Network Alteration by MSB-first Accumulative Computation Proceedings Article In: International Symposium on Computing and Networking (CANDAR), 2020. @inproceedings{suzuki-candar2020,
title = {ProgressiveNN: Achieving Computational Scalability without Network Alteration by MSB-first Accumulative Computation},
author = {Junnosuke Suzuki and Kota Ando and Kazutoshi Hirose and Kazushi Kawamura and Thiem Van Chu and Masato Motomura and Jaehoon Yu},
year = {2020},
date = {2020-11-24},
booktitle = {International Symposium on Computing and Networking (CANDAR)},
keywords = {Conference Papers},
pubstate = {published},
tppubtype = {inproceedings}
}
|
32. | Daichi Fujiki, Shunhao Wu, Nathan Ozog, Kush Goliya, David T. Blaauw, Satish Narayanasamy, Reetuparna Das [IEEE CS Tokyo/Japan Joint Local Chapters Young Author Award 2022] SeedEx: A Genome Sequencing Accelerator for Optimal Alignments in Subminimal Space Proceedings Article In: International Symposium on Microarchitecture (MICRO), 2020. @inproceedings{ieee-cs-award-2022,
title = {[IEEE CS Tokyo/Japan Joint Local Chapters Young Author Award 2022] SeedEx: A Genome Sequencing Accelerator for Optimal Alignments in Subminimal Space},
author = {Daichi Fujiki and Shunhao Wu and Nathan Ozog and Kush Goliya and David T. Blaauw and Satish Narayanasamy and Reetuparna Das},
year = {2020},
date = {2020-10-22},
urldate = {2020-10-22},
booktitle = {International Symposium on Microarchitecture (MICRO)},
keywords = {Awards, Conference Papers},
pubstate = {published},
tppubtype = {inproceedings}
}
|
33. | Ángel López García-Arias, Jaehoon Yu, Masanori Hashimoto Low-Cost Reservoir Computing using Cellular Automata and Random Forests Proceedings Article In: IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1-5, 2020. @inproceedings{reca-lopez-iscas2020,
title = {Low-Cost Reservoir Computing using Cellular Automata and Random Forests},
author = {Ángel López García-Arias and Jaehoon Yu and Masanori Hashimoto},
year = {2020},
date = {2020-10-10},
booktitle = {IEEE International Symposium on Circuits and Systems (ISCAS)},
pages = {1-5},
keywords = {Conference Papers},
pubstate = {published},
tppubtype = {inproceedings}
}
|
34. | Kota Shiba, Tatsuo Omori, Kodai Ueyoshi, Kota Ando, Kazutoshi Hirose, Shinya Takamaeda-Yamazaki, Masato Motomura, Mototsugu Hamada, Tadahiro Kuroda A 3D-Stacked SRAM Using Inductive Coupling with Low-Voltage Transmitter and 12:1 SerDes Proceedings Article In: IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1-5, 2020. @inproceedings{shiba-iscas2020,
title = {A 3D-Stacked SRAM Using Inductive Coupling with Low-Voltage Transmitter and 12:1 SerDes},
author = {Kota Shiba and Tatsuo Omori and Kodai Ueyoshi and Kota Ando and Kazutoshi Hirose and Shinya Takamaeda-Yamazaki and Masato Motomura and Mototsugu Hamada and Tadahiro Kuroda},
year = {2020},
date = {2020-10-10},
booktitle = {IEEE International Symposium on Circuits and Systems (ISCAS)},
pages = {1-5},
keywords = {Conference Papers},
pubstate = {published},
tppubtype = {inproceedings}
}
|
35. | Kazuki Onishi, Jaehoon Yu, Masanori Hashimoto Memory Efficient Training using Lookup-Table-based Quantization for Neural Network Proceedings Article In: IEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS), pp. 251–255, IEEE 2020. @inproceedings{onishi2020memory,
title = {Memory Efficient Training using Lookup-Table-based Quantization for Neural Network},
author = {Kazuki Onishi and Jaehoon Yu and Masanori Hashimoto},
year = {2020},
date = {2020-09-04},
booktitle = {IEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS)},
pages = {251--255},
organization = {IEEE},
keywords = {Conference Papers},
pubstate = {published},
tppubtype = {inproceedings}
}
|
36. | Taiga Ikeda, Kento Sakurada, Atsuyoshi Nakamura, Masato Motomura, Shinya Takamaeda-Yamazaki Hardware/Algorithm Co-optimization for Fully-Parallelized Compact Decision Tree Ensembles on FPGAs Proceedings Article In: International Symposium on Applied Reconfigurable Computing (ARC), Universidad de Castilla-La Mancha, Toledo, Spain, 2020. @inproceedings{Motomura-ARC-2020,
title = {Hardware/Algorithm Co-optimization for Fully-Parallelized Compact Decision Tree Ensembles on FPGAs},
author = {Taiga Ikeda and Kento Sakurada and Atsuyoshi Nakamura and Masato Motomura and Shinya Takamaeda-Yamazaki},
year = {2020},
date = {2020-04-01},
booktitle = {International Symposium on Applied Reconfigurable Computing (ARC)},
address = {Universidad de Castilla-La Mancha, Toledo, Spain},
keywords = {Conference Papers},
pubstate = {published},
tppubtype = {inproceedings}
}
|
37. | Masanori Hashimoto, Xu Bai, Naoki Banno, Munehiro Tada, Toshitsugu Sakamoto, Jaehoon Yu, Ryutaro Doi, Yusuke Araki, Hidetoshi Onodera, Takashi Imagawa, Hiroyuki Ochi, Kazutoshi Wakabayashi, Yukio Mitsuyama, Tadahiko Sugibayashi Via-Switch FPGA: 65nm CMOS Implementation and Architecture Extension for AI Applications Proceedings Article In: International Solid-State Circuits Conference (ISSCC), pp. 502–503, 2020. @inproceedings{id529,
title = {Via-Switch FPGA: 65nm CMOS Implementation and Architecture Extension for AI Applications},
author = {Masanori Hashimoto and Xu Bai and Naoki Banno and Munehiro Tada and Toshitsugu Sakamoto and Jaehoon Yu and Ryutaro Doi and Yusuke Araki and Hidetoshi Onodera and Takashi Imagawa and Hiroyuki Ochi and Kazutoshi Wakabayashi and Yukio Mitsuyama and Tadahiko Sugibayashi},
year = {2020},
date = {2020-02-17},
booktitle = {International Solid-State Circuits Conference (ISSCC)},
pages = {502--503},
keywords = {Conference Papers},
pubstate = {published},
tppubtype = {inproceedings}
}
|
38. | Kasho Yamamoto, Kota Ando, Normann Mertig, Takashi Takemoto, Masanao Yamaoka, Hiroshi Teramoto, Akira Sakai, Shinya Takamaeda-Yamazaki, Masato Motomura STATICA: A 512-Spin 0.25M-Weight Full-Digital Annealing Processor with a Near-Memory All-Spin-Updates-at-Once Architecture for Combinatorial Optimization with Complete Spin-Spin Interactions Proceedings Article In: International Solid-State Circuits Conference (ISSCC), pp. 138–139, 2020. @inproceedings{statica,
title = {STATICA: A 512-Spin 0.25M-Weight Full-Digital Annealing Processor with a Near-Memory All-Spin-Updates-at-Once Architecture for Combinatorial Optimization with Complete Spin-Spin Interactions},
author = {Kasho Yamamoto and Kota Ando and Normann Mertig and Takashi Takemoto and Masanao Yamaoka and Hiroshi Teramoto and Akira Sakai and Shinya Takamaeda-Yamazaki and Masato Motomura},
year = {2020},
date = {2020-02-17},
booktitle = {International Solid-State Circuits Conference (ISSCC)},
pages = {138--139},
keywords = {Conference Papers},
pubstate = {published},
tppubtype = {inproceedings}
}
|
39. | Thiem Van Chu, Kenji Kise, Kiyofumi Tanaka Dependency-Driven Trace-Based Network-on-Chip Emulation on FPGAs Proceedings Article In: ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA), pp. 211–221, 2020. @inproceedings{thiem-fpga2020,
title = {Dependency-Driven Trace-Based Network-on-Chip Emulation on FPGAs},
author = {Thiem Van Chu and Kenji Kise and Kiyofumi Tanaka},
year = {2020},
date = {2020-01-01},
booktitle = {ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA)},
pages = {211--221},
keywords = {Conference Papers},
pubstate = {published},
tppubtype = {inproceedings}
}
|
2019
|
40. | Prasoon Ambalathankandy, Yafei Ou, Jyotsna Kochiyil, Shinya Takamaeda-Yamazaki, Masato Motomura, Tetsuya Asai, Masayuki Ikebe Radiography Contrast Enhancement: Smoothed LHE Filter, a Practical Solution for Digital X-rays with Mach Band Proceedings Article In: International Conference on Digital Image Computing: Techniques and Applications, University of Western Australia, Perth, Australia, 2019. @inproceedings{Motomura-DICTA-2019,
title = {Radiography Contrast Enhancement: Smoothed LHE Filter, a Practical Solution for Digital X-rays with Mach Band},
author = {Prasoon Ambalathankandy and Yafei Ou and Jyotsna Kochiyil and Shinya Takamaeda-Yamazaki and Masato Motomura and Tetsuya Asai and Masayuki Ikebe},
year = {2019},
date = {2019-12-02},
booktitle = {International Conference on Digital Image Computing: Techniques and Applications},
address = {University of Western Australia, Perth, Australia},
keywords = {Conference Papers},
pubstate = {published},
tppubtype = {inproceedings}
}
|
41. | Yuki Hirayama, Tetsuya Asai, Masato Motomura, Shinya Takamaeda-Yamazaki A Resource-Efficient Weight Sampling Method for Bayesian Neural Networks Accelerators Proceedings Article In: International Symposium on Computing and Networking (CANDAR), 2019. @inproceedings{Motomura-CANDAR-2019,
title = {A Resource-Efficient Weight Sampling Method for Bayesian Neural Networks Accelerators},
author = {Yuki Hirayama and Tetsuya Asai and Masato Motomura and Shinya Takamaeda-Yamazaki},
year = {2019},
date = {2019-11-26},
booktitle = {International Symposium on Computing and Networking (CANDAR)},
keywords = {Conference Papers},
pubstate = {published},
tppubtype = {inproceedings}
}
|
42. | Shota Fukui, Jaehoon Yu, Masanori Hashimoto Distilling Knowledge for Non-Neural Networks Proceedings Article In: Asia-Pacific Signal and Information Processing Association (APSIPA), 2019. @inproceedings{2019-11-Fukui-APSIPA,
title = {Distilling Knowledge for Non-Neural Networks},
author = {Shota Fukui and Jaehoon Yu and Masanori Hashimoto},
year = {2019},
date = {2019-11-01},
booktitle = {Asia-Pacific Signal and Information Processing Association (APSIPA)},
keywords = {Conference Papers},
pubstate = {published},
tppubtype = {inproceedings}
}
|
43. | Toranosuke Tanio, Kouya Takeda, Jaehoon Yu, Masanori Hashimoto Training Data Reduction using Support Vectors for Neural Networks Proceedings Article In: Asia-Pacific Signal and Information Processing Association (APSIPA), 2019. @inproceedings{2019-11-Tanio-APSIPA,
title = {Training Data Reduction using Support Vectors for Neural Networks},
author = {Toranosuke Tanio and Kouya Takeda and Jaehoon Yu and Masanori Hashimoto},
year = {2019},
date = {2019-11-01},
booktitle = {Asia-Pacific Signal and Information Processing Association (APSIPA)},
keywords = {Conference Papers},
pubstate = {published},
tppubtype = {inproceedings}
}
|
44. | Yuka Oba, Kota Ando, Tetsuya Asai, Masato Motomura, Shinya Takamaeda-Yamazaki DeltaNet: Differential Binary Neural Network Proceedings Article In: IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP), New York, USA, 2019. @inproceedings{motomura_00039b,
title = {DeltaNet: Differential Binary Neural Network},
author = {Yuka Oba and Kota Ando and Tetsuya Asai and Masato Motomura and Shinya Takamaeda-Yamazaki},
year = {2019},
date = {2019-07-01},
booktitle = {IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP)},
address = {New York, USA},
keywords = {Conference Papers},
pubstate = {published},
tppubtype = {inproceedings}
}
|
45. | Koyo Minamikawa, Shinya Takamaeda-Yamazaki, Masayuki Ikebe, Masato Motomura, Tetsuya Asai FPGA-Based FORCE Learning Accelerator towards Real-Time Online Reservoir Computing Proceedings Article In: RISP International Workshop on Nonlinear Circuits, Communications and Signal Processing, Honolulu, USA, 2019. @inproceedings{motomura_00046b,
title = {FPGA-Based FORCE Learning Accelerator towards Real-Time Online Reservoir Computing},
author = {Koyo Minamikawa and Shinya Takamaeda-Yamazaki and Masayuki Ikebe and Masato Motomura and Tetsuya Asai},
year = {2019},
date = {2019-03-01},
booktitle = {RISP International Workshop on Nonlinear Circuits, Communications and Signal Processing},
address = {Honolulu, USA},
keywords = {Conference Papers},
pubstate = {published},
tppubtype = {inproceedings}
}
|
46. | Shunya Suzuki, Seunggoo Rim, Shinya Takamaeda-Yamazaki, Masayuki Ikebe, Masato Motomura, Tetsuya Asai Experimental Demonstration of Physical Reservoir Computing with Nonlinear Electronic Devices Proceedings Article In: RISP International Workshop on Nonlinear Circuits, Communications and Signal Processing, Honolulu, USA, 2019. @inproceedings{motomura_00045b,
title = {Experimental Demonstration of Physical Reservoir Computing with Nonlinear Electronic Devices},
author = {Shunya Suzuki and Seunggoo Rim and Shinya Takamaeda-Yamazaki and Masayuki Ikebe and Masato Motomura and Tetsuya Asai},
year = {2019},
date = {2019-03-01},
booktitle = {RISP International Workshop on Nonlinear Circuits, Communications and Signal Processing},
address = {Honolulu, USA},
keywords = {Conference Papers},
pubstate = {published},
tppubtype = {inproceedings}
}
|
47. | Tatsuya Kaneko, Masayuki Ikebe, Shinya Takamaeda-Yamazaki, Masato Motomura, Tetsuya Asai Hardware-Oriented Algorithm and Architecture for Generative Adversarial Networks Proceedings Article In: RISP International Workshop on Nonlinear Circuits, Communications and Signal Processing, Honolulu, USA, 2019. @inproceedings{motomura_00044b,
title = {Hardware-Oriented Algorithm and Architecture for Generative Adversarial Networks},
author = {Tatsuya Kaneko and Masayuki Ikebe and Shinya Takamaeda-Yamazaki and Masato Motomura and Tetsuya Asai},
year = {2019},
date = {2019-03-01},
booktitle = {RISP International Workshop on Nonlinear Circuits, Communications and Signal Processing},
address = {Honolulu, USA},
keywords = {Conference Papers},
pubstate = {published},
tppubtype = {inproceedings}
}
|
48. | Tatsuya Kaneko, Masayuki Ikebe, Shinya Takamaeda-Yamazaki, Masato Motomura, Tetsuya Asai Ternarized Backpropagation: A Hardware-Oriented Optimization Algorithm for Edge-Oriented AI Devices Proceedings Article In: RIEC International Symposium on Brain Functions and Brain Computer, Sendai, Japan, 2019. @inproceedings{motomura_00047,
title = {Ternarized Backpropagation: A Hardware-Oriented Optimization Algorithm for Edge-Oriented AI Devices},
author = {Tatsuya Kaneko and Masayuki Ikebe and Shinya Takamaeda-Yamazaki and Masato Motomura and Tetsuya Asai},
year = {2019},
date = {2019-02-01},
booktitle = {RIEC International Symposium on Brain Functions and Brain Computer},
address = {Sendai, Japan},
keywords = {Conference Papers},
pubstate = {published},
tppubtype = {inproceedings}
}
|
49. | Seunggoo Rim, Shunya Suzuki, Shinya Takamaeda-Yamazaki, Masayuki Ikebe, Masato Motomura, Tetsuya Asai Approach to Reservoir Computing with Schmitt Trigger Oscillator-Based Analog Neural Circuits Proceedings Article In: Japan-Korea Joint Workshop on Complex Communication Sciences, Pyengonchang, Korea, 2019. @inproceedings{motomura_00049,
title = {Approach to Reservoir Computing with Schmitt Trigger Oscillator-Based Analog Neural Circuits},
author = {Seunggoo Rim and Shunya Suzuki and Shinya Takamaeda-Yamazaki and Masayuki Ikebe and Masato Motomura and Tetsuya Asai},
year = {2019},
date = {2019-01-01},
booktitle = {Japan-Korea Joint Workshop on Complex Communication Sciences},
address = {Pyengonchang, Korea},
keywords = {Conference Papers},
pubstate = {published},
tppubtype = {inproceedings}
}
|
2018
|
50. | Prasoon Ambalathankandy, Takeshi Shimada, Shinya Takamaeda-Yamazaki, Masato Motomura, Tetsuya Asai, Masayuki Ikebe Analysis of Smoothed LHE Methods for Processing Images with Optical Illusions Proceedings Article In: IEEE International Conference on Visual Communications and Image Processing, Taichung, Taiwan, 2018. @inproceedings{motomura_00052,
title = {Analysis of Smoothed LHE Methods for Processing Images with Optical Illusions},
author = {Prasoon Ambalathankandy and Takeshi Shimada and Shinya Takamaeda-Yamazaki and Masato Motomura and Tetsuya Asai and Masayuki Ikebe},
year = {2018},
date = {2018-12-01},
booktitle = {IEEE International Conference on Visual Communications and Image Processing},
address = {Taichung, Taiwan},
keywords = {Conference Papers},
pubstate = {published},
tppubtype = {inproceedings}
}
|