2025
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1. | Hiroaki Ito, Jiale Yan, Hikari Otsuka, Kazushi Kawamura, Masato Motomura, Thiem Van Chu, Daichi Fujiki Uncovering Strong Lottery Tickets in Graph Transformers: A Path to Memory Efficient and Robust Graph Learning Journal Article In: Transactions on Machine Learning Research, 2025. @article{nokey,
title = {Uncovering Strong Lottery Tickets in Graph Transformers: A Path to Memory Efficient and Robust Graph Learning},
author = {Hiroaki Ito and Jiale Yan and Hikari Otsuka and Kazushi Kawamura and Masato Motomura and Thiem Van Chu and Daichi Fujiki},
year = {2025},
date = {2025-03-22},
urldate = {2025-03-22},
journal = {Transactions on Machine Learning Research},
keywords = {Journal Papers},
pubstate = {published},
tppubtype = {article}
}
|
2. | Hikari Otsuka, Daiki Chijiwa, 'Angel L'opez Garc'ia-Arias, Yasuyuki Okoshi, Kazushi Kawamura, Thiem Van Chu, Daichi Fujiki, Susumu Takeuchi, Masato Motomura Partially Frozen Random Networks Contain Compact Strong Lottery Tickets Journal Article In: Transactions on Machine Learning Research, 2025. @article{nokey,
title = {Partially Frozen Random Networks Contain Compact Strong Lottery Tickets},
author = {Hikari Otsuka and Daiki Chijiwa and {'A}ngel L{'o}pez Garc{'i}a-Arias and Yasuyuki Okoshi and Kazushi Kawamura and Thiem Van Chu and Daichi Fujiki and Susumu Takeuchi and Masato Motomura},
url = {https://openreview.net/forum?id=xpnPYfufhz},
year = {2025},
date = {2025-02-11},
journal = {Transactions on Machine Learning Research},
keywords = {Journal Papers},
pubstate = {published},
tppubtype = {article}
}
|
2024
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3. | Yuki Ichikawa, Kazushi Kawamura, Masato Motomura, Thiem Van Chu Efficient Stereo Visual Odometry on FPGA Featuring On-Chip Map Management and Pipelined Descriptor-Based Block Matching Journal Article In: IEEE Access, 2024. @article{nokey,
title = {Efficient Stereo Visual Odometry on FPGA Featuring On-Chip Map Management and Pipelined Descriptor-Based Block Matching},
author = {Yuki Ichikawa and Kazushi Kawamura and Masato Motomura and Thiem Van Chu },
year = {2024},
date = {2024-09-23},
urldate = {2024-09-23},
journal = {IEEE Access},
keywords = {Journal Papers},
pubstate = {published},
tppubtype = {article}
}
|
4. | Hikari Otsuka, Yasuyuki Okoshi, Ángel López García-Arias, Kazushi Kawamura, Thiem Van Chu, Daichi Fujiki, Masato Motomura Restricted Random Pruning at Initialization for High Compression Range Journal Article In: Transactions on Machine Learning Research (TMLR), 2024. @article{otsuka-tmlr-202405,
title = {Restricted Random Pruning at Initialization for High Compression Range},
author = {Hikari Otsuka and Yasuyuki Okoshi and Ángel López García-Arias and Kazushi Kawamura and Thiem Van Chu and Daichi Fujiki and Masato Motomura},
year = {2024},
date = {2024-05-01},
journal = {Transactions on Machine Learning Research (TMLR)},
keywords = {Journal Papers},
pubstate = {published},
tppubtype = {article}
}
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5. | Satoru Jimbo, Tatsuhiko Shirai, Nozomu Togawa, Masato Motomura, Kazushi Kawamura A GPU-Based Ising Machine With a Multi-Spin-Flip Capability for Constrained Combinatorial Optimization Journal Article In: IEEE Access, 2024. @article{ieee-access-jimbo-2024,
title = {A GPU-Based Ising Machine With a Multi-Spin-Flip Capability for Constrained Combinatorial Optimization},
author = {Satoru Jimbo and Tatsuhiko Shirai and Nozomu Togawa and Masato Motomura and Kazushi Kawamura},
year = {2024},
date = {2024-03-21},
journal = {IEEE Access},
keywords = {Journal Papers},
pubstate = {published},
tppubtype = {article}
}
|
6. | Shungo Kumazawa, Jaehoon Yu, Kazushi Kawamura, Thiem Van Chu, Masato Motomura Toward Improving Ensemble-Based Collaborative Inference at the Edge Journal Article In: IEEE Access, 2024. @article{ieee-access-kumazawa-2024,
title = {Toward Improving Ensemble-Based Collaborative Inference at the Edge},
author = {Shungo Kumazawa and Jaehoon Yu and Kazushi Kawamura and Thiem Van Chu and Masato Motomura},
year = {2024},
date = {2024-01-08},
urldate = {2024-01-08},
journal = {IEEE Access},
keywords = {Journal Papers},
pubstate = {published},
tppubtype = {article}
}
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2023
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7. | Junnosuke Suzuki, Jaehoon Yu, Mari Yasunaga, Ángel López García-Arias, Yasuyuki Okoshi, Shungo Kumazawa, Kota Ando, Kazushi Kawamura, Thiem Van Chu, Masato Motomura Pianissimo: A Sub-mW Class DNN Accelerator With Progressively Adjustable Bit-Precision Journal Article In: IEEE Access, 2023. @article{ieee-access-pianissimo,
title = {Pianissimo: A Sub-mW Class DNN Accelerator With Progressively Adjustable Bit-Precision},
author = {Junnosuke Suzuki and Jaehoon Yu and Mari Yasunaga and Ángel López García-Arias and Yasuyuki Okoshi and Shungo Kumazawa and Kota Ando and Kazushi Kawamura and Thiem Van Chu and Masato Motomura},
year = {2023},
date = {2023-12-26},
journal = {IEEE Access},
keywords = {Journal Papers},
pubstate = {published},
tppubtype = {article}
}
|
8. | Daiki Okonogi, Satoru Jimbo, Kota Ando, Thiem Van Chu, Jaehoon Yu, Masato Motomura, Kazushi Kawamura A Fully-Parallel Annealing Algorithm with Autonomous Pinning Effect Control for Various Combinatorial Optimization Problems Journal Article In: IEICE Transactions on Information and Systems, 2023. @article{ieice-d-2023-okonogi,
title = {A Fully-Parallel Annealing Algorithm with Autonomous Pinning Effect Control for Various Combinatorial Optimization Problems},
author = {Daiki Okonogi and Satoru Jimbo and Kota Ando and Thiem Van Chu and Jaehoon Yu and Masato Motomura and Kazushi Kawamura},
year = {2023},
date = {2023-12-01},
journal = {IEICE Transactions on Information and Systems},
keywords = {Journal Papers},
pubstate = {published},
tppubtype = {article}
}
|
9. | Bruno Hideki Fukushima-Kimura, Satoshi Handa, Katsuhiro Kamakura, Yoshinori Kamijima, Kazushi Kawamura, Akira Sakai Mixing time and simulated annealing for the stochastic cellular automata Journal Article In: Journal of Statistical Physics, vol. 190, no. 79, pp. 1-20, 2023. @article{bruno-journal-2023-2,
title = {Mixing time and simulated annealing for the stochastic cellular automata},
author = {Bruno Hideki Fukushima-Kimura and Satoshi Handa and Katsuhiro Kamakura and Yoshinori Kamijima and Kazushi Kawamura and Akira Sakai},
doi = {10.1007/s10955-023-03090-x},
year = {2023},
date = {2023-12-01},
journal = {Journal of Statistical Physics},
volume = {190},
number = {79},
pages = {1-20},
keywords = {Journal Papers},
pubstate = {published},
tppubtype = {article}
}
|
10. | Bruno Hideki Fukushima-Kimura, Yoshinori Kamijima, Kazushi Kawamura, Akira Sakai Stochastic optimization: Glauber dynamics versus stochastic cellular automata Journal Article In: Transactions of the Institute of Systems, Control and Information Engineers, vol. 36, no. 1, pp. 9-16, 2023. @article{bruno-journal-2023-1,
title = {Stochastic optimization: Glauber dynamics versus stochastic cellular automata},
author = {Bruno Hideki Fukushima-Kimura and Yoshinori Kamijima and Kazushi Kawamura and Akira Sakai},
doi = {10.5687/iscie.36.9},
year = {2023},
date = {2023-12-01},
journal = {Transactions of the Institute of Systems, Control and Information Engineers},
volume = {36},
number = {1},
pages = {9-16},
keywords = {Journal Papers},
pubstate = {published},
tppubtype = {article}
}
|
11. | Ángel López García-Arias, Yasuyuki Okoshi, Masanori Hashimoto, Masato Motomura, Jaehoon Yu Recurrent Residual Networks Contain Stronger Lottery Tickets Journal Article In: IEEE Access, vol. 11, pp. 16588-16604, 2023. @article{lopez-ieeeaccess2023,
title = {Recurrent Residual Networks Contain Stronger Lottery Tickets},
author = {Ángel López García-Arias and Yasuyuki Okoshi and Masanori Hashimoto and Masato Motomura and Jaehoon Yu},
doi = {10.1109/ACCESS.2023.3245808},
year = {2023},
date = {2023-02-15},
urldate = {2023-02-15},
journal = {IEEE Access},
volume = {11},
pages = {16588-16604},
keywords = {Journal Papers},
pubstate = {published},
tppubtype = {article}
}
|
12. | Jiale Yan, Kota Ando, Jaehoon Yu, Masato Motomura TT-MLP: Tensor Train Decomposition on Deep MLPs Journal Article In: IEEE Access, vol. 11, pp. 10398-10411, 2023. @article{jiale-ieeeaccess-2023,
title = {TT-MLP: Tensor Train Decomposition on Deep MLPs},
author = {Jiale Yan and Kota Ando and Jaehoon Yu and Masato Motomura},
doi = {10.1109/ACCESS.2023.3240784},
year = {2023},
date = {2023-01-30},
urldate = {2023-01-30},
journal = {IEEE Access},
volume = {11},
pages = {10398-10411},
keywords = {Journal Papers},
pubstate = {published},
tppubtype = {article}
}
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2022
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13. | Satoru Jimbo, Daiki Okonogi, Kota Ando, Thiem Van Chu, Jaehoon Yu, Masato Motomura, Kazushi Kawamura A Hybrid Integer Encoding Method for Obtaining High-quality Solutions of Quadratic Knapsack Problems on Solid-state Annealers Journal Article In: IEICE Transactions on Information and Systems, 2022. @article{ieice-d-2022-jimbo,
title = {A Hybrid Integer Encoding Method for Obtaining High-quality Solutions of Quadratic Knapsack Problems on Solid-state Annealers},
author = {Satoru Jimbo and Daiki Okonogi and Kota Ando and Thiem Van Chu and Jaehoon Yu and Masato Motomura and Kazushi Kawamura},
year = {2022},
date = {2022-12-01},
journal = {IEICE Transactions on Information and Systems},
keywords = {Journal Papers},
pubstate = {published},
tppubtype = {article}
}
|
14. | Masanori Hashimoto, X Bai, Naoki Banno, Munehiro Tada, Toshitsugu Sakamoto, Jaehoon Yu, Ryutaro Doi, Hidetoshi Onodera, Takashi Imagawa, Hiroyuki Ochi Via-switch FPGA with transistor-free programmability enabling energy-efficient near-memory parallel computation Journal Article In: Japanese Journal of Applied Physics, 2022. @article{viaswitch-fpga-physics,
title = {Via-switch FPGA with transistor-free programmability enabling energy-efficient near-memory parallel computation},
author = {Masanori Hashimoto and X Bai and Naoki Banno and Munehiro Tada and Toshitsugu Sakamoto and Jaehoon Yu and Ryutaro Doi and Hidetoshi Onodera and Takashi Imagawa and Hiroyuki Ochi},
doi = {10.35848/1347-4065/ac6b81},
year = {2022},
date = {2022-04-28},
journal = {Japanese Journal of Applied Physics},
keywords = {Journal Papers},
pubstate = {published},
tppubtype = {article}
}
|
2021
|
15. | Shungo Kumazawa, Kazushi Kawamura, Thiem Van Chu, Masato Motomura, Jaehoon Yu ExtraFerns: Fully Parallel Ensemble Learning Technique with Random Projection and Non-Greedy yet Minimal Memory Access Training Journal Article In: International Journal of Networking and Computing, vol. 11, no. 2, pp. 215-230, 2021. @article{kumazawa-ijnc-2021,
title = {ExtraFerns: Fully Parallel Ensemble Learning Technique with Random Projection and Non-Greedy yet Minimal Memory Access Training},
author = {Shungo Kumazawa and Kazushi Kawamura and Thiem Van Chu and Masato Motomura and Jaehoon Yu},
year = {2021},
date = {2021-07-08},
journal = {International Journal of Networking and Computing},
volume = {11},
number = {2},
pages = {215-230},
keywords = {Journal Papers},
pubstate = {published},
tppubtype = {article}
}
|
16. | Junnosuke Suzuki, Tomohiro Kaneko, Kota Ando, Kazutoshi Hirose, Kazushi Kawamura, Thiem Van Chu, Masato Motomura, Jaehoon Yu ProgressiveNN: Achieving Computational Scalability with Dynamic Bit-Precision Adjustment by MSB-first Accumulative Computation Journal Article In: International Journal of Networking and Computing, vol. 11, no. 2, pp. 338-353, 2021. @article{suzuki-ijnc-2021,
title = {ProgressiveNN: Achieving Computational Scalability with Dynamic Bit-Precision Adjustment by MSB-first Accumulative Computation},
author = {Junnosuke Suzuki and Tomohiro Kaneko and Kota Ando and Kazutoshi Hirose and Kazushi Kawamura and Thiem Van Chu and Masato Motomura and Jaehoon Yu},
year = {2021},
date = {2021-07-08},
journal = {International Journal of Networking and Computing},
volume = {11},
number = {2},
pages = {338-353},
keywords = {Journal Papers},
pubstate = {published},
tppubtype = {article}
}
|
17. | Kota Shiba, Tatsuo Omori, Kodai Ueyoshi, Kota Ando, Kazutoshi Hirose, Shinya Takamaeda-Yamazaki, Masato Motomura, Mototsugu Hamada, Tadahiro Kuroda A 96-MB 3D-Stacked SRAM Using Inductive Coupling with 0.4-V Transmitter, Termination Scheme and 12:1 SerDes in 40-nm CMOS Journal Article In: IEEE Transactions on Circuits and Systems I, vol. 68, no. 2, pp. 692-703, 2021. @article{shiba-ieeetcs2020,
title = {A 96-MB 3D-Stacked SRAM Using Inductive Coupling with 0.4-V Transmitter, Termination Scheme and 12:1 SerDes in 40-nm CMOS},
author = {Kota Shiba and Tatsuo Omori and Kodai Ueyoshi and Kota Ando and Kazutoshi Hirose and Shinya Takamaeda-Yamazaki and Masato Motomura and Mototsugu Hamada and Tadahiro Kuroda},
year = {2021},
date = {2021-02-01},
journal = {IEEE Transactions on Circuits and Systems I},
volume = {68},
number = {2},
pages = {692-703},
keywords = {Journal Papers},
pubstate = {published},
tppubtype = {article}
}
|
2020
|
18. | Kazutoshi Hirose, Shinya Takamaeda-Yamazaki, Jaehoon Yu, Masato Motomura Selective Fine-Tuning on a Classifier Ensemble: Realizing Adaptive Neural Networks With a Diversified Multi-Exit Architecture Journal Article In: IEEE Access, vol. 9, pp. 6179-6187, 2020. @article{hirose-ieee-access-2020,
title = {Selective Fine-Tuning on a Classifier Ensemble: Realizing Adaptive Neural Networks With a Diversified Multi-Exit Architecture},
author = {Kazutoshi Hirose and Shinya Takamaeda-Yamazaki and Jaehoon Yu and Masato Motomura},
year = {2020},
date = {2020-12-28},
journal = {IEEE Access},
volume = {9},
pages = {6179-6187},
keywords = {Journal Papers},
pubstate = {published},
tppubtype = {article}
}
|
19. | Kasho Yamamoto, Kazushi Kawamura, Kota Ando, Normann Mertig, Takashi Takemoto, Masanao Yamaoka, Hiroshi Teramoto, Akira Sakai, Shinya Takamaeda-Yamazaki, Masato Motomura STATICA: A 512-Spin 0.25M-Weight Annealing Processor With an All-Spin-Updates-at-Once Architecture for Combinatorial Optimization With Complete Spin-Spin Interactions Journal Article In: IEEE Journal of Solid-State Circuits (JSSC), 2020. @article{statica-jssc,
title = {STATICA: A 512-Spin 0.25M-Weight Annealing Processor With an All-Spin-Updates-at-Once Architecture for Combinatorial Optimization With Complete Spin-Spin Interactions},
author = {Kasho Yamamoto and Kazushi Kawamura and Kota Ando and Normann Mertig and Takashi Takemoto and Masanao Yamaoka and Hiroshi Teramoto and Akira Sakai and Shinya Takamaeda-Yamazaki and Masato Motomura},
year = {2020},
date = {2020-10-13},
journal = {IEEE Journal of Solid-State Circuits (JSSC)},
keywords = {Journal Papers},
pubstate = {published},
tppubtype = {article}
}
|
20. | Yuki Hirayama, Tetsuya Asai, Masato Motomura, Shinya Takamaeda-Yamazaki A Hardware-Efficient Weight Sampling Circuit for Bayesian Neural Networks Journal Article In: International Journal of Networking and Computing, vol. 10, 2020. @article{hirayama-ijnc2020,
title = {A Hardware-Efficient Weight Sampling Circuit for Bayesian Neural Networks},
author = {Yuki Hirayama and Tetsuya Asai and Masato Motomura and Shinya Takamaeda-Yamazaki},
year = {2020},
date = {2020-07-01},
journal = {International Journal of Networking and Computing},
volume = {10},
keywords = {Journal Papers},
pubstate = {published},
tppubtype = {article}
}
|
21. | Tai-Yu Cheng, Yukata Masuda, Jun Chen, Jaehoon Yu, Masanori Hashimoto Logarithm-Approximate Floating-Point Multiplier is Applicable to Power-Efficient Neural Network Training Journal Article In: Integration, vol. 74, pp. 19–31, 2020. @article{cheng2020logarithm,
title = {Logarithm-Approximate Floating-Point Multiplier is Applicable to Power-Efficient Neural Network Training},
author = {Tai-Yu Cheng and Yukata Masuda and Jun Chen and Jaehoon Yu and Masanori Hashimoto},
year = {2020},
date = {2020-05-14},
journal = {Integration},
volume = {74},
pages = {19--31},
keywords = {Journal Papers},
pubstate = {published},
tppubtype = {article}
}
|
22. | 本村 真人, 高前田 伸也, 植吉 晃大, 安藤 洸太, 廣瀨 一俊 深層ニューラルネットワーク向けプロセッサ技術の実例と展望 Journal Article In: 電子情報通信学会和文論文誌C, vol. J103-C, no. 05, 2020. @article{Motomura-IEICE-C-2020,
title = {深層ニューラルネットワーク向けプロセッサ技術の実例と展望},
author = {本村 真人 and 高前田 伸也 and 植吉 晃大 and 安藤 洸太 and 廣瀨 一俊},
year = {2020},
date = {2020-05-01},
journal = {電子情報通信学会和文論文誌C},
volume = {J103-C},
number = {05},
keywords = {Journal Papers},
pubstate = {published},
tppubtype = {article}
}
|
23. | Yafei Ou, Prasoon Ambalathankandy, Masayuki Ikebe, Shinya Takamaeda, Masato Motomura, Tetsuya Asai Real-time Tone Mapping: A State of the Art Report Journal Article In: IEEE Transactions on Circuits and Systems for Video Technology, 2020. @article{Motomura-TCSVT-2020,
title = {Real-time Tone Mapping: A State of the Art Report},
author = {Yafei Ou and Prasoon Ambalathankandy and Masayuki Ikebe and Shinya Takamaeda and Masato Motomura and Tetsuya Asai},
year = {2020},
date = {2020-01-01},
journal = {IEEE Transactions on Circuits and Systems for Video Technology},
keywords = {Journal Papers},
pubstate = {published},
tppubtype = {article}
}
|
2019
|
24. | Prasoon Ambalathankandy, Masayuki Ikebe, Takashi Yoshida, Takeshi Shimada, Shinya Takamaeda-Yamazaki, Masato Motomura, Tetsuya Asai An Adaptive Global and Local Tone Mapping Algorithm Implemented on FPGA Journal Article In: IEEE Transactions on Circuits and Systems for Video Technology, vol. 29, 2019. @article{motomura_00001,
title = {An Adaptive Global and Local Tone Mapping Algorithm Implemented on FPGA},
author = {Prasoon Ambalathankandy and Masayuki Ikebe and Takashi Yoshida and Takeshi Shimada and Shinya Takamaeda-Yamazaki and Masato Motomura and Tetsuya Asai},
year = {2019},
date = {2019-12-01},
journal = {IEEE Transactions on Circuits and Systems for Video Technology},
volume = {29},
keywords = {Journal Papers},
pubstate = {published},
tppubtype = {article}
}
|
25. | Kasho Yamamoto, Masayuki Ikebe, Tetsuya Asai, Masato Motomura, Shinya Takamaeda-Yamazaki FPGA-Based Annealing Processor with Time-Division Multiplexing Journal Article In: IEICE Transactions on Information and Systems, vol. E102, 2019. @article{motomura_00002,
title = {FPGA-Based Annealing Processor with Time-Division Multiplexing},
author = {Kasho Yamamoto and Masayuki Ikebe and Tetsuya Asai and Masato Motomura and Shinya Takamaeda-Yamazaki},
year = {2019},
date = {2019-12-01},
journal = {IEICE Transactions on Information and Systems},
volume = {E102},
keywords = {Journal Papers},
pubstate = {published},
tppubtype = {article}
}
|
26. | Kota Ando, Kodai Ueyoshi, Yuka Oba, Kazutoshi Hirose, Ryota Uematsu, Takumi Kudo, Masayuki Ikebe, Tetsuya Asai, Shinya Takamaeda-Yamazaki, Masato Motomura Dither NN: Hardware/Algorithm Co-Design for Accurate Quantized Neural Networks Journal Article In: IEICE Transactions on Information and Systems, vol. E102, 2019. @article{motomura_00003,
title = {Dither NN: Hardware/Algorithm Co-Design for Accurate Quantized Neural Networks},
author = {Kota Ando and Kodai Ueyoshi and Yuka Oba and Kazutoshi Hirose and Ryota Uematsu and Takumi Kudo and Masayuki Ikebe and Tetsuya Asai and Shinya Takamaeda-Yamazaki and Masato Motomura},
year = {2019},
date = {2019-12-01},
journal = {IEICE Transactions on Information and Systems},
volume = {E102},
keywords = {Journal Papers},
pubstate = {published},
tppubtype = {article}
}
|
27. | Tatsuya Kaneko, Kentaro Orimo, Itaru Hida, Shinya Takamaeda-Yamazaki, Masayuki Ikebe, Masato Motomura, Tetsuya Asai A Study on a Low Power Optimization Algorithm for An Edge-AI Device Journal Article In: Nonlinear Theory and Its Applications, vol. E10-N, no. 4, 2019. @article{motomura_00004,
title = {A Study on a Low Power Optimization Algorithm for An Edge-AI Device},
author = {Tatsuya Kaneko and Kentaro Orimo and Itaru Hida and Shinya Takamaeda-Yamazaki and Masayuki Ikebe and Masato Motomura and Tetsuya Asai},
year = {2019},
date = {2019-10-01},
journal = {Nonlinear Theory and Its Applications},
volume = {E10-N},
number = {4},
keywords = {Journal Papers},
pubstate = {published},
tppubtype = {article}
}
|
28. | Tatsuya Kaneko, Masayuki Ikebe, Shinya Takamaeda-Yamazaki, Masato Motomura, Tetsuya Asai Hardware-Oriented Algorithm and Architecture for Generative Adversarial Networks Journal Article In: Journal of Signal Processing, vol. 23, no. 4, pp. 151-154, 2019. @article{motomura_00005,
title = {Hardware-Oriented Algorithm and Architecture for Generative Adversarial Networks},
author = {Tatsuya Kaneko and Masayuki Ikebe and Shinya Takamaeda-Yamazaki and Masato Motomura and Tetsuya Asai},
year = {2019},
date = {2019-07-01},
journal = {Journal of Signal Processing},
volume = {23},
number = {4},
pages = {151-154},
keywords = {Journal Papers},
pubstate = {published},
tppubtype = {article}
}
|
29. | Kodai Ueyoshi, Kota Ando, Kazutoshi Hirose, Shinya Takamaeda-Yamazaki, Mototsugu Hamada, Tadahiro Kuroda, Masato Motomura QUEST: Multi-Purpose Log-Quantized DNN Inference Engine Stacked on 96-MB 3-D SRAM Using Inductive Coupling Technology in 40-nm CMOS Journal Article In: IEEE Journal of Solid-State Circuits, vol. 54, no. 1, pp. 186-196, 2019. @article{motomura_00006,
title = {QUEST: Multi-Purpose Log-Quantized DNN Inference Engine Stacked on 96-MB 3-D SRAM Using Inductive Coupling Technology in 40-nm CMOS},
author = {Kodai Ueyoshi and Kota Ando and Kazutoshi Hirose and Shinya Takamaeda-Yamazaki and Mototsugu Hamada and Tadahiro Kuroda and Masato Motomura},
year = {2019},
date = {2019-01-01},
journal = {IEEE Journal of Solid-State Circuits},
volume = {54},
number = {1},
pages = {186-196},
keywords = {Journal Papers},
pubstate = {published},
tppubtype = {article}
}
|
30. | Salita Sombatsiri, Seiya Shibata, Yuki Kobayashi, Hiroaki Inoue, Takashi Takenaka, Takeo Hosomi, Jaehoon Yu, Yoshinori Takeuchi Parallelism-Flexible Convolution Core for Sparse Convolutional Neural Networks on FPGA Journal Article In: vol. 12, pp. 22–37, 2019. @article{sombatsiri2019parallelism,
title = {Parallelism-Flexible Convolution Core for Sparse Convolutional Neural Networks on FPGA},
author = {Salita Sombatsiri and Seiya Shibata and Yuki Kobayashi and Hiroaki Inoue and Takashi Takenaka and Takeo Hosomi and Jaehoon Yu and Yoshinori Takeuchi},
year = {2019},
date = {2019-01-01},
volume = {12},
pages = {22--37},
keywords = {Journal Papers},
pubstate = {published},
tppubtype = {article}
}
|
31. | Thiem Van Chu, Kenji Kise LEF: An Effective Routing Algorithm for Two-Dimensional Meshes Journal Article In: IEICE Transactions on Information and Systems, vol. E102-D, no. 10, pp. 1925–1941, 2019. @article{thiem-ieice2019,
title = {LEF: An Effective Routing Algorithm for Two-Dimensional Meshes},
author = {Thiem Van Chu and Kenji Kise},
year = {2019},
date = {2019-01-01},
journal = {IEICE Transactions on Information and Systems},
volume = {E102-D},
number = {10},
pages = {1925--1941},
keywords = {Journal Papers},
pubstate = {published},
tppubtype = {article}
}
|
32. | Ryutaro Doi, Jaehoon Yu, Masanori Hashimoto Sneak Path Free Reconfiguration with Minimized Programming Steps for Via-switch Crossbar Based FPGA Journal Article In: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, pp. 1-1, 2019, ISSN: 1937-4151. @article{8935433,
title = {Sneak Path Free Reconfiguration with Minimized Programming Steps for Via-switch Crossbar Based FPGA},
author = {Ryutaro Doi and Jaehoon Yu and Masanori Hashimoto},
issn = {1937-4151},
year = {2019},
date = {2019-01-01},
journal = {IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems},
pages = {1-1},
keywords = {Journal Papers},
pubstate = {published},
tppubtype = {article}
}
|
2018
|
33. | Prasoon Ambalathankandy, Shinya Takamaeda-Yamazaki, Masato Motomura, Tetsuya Asai, Masayuki Ikebe, Hotaka Kusano Real-time HDTV to 4K and 8K-UHD Conversions Using Anti-Aliasing Based Super Resolution Algorithm on FPGA Journal Article In: Microprocessors and Microsystems, vol. 60, 2018. @article{motomura_00007,
title = {Real-time HDTV to 4K and 8K-UHD Conversions Using Anti-Aliasing Based Super Resolution Algorithm on FPGA},
author = {Prasoon Ambalathankandy and Shinya Takamaeda-Yamazaki and Masato Motomura and Tetsuya Asai and Masayuki Ikebe and Hotaka Kusano},
year = {2018},
date = {2018-12-01},
journal = {Microprocessors and Microsystems},
volume = {60},
keywords = {Journal Papers},
pubstate = {published},
tppubtype = {article}
}
|
34. | Kazutoshi Hirose, Ryota Uematsu, Kota Ando, Kodai Ueyoshi, Masayuki Ikebe, Tetsuya Asai, Masato Motomura, Shinya Takamaeda-Yamazaki Quantization Error-Based Regularization for Hardware-Aware Neural Network Training Journal Article In: Nonlinear Theory and Its Applications, vol. E9-N, no. 4, pp. 453-465, 2018. @article{motomura_00008,
title = {Quantization Error-Based Regularization for Hardware-Aware Neural Network Training},
author = {Kazutoshi Hirose and Ryota Uematsu and Kota Ando and Kodai Ueyoshi and Masayuki Ikebe and Tetsuya Asai and Masato Motomura and Shinya Takamaeda-Yamazaki},
year = {2018},
date = {2018-10-01},
journal = {Nonlinear Theory and Its Applications},
volume = {E9-N},
number = {4},
pages = {453-465},
keywords = {Journal Papers},
pubstate = {published},
tppubtype = {article}
}
|
35. | Kota Ando, Kodai Ueyoshi, Kentaro Orimo, Haruyoshi Yonekawa, Shimpei Sato, Hiroki Nakahara, Shinya Takamaeda-Yamazaki, Masayuki Ikebe, Tetsuya Asai, Tadahiro Kuroda, Masato Motomura BRein Memory: A Single-Chip Binary/Ternary Reconfigurable In-Memory Deep Neural Network Accelerator Achieving 1.4TOPS at 0.6W Journal Article In: IEEE Journal of Solid-State Circuits, vol. 53, no. 4, pp. 983-994, 2018. @article{motomura_00009,
title = {BRein Memory: A Single-Chip Binary/Ternary Reconfigurable In-Memory Deep Neural Network Accelerator Achieving 1.4TOPS at 0.6W},
author = {Kota Ando and Kodai Ueyoshi and Kentaro Orimo and Haruyoshi Yonekawa and Shimpei Sato and Hiroki Nakahara and Shinya Takamaeda-Yamazaki and Masayuki Ikebe and Tetsuya Asai and Tadahiro Kuroda and Masato Motomura},
year = {2018},
date = {2018-04-01},
journal = {IEEE Journal of Solid-State Circuits},
volume = {53},
number = {4},
pages = {983-994},
keywords = {Journal Papers},
pubstate = {published},
tppubtype = {article}
}
|
36. | Aoi Tanibata, Alexandre Schmid, Shinya Takamaeda-Yamazaki, Masayuki Ikebe, Masato Motomura, Tetsuya Asai Proto-Computing Architecture over A Digital Medium Aiming at Real-Time Video Processing Journal Article In: Complexity, vol. 2018, pp. 3618621-1-11, 2018. @article{motomura_00010,
title = {Proto-Computing Architecture over A Digital Medium Aiming at Real-Time Video Processing},
author = {Aoi Tanibata and Alexandre Schmid and Shinya Takamaeda-Yamazaki and Masayuki Ikebe and Masato Motomura and Tetsuya Asai},
year = {2018},
date = {2018-02-01},
journal = {Complexity},
volume = {2018},
pages = {3618621-1-11},
keywords = {Journal Papers},
pubstate = {published},
tppubtype = {article}
}
|
37. | Tomoki Sugiura, Jaehoon Yu, Yoshinori Takeuchi Phase Locking Value Calculator based on Hardware-oriented Mathematical Expression Journal Article In: vol. 101, no. 12, pp. 2254–2261, 2018. @article{sugiura2018phase,
title = {Phase Locking Value Calculator based on Hardware-oriented Mathematical Expression},
author = {Tomoki Sugiura and Jaehoon Yu and Yoshinori Takeuchi},
year = {2018},
date = {2018-01-01},
volume = {101},
number = {12},
pages = {2254--2261},
keywords = {Journal Papers},
pubstate = {published},
tppubtype = {article}
}
|
38. | Koichi Mitsunari, Yoshinori Takeuchi, Masaharu Imai, Jaehoon Yu Decomposed Vector Histograms of Oriented Gradients for Efficient Hardware Implementation Journal Article In: IEICE_J_FECACS, vol. 101, no. 11, pp. 1766–1775, 2018, ((被引用件数: 1)). @article{mitsunari2018decomposed,
title = {Decomposed Vector Histograms of Oriented Gradients for Efficient Hardware Implementation},
author = {Koichi Mitsunari and Yoshinori Takeuchi and Masaharu Imai and Jaehoon Yu},
year = {2018},
date = {2018-01-01},
journal = {IEICE_J_FECACS},
volume = {101},
number = {11},
pages = {1766--1775},
note = {(被引用件数: 1)},
keywords = {Journal Papers},
pubstate = {published},
tppubtype = {article}
}
|
39. | Hiroyuki Ochi, Kosei Yamaguchi, Tetsuaki Fujimoto, Junshi Hotate, Takashi Kishimoto, Toshiki Higashi, Takashi Imagawa, Ryutaro Doi, Munehiro Tada, Tadahiko Sugibayashi, Wataru Takahashi, Kazutoshi Wakabayashi, Hidetoshi Onodera, Yukio Mitsuyama, Jaehoon Yu, Masanori Hashimoto Via-Switch FPGA: Highly Dense Mixed-Grained Reconfigurable Architecture with Overlay Via-Switch Crossbars Journal Article In: no. 99, pp. 1–14, 2018, ((IF: 1.744, 被引用件数: 3)). @article{ochi2018via,
title = {Via-Switch FPGA: Highly Dense Mixed-Grained Reconfigurable Architecture with Overlay Via-Switch Crossbars},
author = {Hiroyuki Ochi and Kosei Yamaguchi and Tetsuaki Fujimoto and Junshi Hotate and Takashi Kishimoto and Toshiki Higashi and Takashi Imagawa and Ryutaro Doi and Munehiro Tada and Tadahiko Sugibayashi and Wataru Takahashi and Kazutoshi Wakabayashi and Hidetoshi Onodera and Yukio Mitsuyama and Jaehoon Yu and Masanori Hashimoto},
year = {2018},
date = {2018-01-01},
number = {99},
pages = {1--14},
note = {(IF: 1.744, 被引用件数: 3)},
keywords = {Journal Papers},
pubstate = {published},
tppubtype = {article}
}
|
40. | Koichi Mitsunari, Jaehoon Yu, Takao Onoye, Masanori Hashimoto Hardware Architecture for High-Speed Object Detection Using Decision Tree Ensemble Journal Article In: IEICE_J_FECACS, vol. 101, no. 9, pp. 1298–1307, 2018, ((被引用件数: 1)). @article{mitsunari2018hardware,
title = {Hardware Architecture for High-Speed Object Detection Using Decision Tree Ensemble},
author = {Koichi Mitsunari and Jaehoon Yu and Takao Onoye and Masanori Hashimoto},
year = {2018},
date = {2018-01-01},
journal = {IEICE_J_FECACS},
volume = {101},
number = {9},
pages = {1298--1307},
note = {(被引用件数: 1)},
keywords = {Journal Papers},
pubstate = {published},
tppubtype = {article}
}
|
2017
|
41. | Takuto Tsuji, Masayuki Ikebe, Shinya Takamaeda-Yamazaki, Masato Motomura, Tetsuya Asai 6-DoF Camera Position and Posture Estimation Based on Local Patches of Image Sequence Journal Article In: Journal of Signal Processing, vol. 21, no. 4, pp. 191-194, 2017. @article{motomura_00011,
title = {6-DoF Camera Position and Posture Estimation Based on Local Patches of Image Sequence},
author = {Takuto Tsuji and Masayuki Ikebe and Shinya Takamaeda-Yamazaki and Masato Motomura and Tetsuya Asai},
year = {2017},
date = {2017-07-01},
journal = {Journal of Signal Processing},
volume = {21},
number = {4},
pages = {191-194},
keywords = {Journal Papers},
pubstate = {published},
tppubtype = {article}
}
|
42. | Kota Ando, Shinya Takamaeda-Yamazaki, Masayuki Ikebe, Tetsuya Asai, Masato Motomura A Multithreaded CGRA for Convolutional Neural Network Processing Journal Article In: Circuits and Systems, vol. 8, no. 6, pp. 149-170, 2017. @article{motomura_00012,
title = {A Multithreaded CGRA for Convolutional Neural Network Processing},
author = {Kota Ando and Shinya Takamaeda-Yamazaki and Masayuki Ikebe and Tetsuya Asai and Masato Motomura},
year = {2017},
date = {2017-06-01},
journal = {Circuits and Systems},
volume = {8},
number = {6},
pages = {149-170},
keywords = {Journal Papers},
pubstate = {published},
tppubtype = {article}
}
|
43. | Itaru Hida, Shinya Takamaeda-Yamazaki, Masayuki Ikebe, Masato Motomura, Tetsuya Asai A High Performance and Energy Efficient Microprocessor with a Novel Restricted Dynamically Reconfigurable Accelerator Journal Article In: Circuits and Systems, vol. 8, no. 5, pp. 134-147, 2017. @article{motomura_00014,
title = {A High Performance and Energy Efficient Microprocessor with a Novel Restricted Dynamically Reconfigurable Accelerator},
author = {Itaru Hida and Shinya Takamaeda-Yamazaki and Masayuki Ikebe and Masato Motomura and Tetsuya Asai},
year = {2017},
date = {2017-05-01},
journal = {Circuits and Systems},
volume = {8},
number = {5},
pages = {134-147},
keywords = {Journal Papers},
pubstate = {published},
tppubtype = {article}
}
|
44. | Itaru Hida, Shinya Takamaeda-Yamazaki, Masayuki Ikebe, Masato Motomura, Tetsuya Asai An Energy-Efficient Dynamic Branch Predictor with a Two-Clock-Cycle Naive Bayes Classifier for Pipelined RISC Microprocessors Journal Article In: Nonlinear Theory and Its Applications, vol. E8-N, no. 3, pp. 235-245, 2017. @article{motomura_00013,
title = {An Energy-Efficient Dynamic Branch Predictor with a Two-Clock-Cycle Naive Bayes Classifier for Pipelined RISC Microprocessors},
author = {Itaru Hida and Shinya Takamaeda-Yamazaki and Masayuki Ikebe and Masato Motomura and Tetsuya Asai},
year = {2017},
date = {2017-05-01},
journal = {Nonlinear Theory and Its Applications},
volume = {E8-N},
number = {3},
pages = {235-245},
keywords = {Journal Papers},
pubstate = {published},
tppubtype = {article}
}
|
45. | Takao Marukame, Kodai Ueyoshi, Tetsuya Asai, Masato Motomura, Alexandre Schmid, Masamichi Suzuki, Yusuke Higashi, Yuichiro Mitani Error Tolerance Analysis of Deep Learning Hardware Using Restricted Boltzmann Machine towards Low-Power Memory Implementation Journal Article In: IEEE Transactions on Circuits and Systems II, vol. 64, no. 4, pp. 462-466, 2017. @article{motomura_00015,
title = {Error Tolerance Analysis of Deep Learning Hardware Using Restricted Boltzmann Machine towards Low-Power Memory Implementation},
author = {Takao Marukame and Kodai Ueyoshi and Tetsuya Asai and Masato Motomura and Alexandre Schmid and Masamichi Suzuki and Yusuke Higashi and Yuichiro Mitani},
year = {2017},
date = {2017-04-01},
journal = {IEEE Transactions on Circuits and Systems II},
volume = {64},
number = {4},
pages = {462-466},
keywords = {Journal Papers},
pubstate = {published},
tppubtype = {article}
}
|
46. | Thiem Van Chu, Shimpei Sato, Kenji Kise Fast and Cycle-Accurate Emulation of Large-Scale Networks-on-Chip Using a Single FPGA Journal Article In: ACM Transactions on Reconfigurable Technology and Systems (TRETS), vol. 10, no. 4, pp. 27:1–27:27, 2017. @article{thiem-acmtrets2017,
title = {Fast and Cycle-Accurate Emulation of Large-Scale Networks-on-Chip Using a Single FPGA},
author = {Thiem Van Chu and Shimpei Sato and Kenji Kise},
year = {2017},
date = {2017-01-01},
journal = {ACM Transactions on Reconfigurable Technology and Systems (TRETS)},
volume = {10},
number = {4},
pages = {27:1--27:27},
keywords = {Journal Papers},
pubstate = {published},
tppubtype = {article}
}
|
47. | Yuuka Hirao, Yoshinori Takeuchi, Masaharu Imai, Jaehoon Yu Deformable Part Model Based Arrhythmia Detection Using Time Domain Features Journal Article In: IEICE_J_FECACS, vol. 100, no. 11, pp. 2221–2229, 2017. @article{hirao2017deformable,
title = {Deformable Part Model Based Arrhythmia Detection Using Time Domain Features},
author = {Yuuka Hirao and Yoshinori Takeuchi and Masaharu Imai and Jaehoon Yu},
year = {2017},
date = {2017-01-01},
journal = {IEICE_J_FECACS},
volume = {100},
number = {11},
pages = {2221--2229},
keywords = {Journal Papers},
pubstate = {published},
tppubtype = {article}
}
|
48. | Tomoki Sugiura, Masaharu Imai, Jaehoon Yu, Yoshinori Takeuchi A Low-Energy Application Specific Instruction-Set Processor towards a Low-Computational Lossless Compression Method for Stimuli Position Data of Artificial Vision Systems Journal Article In: vol. 25, pp. 210–219, 2017, ((IF: 0.77, 被引用件数: 2)). @article{sugiura2017low,
title = {A Low-Energy Application Specific Instruction-Set Processor towards a Low-Computational Lossless Compression Method for Stimuli Position Data of Artificial Vision Systems},
author = {Tomoki Sugiura and Masaharu Imai and Jaehoon Yu and Yoshinori Takeuchi},
year = {2017},
date = {2017-01-01},
volume = {25},
pages = {210--219},
note = {(IF: 0.77, 被引用件数: 2)},
keywords = {Journal Papers},
pubstate = {published},
tppubtype = {article}
}
|
2016
|
49. | Kasho Yamamoto, Masayuki Ikebe, Tetsuya Asai, Masato Motomura FPGA-Based Stream Processing for Frequent Itemset Mining with Incremental Multiple Hashes Journal Article In: Circuits and Systems, vol. 7, no. 10, pp. 3299-3309, 2016. @article{motomura_00016,
title = {FPGA-Based Stream Processing for Frequent Itemset Mining with Incremental Multiple Hashes},
author = {Kasho Yamamoto and Masayuki Ikebe and Tetsuya Asai and Masato Motomura},
year = {2016},
date = {2016-08-01},
journal = {Circuits and Systems},
volume = {7},
number = {10},
pages = {3299-3309},
keywords = {Journal Papers},
pubstate = {published},
tppubtype = {article}
}
|
50. | Kodai Ueyoshi, Takao Marukame, Tetsuya Asai, Masato Motomura, Alexandre Schmid FPGA Implementation of A Scalable and Highly Parallel Architecture for Restricted Boltzmann Machines Journal Article In: Circuits and Systems, vol. 7, no. 9, pp. 2132-2141, 2016. @article{motomura_00017,
title = {FPGA Implementation of A Scalable and Highly Parallel Architecture for Restricted Boltzmann Machines},
author = {Kodai Ueyoshi and Takao Marukame and Tetsuya Asai and Masato Motomura and Alexandre Schmid},
year = {2016},
date = {2016-07-01},
journal = {Circuits and Systems},
volume = {7},
number = {9},
pages = {2132-2141},
keywords = {Journal Papers},
pubstate = {published},
tppubtype = {article}
}
|