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252 entries « 1 of 6 »

2021

1.

Kota Ando, Jaehoon Yu, Kazutoshi Hirose, Hiroki Nakahara, Kazushi Kawamura, Thiem Van Chu, Masato Motomura

Edge Inference Engine for Deep & Random Sparse Neural Networks with 4-bit Cartesian-Product MAC Array and Pipelined Activation Aligner Inproceedings

In: Hot Chips 33 (Poster), 2021.

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2.

Takashi Imagawa, Jaehoon Yu, Masanori Hashimoto, Hiroyuki Ochi

MUX Granularity-Oriented Iterative Technology Mapping for Implementing Compute-Intensive Applications on Via-Switch FPGA Inproceedings

In: Design, Automation and Test in Europe Conference (DATE), 2021.

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2020

3.

Junnosuke Suzuki, Kota Ando, Kazutoshi Hirose, Kazushi Kawamura, Thiem Van Chu, Masato Motomura, Jaehoon Yu

ProgressiveNN: Achieving Computational Scalability without Network Alteration by MSB-first Accumulative Computation Inproceedings

In: International Symposium on Computing and Networking (CANDAR), 2020.

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4.

Shungo Kumazawa, Kazushi Kawamura, Thiem Van Chu, Masato Motomura, Jaehoon Yu

ExtraFerns: Fully Parallel Ensemble Learning Technique with Non-Greedy yet Minimal Memory Access Training Inproceedings

In: International Symposium on Computing and Networking (CANDAR), 2020.

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5.

Kota Shiba, Tatsuo Omori, Kodai Ueyoshi, Kota Ando, Kazutoshi Hirose, Shinya Takamaeda-Yamazaki, Masato Motomura, Mototsugu Hamada, Tadahiro Kuroda

A 3D-Stacked SRAM Using Inductive Coupling with Low-Voltage Transmitter and 12:1 SerDes Inproceedings

In: IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1-5, 2020.

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6.

Ángel López García-Arias, Jaehoon Yu, Masanori Hashimoto

Low-Cost Reservoir Computing using Cellular Automata and Random Forests Inproceedings

In: IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1-5, 2020.

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7.

Kazuki Onishi, Jaehoon Yu, Masanori Hashimoto

Memory Efficient Training using Lookup-Table-based Quantization for Neural Network Inproceedings

In: IEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS), pp. 251–255, IEEE 2020.

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8.

Taiga Ikeda, Kento Sakurada, Atsuyoshi Nakamura, Masato Motomura, Shinya Takamaeda-Yamazaki

Hardware/Algorithm Co-optimization for Fully-Parallelized Compact Decision Tree Ensembles on FPGAs Inproceedings

In: International Symposium on Applied Reconfigurable Computing (ARC), Universidad de Castilla-La Mancha, Toledo, Spain, 2020.

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9.

Masanori Hashimoto, Xu Bai, Naoki Banno, Munehiro Tada, Toshitsugu Sakamoto, Jaehoon Yu, Ryutaro Doi, Yusuke Araki, Hidetoshi Onodera, Takashi Imagawa, Hiroyuki Ochi, Kazutoshi Wakabayashi, Yukio Mitsuyama, Tadahiko Sugibayashi

Via-Switch FPGA: 65nm CMOS Implementation and Architecture Extension for AI Applications Inproceedings

In: International Solid-State Circuits Conference (ISSCC), pp. 502–503, 2020.

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10.

Kasho Yamamoto, Kota Ando, Normann Mertig, Takashi Takemoto, Masanao Yamaoka, Hiroshi Teramoto, Akira Sakai, Shinya Takamaeda-Yamazaki, Masato Motomura

STATICA: A 512-Spin 0.25M-Weight Full-Digital Annealing Processor with a Near-Memory All-Spin-Updates-at-Once Architecture for Combinatorial Optimization with Complete Spin-Spin Interactions Inproceedings

In: International Solid-State Circuits Conference (ISSCC), pp. 138–139, 2020.

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11.

Thiem Van Chu, Kenji Kise, Kiyofumi Tanaka

Dependency-Driven Trace-Based Network-on-Chip Emulation on FPGAs Inproceedings

In: ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA), pp. 211–221, 2020.

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2019

12.

Prasoon Ambalathankandy, Yafei Ou, Jyotsna Kochiyil, Shinya Takamaeda-Yamazaki, Masato Motomura, Tetsuya Asai, Masayuki Ikebe

Radiography Contrast Enhancement: Smoothed LHE Filter, a Practical Solution for Digital X-rays with Mach Band Inproceedings

In: International Conference on Digital Image Computing: Techniques and Applications, University of Western Australia, Perth, Australia, 2019.

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13.

Yuki Hirayama, Tetsuya Asai, Masato Motomura, Shinya Takamaeda-Yamazaki

A Resource-Efficient Weight Sampling Method for Bayesian Neural Networks Accelerators Inproceedings

In: International Symposium on Computing and Networking (CANDAR), 2019.

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14.

Toranosuke Tanio, Kouya Takeda, Jaehoon Yu, Masanori Hashimoto

Training Data Reduction using Support Vectors for Neural Networks Inproceedings

In: Asia-Pacific Signal and Information Processing Association (APSIPA), 2019.

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15.

Shota Fukui, Jaehoon Yu, Masanori Hashimoto

Distilling Knowledge for Non-Neural Networks Inproceedings

In: Asia-Pacific Signal and Information Processing Association (APSIPA), 2019.

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16.

Yuka Oba, Kota Ando, Tetsuya Asai, Masato Motomura, Shinya Takamaeda-Yamazaki

DeltaNet: Differential Binary Neural Network Inproceedings

In: IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP), New York, USA, 2019.

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17.

Tatsuya Kaneko, Masayuki Ikebe, Shinya Takamaeda-Yamazaki, Masato Motomura, Tetsuya Asai

Hardware-Oriented Algorithm and Architecture for Generative Adversarial Networks Inproceedings

In: RISP International Workshop on Nonlinear Circuits, Communications and Signal Processing, Honolulu, USA, 2019.

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18.

Shunya Suzuki, Seunggoo Rim, Shinya Takamaeda-Yamazaki, Masayuki Ikebe, Masato Motomura, Tetsuya Asai

Experimental Demonstration of Physical Reservoir Computing with Nonlinear Electronic Devices Inproceedings

In: RISP International Workshop on Nonlinear Circuits, Communications and Signal Processing, Honolulu, USA, 2019.

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19.

Koyo Minamikawa, Shinya Takamaeda-Yamazaki, Masayuki Ikebe, Masato Motomura, Tetsuya Asai

FPGA-Based FORCE Learning Accelerator towards Real-Time Online Reservoir Computing Inproceedings

In: RISP International Workshop on Nonlinear Circuits, Communications and Signal Processing, Honolulu, USA, 2019.

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20.

Tatsuya Kaneko, Masayuki Ikebe, Shinya Takamaeda-Yamazaki, Masato Motomura, Tetsuya Asai

Ternarized Backpropagation: A Hardware-Oriented Optimization Algorithm for Edge-Oriented AI Devices Inproceedings

In: RIEC International Symposium on Brain Functions and Brain Computer, Sendai, Japan, 2019.

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21.

Seunggoo Rim, Shunya Suzuki, Shinya Takamaeda-Yamazaki, Masayuki Ikebe, Masato Motomura, Tetsuya Asai

Approach to Reservoir Computing with Schmitt Trigger Oscillator-Based Analog Neural Circuits Inproceedings

In: Japan-Korea Joint Workshop on Complex Communication Sciences, Pyengonchang, Korea, 2019.

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2018

22.

Prasoon Ambalathankandy, Takeshi Shimada, Shinya Takamaeda-Yamazaki, Masato Motomura, Tetsuya Asai, Masayuki Ikebe

Analysis of Smoothed LHE Methods for Processing Images with Optical Illusions Inproceedings

In: IEEE International Conference on Visual Communications and Image Processing, Taichung, Taiwan, 2018.

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23.

Kota Ando, Kodai Ueyoshi, Yuka Oba, Kazutoshi Hirose, Ryota Uematsu, Takumi Kudo, Masayuki Ikebe, Tetsuya Asai, Shinya Takamaeda-Yamazaki, Masato Motomura

Dither NN: An Accurate Neural Network with Dithering for Low Bit-Precision Hardware Inproceedings

In: International Conference on Field-Programmable Technology (FPT), Naha, Japan, 2018.

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24.

Tatsuya Kaneko, Masayuki Ikebe, Shinya Takamaeda-Yamazaki, Masato Motomura, Tetsuya Asai

A Study on Ternary Back Propagation Algorithm for Embedded Egde-AI Processing Inproceedings

In: Joint Workshop of UCL-ICN, NTT, UCL-Gatsby and AIBS: Analysis and Synthesis for Human/Artificial Cognition and Behaviour, Okinawa, Japan, 2018.

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25.

Takumi Kudo, Kodai Ueyoshi, Kota Ando, Kazutoshi Hirose, Ryota Uematsu, Yuka Oba, Masayuki Ikebe, Tetsuya Asai, Masato Motomura, Shinya Takamaeda-Yamazaki

Area and Energy Optimization for Bit-Serial Log-Quantized DNN Accelerator with Shared Accumulators Inproceedings

In: IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, Hanoi, Vietnam, 2018.

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26.

Masanori Hashimoto, Yuki Nakazawa, Jaehoon Yu

Interconnect Delay Analysis for RRAM Crossbar Based FPGA Inproceedings

In: IEEE Computer Society Annual Symposium on VLSI (ISVLSI), pp. 522-527, 2018.

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27.

Taro Fujii, Takao Toi, Teruhito Tanaka, Katsumi Togawa, Toshiro Kitaoka, Kengo Nishino, Noritsugu Nakamura, Hiroki Nakahara, Masato Motomura

New Generation Dynamically Reconfigurable Processor Technology for Accelerating Embedded AI Applications Inproceedings

In: Symposia on VLSI Technology and Circuits, Hawaii, USA, 2018.

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28.

Takeshi Shimada, Masayuki Ikebe, Prasoon Ambalathankandy, Shinya Takamaeda-Yamazaki, Masato Motomura, Tetsuya Asai

Sparse Disparity Estimation Using Global Phase Only Correlation for Stereo Matching Acceleration Inproceedings

In: IEEE International Conference on Acoustics, Speech and Signal Processing, Alberta, Canada, 2018.

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29.

Ryota Uematsu, Kota Ando, Kodai Ueyoshi, Kazutoshi Hirose, Masayuki Ikebe, Tetsuya Asai, Shinya Takamaeda-Yamazaki, Masato Motomura

Exploring CNN Accelerator Design Space on a Dynamically Reconfigurable Hardware Platform Inproceedings

In: Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI), Matsue, Japan, 2018.

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30.

Naoto Iwamaru, Shinya Takamaeda-Yamazaki, Masayuki Ikebe, Masato Motomura, Tetsuya Asai

A Novel Iris-Center Detection Algorithm towards Gaze Estimation Targeting Molecular Cellular Automata Inproceedings

In: International Workshop on Molecular Architectonics, Osaka, Japan, 2018.

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31.

Kodai Ueyoshi, Kota Ando, Kazutoshi Hirose, Shinya Takamaeda-Yamazaki, Junichiro Kadomoto, Tomoki Miyata, Mototsugu Hamada, Tadahiro Kuroda, Masato Motomura

QUEST: A 7.49-TOPS Multi-Purpose Log-Quantized DNN Inference Engine Stacked on 96MB 3D SRAM using Inductive-Coupling Technology in 40nm CMOS Inproceedings

In: International Solid-State Circuits Conference (ISSCC 2018), San Francisco, US, 2018.

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32.

Koichi Mitsunari, Jaehoon Yu, Masanori Hashimoto

Hardware Architecture for Fast General Object Detection Using Aggregated Channel Features Inproceedings

In: pp. 55-58, 2018.

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33.

Ryutaro Doi, Jaehoon Yu, Masanori Hashimoto

Sneak Path Free Reconfiguration of Via-switch Crossbars Based FPGA Inproceedings

In: pp. 68:1–68:8, 2018.

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34.

Kenshi Ito, Jaehoon Yu, Masanori Hashimoto

Adapting Soft Cascade to MAC Operations of Convolutional Neural Networks Inproceedings

In: International Symposium on Multimedia and Communication Technology, pp. 101–104, 2018.

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35.

Masanori Hashimoto, Yuki Nakazawa, Ryutaro Doi, Jaehoon Yu

Interconnect Delay Analysis for RRAM Crossbar Based FPGA Inproceedings

In: pp. 522–527, 2018.

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36.

中澤祐希, 土井龍太郎, 劉載勲, 橋本昌宜

ビアスイッチ FPGA 向け配線解析手法の検討 (VLSI 設計技術) Inproceedings

In: 電子情報通信学会技術研究報告= IEICE technical report: 信学技報, pp. 187–192, 2018.

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37.

土井龍太郎, 劉載勲, 橋本昌宜, others

ビアスイッチ FPGA 再構成時のスニークパス問題を回避するプログラミング順決定手法 Inproceedings

In: DA シンポジウム 2018 論文集, pp. 3–8, 2018.

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2017

38.

Kazutoshi Hirose, Kota Ando, Kodai Ueyoshi, Masayuki Ikebe, Tetsuya Asai, Masato Motomura, Shinya Takamaeda-Yamazaki

Quantization Error-based Regularization in Neural Networks Inproceedings

In: SGAI International Conference on Artificial Intelligence (SGAI), Cambridge, England, 2017.

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39.

Itaru Hida, Kodai Ueyoshi, Shinya Takamaeda-Yamazaki, Masayuki Ikebe, Masato Motomura, Tetsuya Asai

Sign-Invariant Unsupervised Learning Facilitates Weighted-Sum Computation in Analog Neural-Network Devices Inproceedings

In: International Symposium on Nonlinear Theory and Its Applications, Cancun, Mexico, 2017.

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40.

Shinya Takamaeda-Yamazaki, Kodai Ueyoshi, Kota Ando, Ryota Uematsu, Kazutoshi Hirose, Masayuki Ikebe, Tetsuya Asai, Masato Motomura

Accelerating Deep Learning by Binarized Hardware Inproceedings

In: Asia-Pacific Signal and Information Processing Association Annual Summit and Conference (APSIPA ASC), Kuala Lumpur, Malaysia, 2017.

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41.

Kazutoshi Hirose, Ryota Uematsu, Kota Ando, Kentaro Orimo, Kodai Ueyoshi, Masayuki Ikebe, Tetsuya Asai, Shinya Takamaeda-Yamazaki, Masato Motomura

Logarithmic Compression for Memory Footprint Reduction in Neural Network Training Inproceedings

In: International Workshop on Computer Systems and Architectures (CSA), Aomori, Japan, 2017.

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42.

Kazutoshi Hirose, Ryota Uematsu, Kota Ando, Kodai Ueyoshi, Masayuki Ikebe, Tetsuya Asai, Masato Motomura, Shinya Takamaeda-Yamazaki

A Regularization Approach for Quantized Neural Networks Inproceedings

In: International Workshop on Highly Efficient Neural Networks Design (HENND), Seoul, Korea, 2017.

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43.

Aoi Tanibata, Alexandre Schmid, Shinya Takamaeda-Yamazaki, Masayuki Ikebe, Masato Motomura, Tetsuya Asai

FPGA Implementation of Edge-Guided Pattern Generation for Motion-Vector Estimation of Textureless Objects (Demo Night) Inproceedings

In: International Conference on Field-Programmable Logic and Applications (FPL), Ghent, Belgium, 2017.

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44.

Kota Ando, Kodai Ueyoshi, Kazutoshi Hirose, Kentaro Orimo, Haruyoshi Yonekawa, Shimpei Sato, Hiroki Nakahara, Masayuki Ikebe, Shinya Takamaeda-Yamazaki, Tetsuya Asai, Tadahiro Kuroda, Masato Motomura

In-Memory Area-Efficient Signal Streaming Processor Design for Binary Neural Networks Inproceedings

In: IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), Boston, USA, 2017.

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45.

Kasho Yamamoto, Masayuki Ikebe, Tetsuya Asai, Masato Motomura, Shinya Takamaeda-Yamazaki

Time-Division Multiplexing Inproceedings

In: GI-CoRE GSQ, GSB, & IGM Joint Symposium - Quantum, Informatics, Biology, & Medicine -, Sapporo, Japan, 2017.

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46.

Kodai Ueyoshi, Masayuki Ikebe, Tetsuya Asai, Shinya Takamaeda-Yamazaki, Masato Motomura

Hardware Accelerator Design for Convolutional Neural Networks with Low Bit Precision Inproceedings

In: GI-CoRE GSQ, GSB, & IGM Joint Symposium - Quantum, Informatics, Biology, & Medicine -, Sapporo, Japan, 2017.

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47.

Itaru Hida, Shinya Takamaeda-Yamazaki, Masayuki Ikebe, Masato Motomura, Tetsuya Asai

A Versatile and Energy-Efficient Reconfigurable Accelerator for Embedded Microprocessors Inproceedings

In: GI-CoRE GSQ, GSB, & IGM Joint Symposium -Quantum, Informatics, Biology, & Medicine -, Sapporo, Japan, 2017.

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48.

Kota Ando, Kodai Ueyoshi, Kentaro Orimo, Haruyoshi Yonekawa, Shimpei Sato, Hiroki Nakahara, Masayuki Ikebe, Tetsuya Asai, Shinya Takamaeda-Yamazaki, Tadahiro Kuroda, Masato Motomura

BRein Memory: A 13-Layer 4.2 K Neuron/0.8 M Synapse Binary/Ternary Reconfigurable In-Memory Deep Neural Network Accelerator in 65 nm CMOS Inproceedings

In: Symposia on VLSI Technology and Circuits, Kyoto, Japan, 2017.

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49.

Kasho Yamamoto, Weiqiang Huang, Shinya Takamaeda-Yamazaki, Masayuki Ikebe, Tetsuya Asai, Masato Motomura

A Time-Division Multiplexing Ising Machine on FPGAs Inproceedings

In: International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies (HEART), Bochum, Germany, 2017.

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50.

Kodai Ueyoshi, Kota Ando, Kentaro Orimo, Masayuki Ikebe, Tetsuya Asai, Masato Motomura

Exploring Optimized Accelerator Design for Binarized Convolutional Neural Networks Inproceedings

In: International Joint Conference on Neural Networks, Alaska, USA, 2017.

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252 entries « 1 of 6 »