Conference
IEEE SSCS Distinguished Lecture
Prof. Motomura delivered an IEEE SSCS Distinguished Lecture entitled “Reconfigurable and Domain-Specific Hardware for AI Computing” virtually on December 11.
Prof. Motomura delivered an IEEE SSCS Distinguished Lecture entitled “Reconfigurable and Domain-Specific Hardware for AI Computing” virtually on December 11.
We are pleased to welcome three new ArtIC members! Yuta Nagahara (B3) Mari Yasunaga (B3) Masato Watanabe (B3)
Prof. Motomura gave an invited talk entitled “Domain-Specific Architectures for Boosting “Compute for Intelligence”” at The 8th International Workshop on Computer Systems and Architectures (CSA 2020) held virtually on November 26.
Prof. Motomura gave an invited talk entitled “Designing AI Accelerator Chips for the Smarter Future” at The 3rd IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA 2020) held virtually from November 23 to 25.
Assistant Prof. Kawamura gave an invited talk at 16th AI Chip Design Center Forum held virtually on October 30.
Mr. Kitajima, senior in undergraduate, got the fourth place in 85th All Japan Student Yacht Championship, which is the first in Tokyo Tech.
Prof. Motomura gave an invited talk entitled “Stochastic Cellular Automata Annealing (SCA) and its Non-Quantum Silicon Chip Implementation: Realizing Fully-Parallel Spin-Updates for Fully-Connected Spin Systems” at Conference on Quantum Annealing/Adiabatic Quantum Computation held virtually from October 5 to 6.
The paper entitled “ExtraFerns: Fully Parallel Ensemble Learning Technique with Non-Greedy yet Minimal Memory Access Training” has been accepted for publication in the Proceedings of CANDAR 2020. S. Kumazawa will give a presentation at this conference that will be held virtually Read more…
The paper entitled “ProgressiveNN: Achieving Computational Scalability without Network Alteration by MSB-first Accumulative Computation” has been accepted for publication in the Proceedings of CANDAR 2020. J. Suzuki will give a presentation at this conference that will be held virtually from November Read more…
The paper entitled “STATICA: A 512-Spin 0.25M-Weight Annealing Processor with an All-Spin-Updates-at-Once Architecture for Combinatorial Optimization with Complete Spin-Spin Interactions” has been accepted for publication in the IEEE Journal of Solid State Circuits (IEEE JSSC).