At the 2022 International Solid-State Circuits Conference (ISSCC), known as the “Olympics of semiconductor integrated circuits”, we have presented “Hiddenite: 4K-PE Hidden Network Inference 4D-Tensor Engine Exploiting On-Chip Model Construction Achieving 34.8-to-16.0TOPS/W for CIFAR-100 and ImageNet” and provided a demonstration Read more…
At the 2022 International Solid-State Circuits Conference (ISSCC), Professor Motomura was awarded the IEEE Fellow status for his “contributions to memory-logic integration of reconfigurable chip architecture”. Congratulations!
Prof. Motomura gave an invited talk entitled “Trends in Machine Learning Accelerators in HotChips2021: Tokyo Tech’s DNN Inference Accelerator Announcement and Summary of other Presentations in the Field” at The 31st AI Chip Design Center Forum held virtually on January Read more…
Congrats to Yasuyuki Okoshi on receiving the Outstanding Presentation Award for his pre-midterm research proposal presentation from the Department of Information and Communications Engineering. Date: December 1, 2021 Title: Research on High-Precision and Lightweight HNN using Multi-Bit Masks Congratulations!
Our paper entitled “A High-Performance and Flexible FPGA Inference Accelerator for Decision Forests Based on Prior Feature Space Partitioning” received the best paper award at FPT 2021. Congratulations to Assistant Professor Thiem Van Chu! FPT 2021 (held virtually on 6th-10th Read more…
We are pleased to welcome four new ArtIC members! Hikari Otsuka (B3) Akira Hyodo (B3) Akihiro Shioda (B3) Tsukasa Yamakura (B3)
Our paper entitled “Hiddenite: 4K-PE Hidden Network Inference 4D-Tensor Engine Exploiting On-Chip Model Construction Achieving 34.8-to-16.0TOPS/W for CIFAR-100 and ImageNet” has been accepted to ISSCC 2022. Congratulations to the co-first authors, Ph.D. student Kazutoshi Hirose and Associate Professor Jaehoon Yu! Read more…
A technology exhibition, CEATEC 2021, will be held virtually from October 19 to 22. In this exhibition, we show some research results (mainly related to “annealing processor”) obtained in the CREST project “Technology for Computing Revolution for Society 5.0”. Our Read more…
Our paper entitled “Hidden-Fold Networks: Random Recurrent Residuals Using Sparse Supermasks” has been accepted to BMVC 2021. Ph.D. student Ángel López García-Arias will give a poster presentation at the conference. BMVC 2021 (held virtually on 22nd-25th November 2021)
Our paper entitled “A High-Performance and Flexible FPGA Inference Accelerator for Decision Forests Based on Prior Feature Space Partitioning” has been accepted to FPT 2021. Asst. Prof. Thiem will give a presentation at the conference. FPT 2021 (held virtually on Read more…