What’s New

Our paper entitled “Hiddenite: 4K-PE Hidden Network Inference 4D-Tensor Engine Exploiting On-Chip Model Construction Achieving 34.8-to-16.0TOPS/W for CIFAR-100 and ImageNet” has been accepted to ISSCC 2022. Congratulations to the co-first authors, Ph.D. student Kazutoshi Hirose and Associate Professor Jaehoon Yu! Read more…

Our paper entitled “Hidden-Fold Networks: Random Recurrent Residuals Using Sparse Supermasks” has been accepted to BMVC 2021. Ph.D. student Ángel López García-Arias will give a poster presentation at the conference. BMVC 2021 (held virtually on 22nd-25th November 2021)

Our paper entitled “A High-Performance and Flexible FPGA Inference Accelerator for Decision Forests Based on Prior Feature Space Partitioning” has been accepted to FPT 2021. Asst. Prof. Thiem will give a presentation at the conference. FPT 2021 (held virtually on Read more…

Our poster entitled “Edge Inference Engine for Deep & Random Sparse Neural Networks with 4-bit Cartesian-Product MAC Array and Pipelined Activation Aligner” has been accepted to Hot Chips 2021. Asst. Prof. Ando will give a presentation at this conference that Read more…

Prof. Motomura gave an invited talk entitled “New Development of Structural Information Processing Enabled by LSI Technology” at The LSI and Systems Workshop 2021 held virtually on May 10.

Prof. Motomura gave an invited talk entitled “Information Processing Architecture in the Post-Neumann and Post-Moore Era” at The 68th JSAP Spring Meeting 2021 (Open Symposium: A Paradigm Shift to Post-Moore for AI/IoT Era) held virtually on March 18.

Prof. Motomura gave a talk entitled “An Introduction of Fully Connected and Fully Parallel Annealing HW ~ From Mathematical Model to LSI Implementation ~ ” at The Tohoku Forum for Creativity – 2021 Thematic Program (Panel Discussion: Quantum and Quantum-Inspired Read more…