Our paper entitled “Amorphica: 4-Replica 512 Fully Connected Spin 336MHz Metamorphic Annealer with Programmable Optimization Strategy and Compressed-Spin-Transfer Multi-Chip Extension” has been accepted to ISSCC 2023. Assistant Professor K. Kawamura will give a presentation in Session 2. Digital Processors on February 20, 2023. We also give a demo presentation in Read more…
Genta Inoue and Akira Hyodo gave poster presentation at SLDM WIP Forum 2022 at Kyoto on November 11, 2022.
Associate Professor Yu gave an invited talk at SSDM 2022 on September 28.
Our paper entitled “Multicoated Supermasks Enhance Hidden Networks” has been accepted to ICML 2022. Our second year Master’s student Yasuyuki Okoshi will give a short presentation at the conference in July 2022. Congratulations! ICML 2022 (held in a hybrid format (both in-person at Baltimore and virtually) on 17th-23rd July 2022)
Our paper entitled “APC-SCA: A Fully-Parallel Annealing Algorithm with Autonomous Pinning Effect Control” has been accepted to APDCM2022. Daiki Okonogi will give an oral presentation at the conference.
Assistant Prof. Kawamura gave a talk at IPSJ-ONE on March 5, 2022. IPSJ-ONE is an event of the 84th National Convention of IPSJ. He introduced “combinatorial optimization & Ising machine” for beginners. IPSJ-ONE Web site (Japanese only) IPSJ-ONE YouTube archive (Japanese only)
Professor Motomura and Associate Professor Yu gave invited talks at The 84th National Convention of IPSJ held virtually on March 4.
At the 2022 International Solid-State Circuits Conference (ISSCC), known as the “Olympics of semiconductor integrated circuits”, we have presented “Hiddenite: 4K-PE Hidden Network Inference 4D-Tensor Engine Exploiting On-Chip Model Construction Achieving 34.8-to-16.0TOPS/W for CIFAR-100 and ImageNet” and provided a demonstration of DNN inference with a real chip.
Prof. Motomura gave an invited talk entitled “Trends in Machine Learning Accelerators in HotChips2021: Tokyo Tech’s DNN Inference Accelerator Announcement and Summary of other Presentations in the Field” at The 31st AI Chip Design Center Forum held virtually on January 28.
Our paper entitled “Hiddenite: 4K-PE Hidden Network Inference 4D-Tensor Engine Exploiting On-Chip Model Construction Achieving 34.8-to-16.0TOPS/W for CIFAR-100 and ImageNet” has been accepted to ISSCC 2022. Congratulations to the co-first authors, Ph.D. student Kazutoshi Hirose and Associate Professor Jaehoon Yu! Kazutoshi will give a presentation at the conference on February Read more…