468 entries « 5 of 10 »

2017

201.

Masato Motomura

[Invited] A Binary/Ternary Reconfigurable in-Memory Deep Neural Network Accelerator Presentation

MIT CSAIL Seminar, Cambridge, USA, 01.08.2017.

BibTeX | Tags: Invited Talks

202.

Kodai Ueyoshi, Masayuki Ikebe, Tetsuya Asai, Shinya Takamaeda-Yamazaki, Masato Motomura

Hardware Accelerator Design for Convolutional Neural Networks with Low Bit Precision Proceedings Article

In: GI-CoRE GSQ, GSB, & IGM Joint Symposium - Quantum, Informatics, Biology, & Medicine -, Sapporo, Japan, 2017.

BibTeX | Tags: Conference Papers

203.

Itaru Hida, Shinya Takamaeda-Yamazaki, Masayuki Ikebe, Masato Motomura, Tetsuya Asai

A Versatile and Energy-Efficient Reconfigurable Accelerator for Embedded Microprocessors Proceedings Article

In: GI-CoRE GSQ, GSB, & IGM Joint Symposium -Quantum, Informatics, Biology, & Medicine -, Sapporo, Japan, 2017.

BibTeX | Tags: Conference Papers

204.

Kasho Yamamoto, Masayuki Ikebe, Tetsuya Asai, Masato Motomura, Shinya Takamaeda-Yamazaki

Time-Division Multiplexing Proceedings Article

In: GI-CoRE GSQ, GSB, & IGM Joint Symposium - Quantum, Informatics, Biology, & Medicine -, Sapporo, Japan, 2017.

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205.

Takuto Tsuji, Masayuki Ikebe, Shinya Takamaeda-Yamazaki, Masato Motomura, Tetsuya Asai

6-DoF Camera Position and Posture Estimation Based on Local Patches of Image Sequence Journal Article

In: Journal of Signal Processing, vol. 21, no. 4, pp. 191-194, 2017.

BibTeX | Tags: Journal Papers

206.

Kota Ando, Kodai Ueyoshi, Kentaro Orimo, Haruyoshi Yonekawa, Shimpei Sato, Hiroki Nakahara, Masayuki Ikebe, Tetsuya Asai, Shinya Takamaeda-Yamazaki, Tadahiro Kuroda, Masato Motomura

BRein Memory: A 13-Layer 4.2 K Neuron/0.8 M Synapse Binary/Ternary Reconfigurable In-Memory Deep Neural Network Accelerator in 65 nm CMOS Proceedings Article

In: Symposia on VLSI Technology and Circuits, Kyoto, Japan, 2017.

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207.

Kasho Yamamoto, Weiqiang Huang, Shinya Takamaeda-Yamazaki, Masayuki Ikebe, Tetsuya Asai, Masato Motomura

A Time-Division Multiplexing Ising Machine on FPGAs Proceedings Article

In: International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies (HEART), Bochum, Germany, 2017.

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208.

Kota Ando, Shinya Takamaeda-Yamazaki, Masayuki Ikebe, Tetsuya Asai, Masato Motomura

A Multithreaded CGRA for Convolutional Neural Network Processing Journal Article

In: Circuits and Systems, vol. 8, no. 6, pp. 149-170, 2017.

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209.

Kodai Ueyoshi, Kota Ando, Kentaro Orimo, Masayuki Ikebe, Tetsuya Asai, Masato Motomura

Exploring Optimized Accelerator Design for Binarized Convolutional Neural Networks Proceedings Article

In: International Joint Conference on Neural Networks, Alaska, USA, 2017.

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210.

Kodai Ueyoshi, Takao Marukame, Tetsuya Asai, Masato Motomura, Alexandre Schmid

Feature Extraction System Using Restricted Boltzmann Machines on FPGA Proceedings Article

In: IEEE International Symposium on Circuits & Systems, Baltimore, USA, 2017.

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211.

Itaru Hida, Shinya Takamaeda-Yamazaki, Masayuki Ikebe, Masato Motomura, Tetsuya Asai

An Energy-Efficient Dynamic Branch Predictor with a Two-Clock-Cycle Naive Bayes Classifier for Pipelined RISC Microprocessors Journal Article

In: Nonlinear Theory and Its Applications, vol. E8-N, no. 3, pp. 235-245, 2017.

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212.

Itaru Hida, Shinya Takamaeda-Yamazaki, Masayuki Ikebe, Masato Motomura, Tetsuya Asai

A High Performance and Energy Efficient Microprocessor with a Novel Restricted Dynamically Reconfigurable Accelerator Journal Article

In: Circuits and Systems, vol. 8, no. 5, pp. 134-147, 2017.

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213.

Kasho Yamamoto, Shinya Takamaeda-Yamazaki, Masayuki Ikebe, Tetsuya Asai, Masato Motomura

A Scalable Ising Model Implementation on An FPGA Proceedings Article

In: COOL Chips, Yokohama, Japan, 2017.

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214.

Tomoya Fujii, Shimpei Sato, Hiroki Nakahara, Masato Motomura

An FPGA Realization of a Deep Convolutional Neural Network Using A Threshold Neuron Pruning Proceedings Article

In: International Symposium on Applied Reconfigurable Computing (ARC), Delft, Netherlands, 2017.

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215.

Takao Marukame, Kodai Ueyoshi, Tetsuya Asai, Masato Motomura, Alexandre Schmid, Masamichi Suzuki, Yusuke Higashi, Yuichiro Mitani

Error Tolerance Analysis of Deep Learning Hardware Using Restricted Boltzmann Machine towards Low-Power Memory Implementation Journal Article

In: IEEE Transactions on Circuits and Systems II, vol. 64, no. 4, pp. 462-466, 2017.

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216.

Yuhan Fu, Masayuki Ikebe, Takeshi Shimada, Masato Motomura, Tetsuya Asai

Low latency divider using ensemble of moving average curves Proceedings Article

In: International Symposium on Quality Electronic Design (ISQED), Santa Clara, USA, 2017.

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217.

Masato Motomura

[Invited] Rise of Deep Neural Network Accelerators Presentation

Workshop on Brain-inspired Hardware, Tokyo, Japan, 01.03.2017.

BibTeX | Tags: Invited Talks

218.

Kota Ando, Kodai Ueyoshi, Kentaro Orimo, Masayuki Ikebe, Shinya Takamaeda-Yamazaki, Tetsuya Asai, Masato Motomura

Throughput Analysis of A Data-Flow Reconfigurable Array Architecture for Convolutional Neural Networks Proceedings Article

In: RIEC International Symposium on Brain Functions and Brain Computer, Sendai, Japan, 2017.

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219.

Takuto Tsuji, Masayuki Ikebe, Shinya Takamaeda-Yamazaki, Masato Motomura, Tetsuya Asai

6-DoF Camera-Position and Posture Estimation Based on Local Patches of Image Sequence Proceedings Article

In: RISP International Workshop on Nonlinear Circuits, Communications and Signal Processing, Guam, USA, 2017.

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220.

Hiroki Nakahara, Haruyoshi Yonekawa, Hisashi Iwamoto, Masato Motomura

A Batch Normalization Free Binarized Convolutional Deep Neural Network on an FPGA Proceedings Article

In: International Symposium on Field-Programmable Gate Array (FPGA), California, USA, 2017.

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221.

Thiem Van Chu, Shimpei Sato, Kenji Kise

Fast and Cycle-Accurate Emulation of Large-Scale Networks-on-Chip Using a Single FPGA Journal Article

In: ACM Transactions on Reconfigurable Technology and Systems (TRETS), vol. 10, no. 4, pp. 27:1–27:27, 2017.

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222.

Susumu Mashimo, Thiem Van Chu, Kenji Kise

High-Performance Hardware Merge Sorter Proceedings Article

In: IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM), pp. 1–8, 2017.

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223.

Yuuka Hirao, Yoshinori Takeuchi, Masaharu Imai, Jaehoon Yu

Deformable Part Model Based Arrhythmia Detection Using Time Domain Features Journal Article

In: IEICE_J_FECACS, vol. 100, no. 11, pp. 2221–2229, 2017.

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224.

Tomoki Sugiura, Masaharu Imai, Jaehoon Yu, Yoshinori Takeuchi

A Low-Energy Application Specific Instruction-Set Processor towards a Low-Computational Lossless Compression Method for Stimuli Position Data of Artificial Vision Systems Journal Article

In: vol. 25, pp. 210–219, 2017, ((IF: 0.77, 被引用件数: 2)).

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225.

Tomoki Sugiura, Jaehoon Yu, Yoshinori Takeuchi

Hardware-Oriented Algorithm for Phase Synchronization Analysis of Biomedical Signals Proceedings Article

In: IEEE_C_BCAS, pp. 1–4, 2017, ((被引用件数: 1)).

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2016

226.

Hiroki Nakahara, Haruyoshi Yonekawa, Tsutomu Sasao, Hisashi Iwamoto, Masato Motomura

A Memory-Based Realization of A Binarized Deep Convolutional Neural Network Proceedings Article

In: International Conference on Field-Programmable Technology (FPT), Xi'an, China, 2016.

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227.

Kentaro Orimo, Kota Ando, Kodai Ueyoshi, Masayuki Ikebe, Tetsuya Asai, Masato Motomura

FPGA Architecture for Feed-Forward Sequential Memory Network Targeting Long-Term Time-Series Forecasting Proceedings Article

In: International Conference on Reconfigurable Computing and FPGAs, Cancun, Mexico, 2016.

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228.

Hotaka Kusano, Masayuki Ikebe, Tetsuya Asai, Masato Motomura

An FPGA-Optimized Architecture of Anti-Aliasing Based Super Resolution for Real-time HDTV to 4K- and 8K-UHD Conversions Proceedings Article

In: International Conference on Reconfigurable Computing and FPGAs, Cancun, Mexico, 2016.

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229.

Aoi Tanibata, Miho Ushida, Alexandre Schmid, Masayuki Ikebe, Tetsuya Asai, Masato Motomura

A Hardware Cellular-Automaton Architecture for Spatial Pattern Generation towards Motion-Vector Estimation of Textureless Objects Proceedings Article

In: International Symposium on Nonlinear Theory and its Applications, Shizuoka, Japan, 2016.

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230.

Masayuki Ikebe, Daisuke Uchida, Yasuhiro Take, Tetsuya Asai, Tadahiro Kuroda, Masato Motomura

[Invited] 3D Stacked Image Sensor Featuring Low Noise Inductive Coupling Channels Proceedings Article

In: International Workshop on Image Sensors and Imaging Systems, Tokyo, Japan, 2016.

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231.

Masato Motomura

[Invited] AI and SoC Presentation

IEEE Asian Solid-State Circuits Conference (Panel Session), Toyama, Japan, 01.11.2016.

BibTeX | Tags: Invited Talks

232.

Kota Ando, Kentaro Orimo, Kodai Ueyoshi, Masayuki Ikebe, Tetsuya Asai, Masato Motomura

Reconfigurable Processor Array Architecture for Deep Convolutional Neural Networks Proceedings Article

In: Workshop on Synthesis And System Integration of Mixed Information Technologies, Kyoto, Japan, 2016.

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233.

Itaru Hida, Masayuki Ikebe, Tetsuya Asai, Masato Motomura

A Two-Clock-Cycle Naive Bayes Classifier for Dynamic Branch Prediction in Pipelined RISC Microprocessors Proceedings Article

In: IEEE Asia Pacific Conference on Circuits and Systems, Jeju, Korea, 2016.

BibTeX | Tags: Conference Papers

234.

Kota Ando, Kentaro Orimo, Kodai Ueyoshi, Masayuki Ikebe, Tetsuya Asai, Masato Motomura

Reconfigurable Processor Array Architecture for Deep Convolutional Neural Networks Proceedings Article

In: Workshop on Synthesis And System Integration of Mixed Information Technologies, Kyoto, Japan, 2016.

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235.

Tetsuya Asai, Masayuki Ikebe, Masato Motomura

Cognitive Motion Processing in Imager/Neural Processor 3D Stacked Systems Presentation

Japan-Korea Joint Workshop on Complex Communication Sciences, Busan, Korea, 01.10.2016.

BibTeX | Tags: Invited Talks

236.

Tetsuya Asai, Masafumi Mori, Toshiyuki Itou, Yasuhiro Take, Masayuki Ikebe, Tadahiro Kuroda, Masato Motomura

Motion-Vector Estimation and Cognitive Classification on An Image Sensor/Processor 3D Stacked System Featuring ThruChip Interfaces Proceedings Article

In: European Solid-State Circuits Conference, Lausanne, Switzerland, 2016.

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237.

Kasho Yamamoto, Masayuki Ikebe, Tetsuya Asai, Masato Motomura

FPGA-Based Stream Processing for Frequent Itemset Mining with Incremental Multiple Hashes Journal Article

In: Circuits and Systems, vol. 7, no. 10, pp. 3299-3309, 2016.

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238.

Kodai Ueyoshi, Takao Marukame, Tetsuya Asai, Masato Motomura, Alexandre Schmid

FPGA Implementation of A Scalable and Highly Parallel Architecture for Restricted Boltzmann Machines Journal Article

In: Circuits and Systems, vol. 7, no. 9, pp. 2132-2141, 2016.

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239.

Kodai Ueyoshi, Takao Marukame, Tetsuya Asai, Masato Motomura, Alexandre Schmid

Robustness of Hardware-Oriented Restricted Boltzmann Machines in Deep Belief Networks for Reliable Processing Journal Article

In: Nonlinear Theory and Its Applications, vol. E7-N, no. 3, pp. 395-406, 2016.

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240.

Miho Ushida, Alexandre Schmid, Tetsuya Asai, Kazuyoshi Ishimura, Masato Motomura

Motion Vector Estimation of Textureless Objects Exploiting Reaction-Diffusion Cellular Automata Journal Article

In: International Journal of Unconventional Computing, vol. 12, no. 2-3, pp. 169-187, 2016.

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241.

Kodai Ueyoshi, Takao Marukame, Tetsuya Asai, Masato Motomura, Alexandre Schmid

Memory-Error Tolerance of Scalable and Highly Parallel Architecture for Restricted Boltzmann Machines in Deep Belief Network Proceedings Article

In: IEEE International Symposium on Circuits and Systems, Montreal, Canada, 2016.

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242.

Kasho Yamamoto, Tetsuya Asai, Masato Motomura

Hardware Architecture for Online Frequent Items Mining with Memory-Efficient Data Structure Proceedings Article

In: COOL Chips XIX, Yokohama, Japan, 2016.

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243.

Kazuyoshi Ishimura, Alexandre Schmid, Tetsuya Asai, Masato Motomura

Stochastic Resonance Induced by Internal Noise in A Unidirectional Network of Excitable FitzHugh-Nagumo Neurons Journal Article

In: Nonlinear Theory and Its Applications, vol. 7, no. 2, pp. 164-175, 2016.

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244.

Masayuki Ikebe, Daisuke Uchida, Yasuhiro Take, Makito Someya, Satoshi Chikuda, Kento Matsuyama, Tetsuya Asai, Tadahiro Kuroda, Masato Motomura

3D Stacked Imager Featuring Inductive Coupling Channels for High Speed/Low-Noise Image Transfer Journal Article

In: ITE Transactions on Media Technology and Applications, vol. 4, no. 2, pp. 142-148, 2016.

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245.

Masashi Imai, Thiem Van Chu, Kenji Kise, Tomohiro Yoneda

The Synchronous vs. Asynchronous NoC Routers: An Apple-to-Apple Comparison between Synchronous and Transition Signaling Asynchronous Designs Proceedings Article

In: IEEE/ACM International Symposium on Networks-on-Chip (NOCS), pp. 1–8, 2016.

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246.

Tomoki Sugiura, Arif Ullah Khan, Jaehoon Yu, Yoshinori Takeuchi, Seiji Kameda, Takatsugu Kamata, Yuki Hayashida, Tetsuya Yagi, Masaharu Imai

A Programmable Controller for Spatio-Temporal Pattern Stimulation of Cortical Visual Prosthesis Proceedings Article

In: IEEE_C_BCAS, pp. 432–435, 2016, ((被引用件数: 2)).

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247.

Jun Kawabe, Yoshinori Takeuchi, Jaehoon Yu, Masaharu Imai

Proposal of An Efficient Clock-Gating Mechanism for Multi-Core Processors to Reduce Power Supply Noise Proceedings Article

In: Workshop on Synthesis And System Integration of Mixed Information technologies, pp. 178–183, 2016.

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248.

Eric Aliwarga, Koichi Mitsunari, Jaehoon Yu, Takao Onoye, Toshitaka Azuma, Mitsuhiko Koga

System Design of Vision-based Framework for Senior Driver Assistance Proceedings Article

In: Workshop on Synthesis And System Integration of Mixed Information technologies, pp. 77–80, 2016.

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249.

Mitsuhiko Koga, Takao Onoye, Jaehoon Yu, Toshitaka Azuma, Eric Aliwarga

Vision-based Comprehensive Framework for Senior Driver Assistance Proceedings Article

In: ERTICO, 2016.

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250.

Yuuka Hirao, Jaehoon Yu, Yoshinori Takeuchi, Masaharu Imai

Arrhythmia Detection Using a Deformable Part Model and Time Domain Features Proceedings Article

In: pp. 94–99, 2016, ((Student Best Paper Award)).

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468 entries « 5 of 10 »