2017
|
201. | Masato Motomura [Invited] A Binary/Ternary Reconfigurable in-Memory Deep Neural Network Accelerator Presentation MIT CSAIL Seminar, Cambridge, USA, 01.08.2017. @misc{motomura_00092,
title = {[Invited] A Binary/Ternary Reconfigurable in-Memory Deep Neural Network Accelerator},
author = {Masato Motomura},
year = {2017},
date = {2017-08-01},
address = {MIT CSAIL Seminar, Cambridge, USA},
keywords = {Invited Talks},
pubstate = {published},
tppubtype = {presentation}
}
|
202. | Kodai Ueyoshi, Masayuki Ikebe, Tetsuya Asai, Shinya Takamaeda-Yamazaki, Masato Motomura Hardware Accelerator Design for Convolutional Neural Networks with Low Bit Precision Proceedings Article In: GI-CoRE GSQ, GSB, & IGM Joint Symposium - Quantum, Informatics, Biology, & Medicine -, Sapporo, Japan, 2017. @inproceedings{motomura_00102,
title = {Hardware Accelerator Design for Convolutional Neural Networks with Low Bit Precision},
author = {Kodai Ueyoshi and Masayuki Ikebe and Tetsuya Asai and Shinya Takamaeda-Yamazaki and Masato Motomura},
year = {2017},
date = {2017-07-01},
booktitle = {GI-CoRE GSQ, GSB, & IGM Joint Symposium - Quantum, Informatics, Biology, & Medicine -},
address = {Sapporo, Japan},
keywords = {Conference Papers},
pubstate = {published},
tppubtype = {inproceedings}
}
|
203. | Itaru Hida, Shinya Takamaeda-Yamazaki, Masayuki Ikebe, Masato Motomura, Tetsuya Asai A Versatile and Energy-Efficient Reconfigurable Accelerator for Embedded Microprocessors Proceedings Article In: GI-CoRE GSQ, GSB, & IGM Joint Symposium -Quantum, Informatics, Biology, & Medicine -, Sapporo, Japan, 2017. @inproceedings{motomura_00103,
title = {A Versatile and Energy-Efficient Reconfigurable Accelerator for Embedded Microprocessors},
author = {Itaru Hida and Shinya Takamaeda-Yamazaki and Masayuki Ikebe and Masato Motomura and Tetsuya Asai},
year = {2017},
date = {2017-07-01},
booktitle = {GI-CoRE GSQ, GSB, & IGM Joint Symposium -Quantum, Informatics, Biology, & Medicine -},
address = {Sapporo, Japan},
keywords = {Conference Papers},
pubstate = {published},
tppubtype = {inproceedings}
}
|
204. | Kasho Yamamoto, Masayuki Ikebe, Tetsuya Asai, Masato Motomura, Shinya Takamaeda-Yamazaki Time-Division Multiplexing Proceedings Article In: GI-CoRE GSQ, GSB, & IGM Joint Symposium - Quantum, Informatics, Biology, & Medicine -, Sapporo, Japan, 2017. @inproceedings{motomura_00104,
title = {Time-Division Multiplexing},
author = {Kasho Yamamoto and Masayuki Ikebe and Tetsuya Asai and Masato Motomura and Shinya Takamaeda-Yamazaki},
year = {2017},
date = {2017-07-01},
booktitle = {GI-CoRE GSQ, GSB, & IGM Joint Symposium - Quantum, Informatics, Biology, & Medicine -},
address = {Sapporo, Japan},
keywords = {Conference Papers},
pubstate = {published},
tppubtype = {inproceedings}
}
|
205. | Takuto Tsuji, Masayuki Ikebe, Shinya Takamaeda-Yamazaki, Masato Motomura, Tetsuya Asai 6-DoF Camera Position and Posture Estimation Based on Local Patches of Image Sequence Journal Article In: Journal of Signal Processing, vol. 21, no. 4, pp. 191-194, 2017. @article{motomura_00011,
title = {6-DoF Camera Position and Posture Estimation Based on Local Patches of Image Sequence},
author = {Takuto Tsuji and Masayuki Ikebe and Shinya Takamaeda-Yamazaki and Masato Motomura and Tetsuya Asai},
year = {2017},
date = {2017-07-01},
journal = {Journal of Signal Processing},
volume = {21},
number = {4},
pages = {191-194},
keywords = {Journal Papers},
pubstate = {published},
tppubtype = {article}
}
|
206. | Kota Ando, Kodai Ueyoshi, Kentaro Orimo, Haruyoshi Yonekawa, Shimpei Sato, Hiroki Nakahara, Masayuki Ikebe, Tetsuya Asai, Shinya Takamaeda-Yamazaki, Tadahiro Kuroda, Masato Motomura BRein Memory: A 13-Layer 4.2 K Neuron/0.8 M Synapse Binary/Ternary Reconfigurable In-Memory Deep Neural Network Accelerator in 65 nm CMOS Proceedings Article In: Symposia on VLSI Technology and Circuits, Kyoto, Japan, 2017. @inproceedings{ando_00022,
title = {BRein Memory: A 13-Layer 4.2 K Neuron/0.8 M Synapse Binary/Ternary Reconfigurable In-Memory Deep Neural Network Accelerator in 65 nm CMOS},
author = {Kota Ando and Kodai Ueyoshi and Kentaro Orimo and Haruyoshi Yonekawa and Shimpei Sato and Hiroki Nakahara and Masayuki Ikebe and Tetsuya Asai and Shinya Takamaeda-Yamazaki and Tadahiro Kuroda and Masato Motomura},
year = {2017},
date = {2017-06-01},
booktitle = {Symposia on VLSI Technology and Circuits},
address = {Kyoto, Japan},
keywords = {Conference Papers},
pubstate = {published},
tppubtype = {inproceedings}
}
|
207. | Kasho Yamamoto, Weiqiang Huang, Shinya Takamaeda-Yamazaki, Masayuki Ikebe, Tetsuya Asai, Masato Motomura A Time-Division Multiplexing Ising Machine on FPGAs Proceedings Article In: International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies (HEART), Bochum, Germany, 2017. @inproceedings{motomura_00108,
title = {A Time-Division Multiplexing Ising Machine on FPGAs},
author = {Kasho Yamamoto and Weiqiang Huang and Shinya Takamaeda-Yamazaki and Masayuki Ikebe and Tetsuya Asai and Masato Motomura},
year = {2017},
date = {2017-06-01},
booktitle = {International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies (HEART)},
address = {Bochum, Germany},
keywords = {Conference Papers},
pubstate = {published},
tppubtype = {inproceedings}
}
|
208. | Kota Ando, Shinya Takamaeda-Yamazaki, Masayuki Ikebe, Tetsuya Asai, Masato Motomura A Multithreaded CGRA for Convolutional Neural Network Processing Journal Article In: Circuits and Systems, vol. 8, no. 6, pp. 149-170, 2017. @article{motomura_00012,
title = {A Multithreaded CGRA for Convolutional Neural Network Processing},
author = {Kota Ando and Shinya Takamaeda-Yamazaki and Masayuki Ikebe and Tetsuya Asai and Masato Motomura},
year = {2017},
date = {2017-06-01},
journal = {Circuits and Systems},
volume = {8},
number = {6},
pages = {149-170},
keywords = {Journal Papers},
pubstate = {published},
tppubtype = {article}
}
|
209. | Kodai Ueyoshi, Kota Ando, Kentaro Orimo, Masayuki Ikebe, Tetsuya Asai, Masato Motomura Exploring Optimized Accelerator Design for Binarized Convolutional Neural Networks Proceedings Article In: International Joint Conference on Neural Networks, Alaska, USA, 2017. @inproceedings{ando_00027,
title = {Exploring Optimized Accelerator Design for Binarized Convolutional Neural Networks},
author = {Kodai Ueyoshi and Kota Ando and Kentaro Orimo and Masayuki Ikebe and Tetsuya Asai and Masato Motomura},
year = {2017},
date = {2017-05-01},
booktitle = {International Joint Conference on Neural Networks},
address = {Alaska, USA},
keywords = {Conference Papers},
pubstate = {published},
tppubtype = {inproceedings}
}
|
210. | Kodai Ueyoshi, Takao Marukame, Tetsuya Asai, Masato Motomura, Alexandre Schmid Feature Extraction System Using Restricted Boltzmann Machines on FPGA Proceedings Article In: IEEE International Symposium on Circuits & Systems, Baltimore, USA, 2017. @inproceedings{motomura_00110,
title = {Feature Extraction System Using Restricted Boltzmann Machines on FPGA},
author = {Kodai Ueyoshi and Takao Marukame and Tetsuya Asai and Masato Motomura and Alexandre Schmid},
year = {2017},
date = {2017-05-01},
booktitle = {IEEE International Symposium on Circuits & Systems},
address = {Baltimore, USA},
keywords = {Conference Papers},
pubstate = {published},
tppubtype = {inproceedings}
}
|
211. | Itaru Hida, Shinya Takamaeda-Yamazaki, Masayuki Ikebe, Masato Motomura, Tetsuya Asai An Energy-Efficient Dynamic Branch Predictor with a Two-Clock-Cycle Naive Bayes Classifier for Pipelined RISC Microprocessors Journal Article In: Nonlinear Theory and Its Applications, vol. E8-N, no. 3, pp. 235-245, 2017. @article{motomura_00013,
title = {An Energy-Efficient Dynamic Branch Predictor with a Two-Clock-Cycle Naive Bayes Classifier for Pipelined RISC Microprocessors},
author = {Itaru Hida and Shinya Takamaeda-Yamazaki and Masayuki Ikebe and Masato Motomura and Tetsuya Asai},
year = {2017},
date = {2017-05-01},
journal = {Nonlinear Theory and Its Applications},
volume = {E8-N},
number = {3},
pages = {235-245},
keywords = {Journal Papers},
pubstate = {published},
tppubtype = {article}
}
|
212. | Itaru Hida, Shinya Takamaeda-Yamazaki, Masayuki Ikebe, Masato Motomura, Tetsuya Asai A High Performance and Energy Efficient Microprocessor with a Novel Restricted Dynamically Reconfigurable Accelerator Journal Article In: Circuits and Systems, vol. 8, no. 5, pp. 134-147, 2017. @article{motomura_00014,
title = {A High Performance and Energy Efficient Microprocessor with a Novel Restricted Dynamically Reconfigurable Accelerator},
author = {Itaru Hida and Shinya Takamaeda-Yamazaki and Masayuki Ikebe and Masato Motomura and Tetsuya Asai},
year = {2017},
date = {2017-05-01},
journal = {Circuits and Systems},
volume = {8},
number = {5},
pages = {134-147},
keywords = {Journal Papers},
pubstate = {published},
tppubtype = {article}
}
|
213. | Kasho Yamamoto, Shinya Takamaeda-Yamazaki, Masayuki Ikebe, Tetsuya Asai, Masato Motomura A Scalable Ising Model Implementation on An FPGA Proceedings Article In: COOL Chips, Yokohama, Japan, 2017. @inproceedings{motomura_00122,
title = {A Scalable Ising Model Implementation on An FPGA},
author = {Kasho Yamamoto and Shinya Takamaeda-Yamazaki and Masayuki Ikebe and Tetsuya Asai and Masato Motomura},
year = {2017},
date = {2017-04-01},
booktitle = {COOL Chips},
address = {Yokohama, Japan},
keywords = {Conference Papers},
pubstate = {published},
tppubtype = {inproceedings}
}
|
214. | Tomoya Fujii, Shimpei Sato, Hiroki Nakahara, Masato Motomura An FPGA Realization of a Deep Convolutional Neural Network Using A Threshold Neuron Pruning Proceedings Article In: International Symposium on Applied Reconfigurable Computing (ARC), Delft, Netherlands, 2017. @inproceedings{motomura_00124,
title = {An FPGA Realization of a Deep Convolutional Neural Network Using A Threshold Neuron Pruning},
author = {Tomoya Fujii and Shimpei Sato and Hiroki Nakahara and Masato Motomura},
year = {2017},
date = {2017-04-01},
booktitle = {International Symposium on Applied Reconfigurable Computing (ARC)},
address = {Delft, Netherlands},
keywords = {Conference Papers},
pubstate = {published},
tppubtype = {inproceedings}
}
|
215. | Takao Marukame, Kodai Ueyoshi, Tetsuya Asai, Masato Motomura, Alexandre Schmid, Masamichi Suzuki, Yusuke Higashi, Yuichiro Mitani Error Tolerance Analysis of Deep Learning Hardware Using Restricted Boltzmann Machine towards Low-Power Memory Implementation Journal Article In: IEEE Transactions on Circuits and Systems II, vol. 64, no. 4, pp. 462-466, 2017. @article{motomura_00015,
title = {Error Tolerance Analysis of Deep Learning Hardware Using Restricted Boltzmann Machine towards Low-Power Memory Implementation},
author = {Takao Marukame and Kodai Ueyoshi and Tetsuya Asai and Masato Motomura and Alexandre Schmid and Masamichi Suzuki and Yusuke Higashi and Yuichiro Mitani},
year = {2017},
date = {2017-04-01},
journal = {IEEE Transactions on Circuits and Systems II},
volume = {64},
number = {4},
pages = {462-466},
keywords = {Journal Papers},
pubstate = {published},
tppubtype = {article}
}
|
216. | Yuhan Fu, Masayuki Ikebe, Takeshi Shimada, Masato Motomura, Tetsuya Asai Low latency divider using ensemble of moving average curves Proceedings Article In: International Symposium on Quality Electronic Design (ISQED), Santa Clara, USA, 2017. @inproceedings{motomura_00127,
title = {Low latency divider using ensemble of moving average curves},
author = {Yuhan Fu and Masayuki Ikebe and Takeshi Shimada and Masato Motomura and Tetsuya Asai},
year = {2017},
date = {2017-03-01},
booktitle = {International Symposium on Quality Electronic Design (ISQED)},
address = {Santa Clara, USA},
keywords = {Conference Papers},
pubstate = {published},
tppubtype = {inproceedings}
}
|
217. | Masato Motomura [Invited] Rise of Deep Neural Network Accelerators Presentation Workshop on Brain-inspired Hardware, Tokyo, Japan, 01.03.2017. @misc{motomura_00125,
title = {[Invited] Rise of Deep Neural Network Accelerators},
author = {Masato Motomura},
year = {2017},
date = {2017-03-01},
address = {Workshop on Brain-inspired Hardware, Tokyo, Japan},
keywords = {Invited Talks},
pubstate = {published},
tppubtype = {presentation}
}
|
218. | Kota Ando, Kodai Ueyoshi, Kentaro Orimo, Masayuki Ikebe, Shinya Takamaeda-Yamazaki, Tetsuya Asai, Masato Motomura Throughput Analysis of A Data-Flow Reconfigurable Array Architecture for Convolutional Neural Networks Proceedings Article In: RIEC International Symposium on Brain Functions and Brain Computer, Sendai, Japan, 2017. @inproceedings{ando_00028,
title = {Throughput Analysis of A Data-Flow Reconfigurable Array Architecture for Convolutional Neural Networks},
author = {Kota Ando and Kodai Ueyoshi and Kentaro Orimo and Masayuki Ikebe and Shinya Takamaeda-Yamazaki and Tetsuya Asai and Masato Motomura},
year = {2017},
date = {2017-02-01},
booktitle = {RIEC International Symposium on Brain Functions and Brain Computer},
address = {Sendai, Japan},
keywords = {Conference Papers},
pubstate = {published},
tppubtype = {inproceedings}
}
|
219. | Takuto Tsuji, Masayuki Ikebe, Shinya Takamaeda-Yamazaki, Masato Motomura, Tetsuya Asai 6-DoF Camera-Position and Posture Estimation Based on Local Patches of Image Sequence Proceedings Article In: RISP International Workshop on Nonlinear Circuits, Communications and Signal Processing, Guam, USA, 2017. @inproceedings{motomura_00130,
title = {6-DoF Camera-Position and Posture Estimation Based on Local Patches of Image Sequence},
author = {Takuto Tsuji and Masayuki Ikebe and Shinya Takamaeda-Yamazaki and Masato Motomura and Tetsuya Asai},
year = {2017},
date = {2017-02-01},
booktitle = {RISP International Workshop on Nonlinear Circuits, Communications and Signal Processing},
address = {Guam, USA},
keywords = {Conference Papers},
pubstate = {published},
tppubtype = {inproceedings}
}
|
220. | Hiroki Nakahara, Haruyoshi Yonekawa, Hisashi Iwamoto, Masato Motomura A Batch Normalization Free Binarized Convolutional Deep Neural Network on an FPGA Proceedings Article In: International Symposium on Field-Programmable Gate Array (FPGA), California, USA, 2017. @inproceedings{motomura_00132,
title = {A Batch Normalization Free Binarized Convolutional Deep Neural Network on an FPGA},
author = {Hiroki Nakahara and Haruyoshi Yonekawa and Hisashi Iwamoto and Masato Motomura},
year = {2017},
date = {2017-02-01},
booktitle = {International Symposium on Field-Programmable Gate Array (FPGA)},
address = {California, USA},
keywords = {Conference Papers},
pubstate = {published},
tppubtype = {inproceedings}
}
|
221. | Thiem Van Chu, Shimpei Sato, Kenji Kise Fast and Cycle-Accurate Emulation of Large-Scale Networks-on-Chip Using a Single FPGA Journal Article In: ACM Transactions on Reconfigurable Technology and Systems (TRETS), vol. 10, no. 4, pp. 27:1–27:27, 2017. @article{thiem-acmtrets2017,
title = {Fast and Cycle-Accurate Emulation of Large-Scale Networks-on-Chip Using a Single FPGA},
author = {Thiem Van Chu and Shimpei Sato and Kenji Kise},
year = {2017},
date = {2017-01-01},
journal = {ACM Transactions on Reconfigurable Technology and Systems (TRETS)},
volume = {10},
number = {4},
pages = {27:1--27:27},
keywords = {Journal Papers},
pubstate = {published},
tppubtype = {article}
}
|
222. | Susumu Mashimo, Thiem Van Chu, Kenji Kise High-Performance Hardware Merge Sorter Proceedings Article In: IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM), pp. 1–8, 2017. @inproceedings{thiem-fccm2017,
title = {High-Performance Hardware Merge Sorter},
author = {Susumu Mashimo and Thiem Van Chu and Kenji Kise},
year = {2017},
date = {2017-01-01},
booktitle = {IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM)},
pages = {1--8},
keywords = {Conference Papers},
pubstate = {published},
tppubtype = {inproceedings}
}
|
223. | Yuuka Hirao, Yoshinori Takeuchi, Masaharu Imai, Jaehoon Yu Deformable Part Model Based Arrhythmia Detection Using Time Domain Features Journal Article In: IEICE_J_FECACS, vol. 100, no. 11, pp. 2221–2229, 2017. @article{hirao2017deformable,
title = {Deformable Part Model Based Arrhythmia Detection Using Time Domain Features},
author = {Yuuka Hirao and Yoshinori Takeuchi and Masaharu Imai and Jaehoon Yu},
year = {2017},
date = {2017-01-01},
journal = {IEICE_J_FECACS},
volume = {100},
number = {11},
pages = {2221--2229},
keywords = {Journal Papers},
pubstate = {published},
tppubtype = {article}
}
|
224. | Tomoki Sugiura, Masaharu Imai, Jaehoon Yu, Yoshinori Takeuchi A Low-Energy Application Specific Instruction-Set Processor towards a Low-Computational Lossless Compression Method for Stimuli Position Data of Artificial Vision Systems Journal Article In: vol. 25, pp. 210–219, 2017, ((IF: 0.77, 被引用件数: 2)). @article{sugiura2017low,
title = {A Low-Energy Application Specific Instruction-Set Processor towards a Low-Computational Lossless Compression Method for Stimuli Position Data of Artificial Vision Systems},
author = {Tomoki Sugiura and Masaharu Imai and Jaehoon Yu and Yoshinori Takeuchi},
year = {2017},
date = {2017-01-01},
volume = {25},
pages = {210--219},
note = {(IF: 0.77, 被引用件数: 2)},
keywords = {Journal Papers},
pubstate = {published},
tppubtype = {article}
}
|
225. | Tomoki Sugiura, Jaehoon Yu, Yoshinori Takeuchi Hardware-Oriented Algorithm for Phase Synchronization Analysis of Biomedical Signals Proceedings Article In: IEEE_C_BCAS, pp. 1–4, 2017, ((被引用件数: 1)). @inproceedings{sugiura2017hardware,
title = {Hardware-Oriented Algorithm for Phase Synchronization Analysis of Biomedical Signals},
author = {Tomoki Sugiura and Jaehoon Yu and Yoshinori Takeuchi},
year = {2017},
date = {2017-01-01},
booktitle = {IEEE_C_BCAS},
pages = {1--4},
note = {(被引用件数: 1)},
keywords = {Conference Papers},
pubstate = {published},
tppubtype = {inproceedings}
}
|
2016
|
226. | Hiroki Nakahara, Haruyoshi Yonekawa, Tsutomu Sasao, Hisashi Iwamoto, Masato Motomura A Memory-Based Realization of A Binarized Deep Convolutional Neural Network Proceedings Article In: International Conference on Field-Programmable Technology (FPT), Xi'an, China, 2016. @inproceedings{motomura_00142,
title = {A Memory-Based Realization of A Binarized Deep Convolutional Neural Network},
author = {Hiroki Nakahara and Haruyoshi Yonekawa and Tsutomu Sasao and Hisashi Iwamoto and Masato Motomura},
year = {2016},
date = {2016-12-01},
booktitle = {International Conference on Field-Programmable Technology (FPT)},
address = {Xi'an, China},
keywords = {Conference Papers},
pubstate = {published},
tppubtype = {inproceedings}
}
|
227. | Kentaro Orimo, Kota Ando, Kodai Ueyoshi, Masayuki Ikebe, Tetsuya Asai, Masato Motomura FPGA Architecture for Feed-Forward Sequential Memory Network Targeting Long-Term Time-Series Forecasting Proceedings Article In: International Conference on Reconfigurable Computing and FPGAs, Cancun, Mexico, 2016. @inproceedings{ando_00029,
title = {FPGA Architecture for Feed-Forward Sequential Memory Network Targeting Long-Term Time-Series Forecasting},
author = {Kentaro Orimo and Kota Ando and Kodai Ueyoshi and Masayuki Ikebe and Tetsuya Asai and Masato Motomura},
year = {2016},
date = {2016-11-01},
booktitle = {International Conference on Reconfigurable Computing and FPGAs},
address = {Cancun, Mexico},
keywords = {Conference Papers},
pubstate = {published},
tppubtype = {inproceedings}
}
|
228. | Hotaka Kusano, Masayuki Ikebe, Tetsuya Asai, Masato Motomura An FPGA-Optimized Architecture of Anti-Aliasing Based Super Resolution for Real-time HDTV to 4K- and 8K-UHD Conversions Proceedings Article In: International Conference on Reconfigurable Computing and FPGAs, Cancun, Mexico, 2016. @inproceedings{motomura_00143,
title = {An FPGA-Optimized Architecture of Anti-Aliasing Based Super Resolution for Real-time HDTV to 4K- and 8K-UHD Conversions},
author = {Hotaka Kusano and Masayuki Ikebe and Tetsuya Asai and Masato Motomura},
year = {2016},
date = {2016-11-01},
booktitle = {International Conference on Reconfigurable Computing and FPGAs},
address = {Cancun, Mexico},
keywords = {Conference Papers},
pubstate = {published},
tppubtype = {inproceedings}
}
|
229. | Aoi Tanibata, Miho Ushida, Alexandre Schmid, Masayuki Ikebe, Tetsuya Asai, Masato Motomura A Hardware Cellular-Automaton Architecture for Spatial Pattern Generation towards Motion-Vector Estimation of Textureless Objects Proceedings Article In: International Symposium on Nonlinear Theory and its Applications, Shizuoka, Japan, 2016. @inproceedings{motomura_00145,
title = {A Hardware Cellular-Automaton Architecture for Spatial Pattern Generation towards Motion-Vector Estimation of Textureless Objects},
author = {Aoi Tanibata and Miho Ushida and Alexandre Schmid and Masayuki Ikebe and Tetsuya Asai and Masato Motomura},
year = {2016},
date = {2016-11-01},
booktitle = {International Symposium on Nonlinear Theory and its Applications},
address = {Shizuoka, Japan},
keywords = {Conference Papers},
pubstate = {published},
tppubtype = {inproceedings}
}
|
230. | Masayuki Ikebe, Daisuke Uchida, Yasuhiro Take, Tetsuya Asai, Tadahiro Kuroda, Masato Motomura [Invited] 3D Stacked Image Sensor Featuring Low Noise Inductive Coupling Channels Proceedings Article In: International Workshop on Image Sensors and Imaging Systems, Tokyo, Japan, 2016. @inproceedings{motomura_00146,
title = {[Invited] 3D Stacked Image Sensor Featuring Low Noise Inductive Coupling Channels},
author = {Masayuki Ikebe and Daisuke Uchida and Yasuhiro Take and Tetsuya Asai and Tadahiro Kuroda and Masato Motomura},
year = {2016},
date = {2016-11-01},
booktitle = {International Workshop on Image Sensors and Imaging Systems},
address = {Tokyo, Japan},
keywords = {Conference Papers},
pubstate = {published},
tppubtype = {inproceedings}
}
|
231. | Masato Motomura [Invited] AI and SoC Presentation IEEE Asian Solid-State Circuits Conference (Panel Session), Toyama, Japan, 01.11.2016. @misc{motomura_00147,
title = {[Invited] AI and SoC},
author = {Masato Motomura},
year = {2016},
date = {2016-11-01},
address = {IEEE Asian Solid-State Circuits Conference (Panel Session), Toyama, Japan},
keywords = {Invited Talks},
pubstate = {published},
tppubtype = {presentation}
}
|
232. | Kota Ando, Kentaro Orimo, Kodai Ueyoshi, Masayuki Ikebe, Tetsuya Asai, Masato Motomura Reconfigurable Processor Array Architecture for Deep Convolutional Neural Networks Proceedings Article In: Workshop on Synthesis And System Integration of Mixed Information Technologies, Kyoto, Japan, 2016. @inproceedings{ando_00030,
title = {Reconfigurable Processor Array Architecture for Deep Convolutional Neural Networks},
author = {Kota Ando and Kentaro Orimo and Kodai Ueyoshi and Masayuki Ikebe and Tetsuya Asai and Masato Motomura},
year = {2016},
date = {2016-10-01},
booktitle = {Workshop on Synthesis And System Integration of Mixed Information Technologies},
address = {Kyoto, Japan},
keywords = {Conference Papers},
pubstate = {published},
tppubtype = {inproceedings}
}
|
233. | Itaru Hida, Masayuki Ikebe, Tetsuya Asai, Masato Motomura A Two-Clock-Cycle Naive Bayes Classifier for Dynamic Branch Prediction in Pipelined RISC Microprocessors Proceedings Article In: IEEE Asia Pacific Conference on Circuits and Systems, Jeju, Korea, 2016. @inproceedings{motomura_00149,
title = {A Two-Clock-Cycle Naive Bayes Classifier for Dynamic Branch Prediction in Pipelined RISC Microprocessors},
author = {Itaru Hida and Masayuki Ikebe and Tetsuya Asai and Masato Motomura},
year = {2016},
date = {2016-10-01},
booktitle = {IEEE Asia Pacific Conference on Circuits and Systems},
address = {Jeju, Korea},
keywords = {Conference Papers},
pubstate = {published},
tppubtype = {inproceedings}
}
|
234. | Kota Ando, Kentaro Orimo, Kodai Ueyoshi, Masayuki Ikebe, Tetsuya Asai, Masato Motomura Reconfigurable Processor Array Architecture for Deep Convolutional Neural Networks Proceedings Article In: Workshop on Synthesis And System Integration of Mixed Information Technologies, Kyoto, Japan, 2016. @inproceedings{motomura_00150,
title = {Reconfigurable Processor Array Architecture for Deep Convolutional Neural Networks},
author = {Kota Ando and Kentaro Orimo and Kodai Ueyoshi and Masayuki Ikebe and Tetsuya Asai and Masato Motomura},
year = {2016},
date = {2016-10-01},
booktitle = {Workshop on Synthesis And System Integration of Mixed Information Technologies},
address = {Kyoto, Japan},
keywords = {Conference Papers},
pubstate = {published},
tppubtype = {inproceedings}
}
|
235. | Tetsuya Asai, Masayuki Ikebe, Masato Motomura Cognitive Motion Processing in Imager/Neural Processor 3D Stacked Systems Presentation Japan-Korea Joint Workshop on Complex Communication Sciences, Busan, Korea, 01.10.2016. @misc{motomura_00151,
title = {Cognitive Motion Processing in Imager/Neural Processor 3D Stacked Systems},
author = {Tetsuya Asai and Masayuki Ikebe and Masato Motomura},
year = {2016},
date = {2016-10-01},
address = {Japan-Korea Joint Workshop on Complex Communication Sciences, Busan, Korea},
keywords = {Invited Talks},
pubstate = {published},
tppubtype = {presentation}
}
|
236. | Tetsuya Asai, Masafumi Mori, Toshiyuki Itou, Yasuhiro Take, Masayuki Ikebe, Tadahiro Kuroda, Masato Motomura Motion-Vector Estimation and Cognitive Classification on An Image Sensor/Processor 3D Stacked System Featuring ThruChip Interfaces Proceedings Article In: European Solid-State Circuits Conference, Lausanne, Switzerland, 2016. @inproceedings{motomura_00158,
title = {Motion-Vector Estimation and Cognitive Classification on An Image Sensor/Processor 3D Stacked System Featuring ThruChip Interfaces},
author = {Tetsuya Asai and Masafumi Mori and Toshiyuki Itou and Yasuhiro Take and Masayuki Ikebe and Tadahiro Kuroda and Masato Motomura},
year = {2016},
date = {2016-09-01},
booktitle = {European Solid-State Circuits Conference},
address = {Lausanne, Switzerland},
keywords = {Conference Papers},
pubstate = {published},
tppubtype = {inproceedings}
}
|
237. | Kasho Yamamoto, Masayuki Ikebe, Tetsuya Asai, Masato Motomura FPGA-Based Stream Processing for Frequent Itemset Mining with Incremental Multiple Hashes Journal Article In: Circuits and Systems, vol. 7, no. 10, pp. 3299-3309, 2016. @article{motomura_00016,
title = {FPGA-Based Stream Processing for Frequent Itemset Mining with Incremental Multiple Hashes},
author = {Kasho Yamamoto and Masayuki Ikebe and Tetsuya Asai and Masato Motomura},
year = {2016},
date = {2016-08-01},
journal = {Circuits and Systems},
volume = {7},
number = {10},
pages = {3299-3309},
keywords = {Journal Papers},
pubstate = {published},
tppubtype = {article}
}
|
238. | Kodai Ueyoshi, Takao Marukame, Tetsuya Asai, Masato Motomura, Alexandre Schmid FPGA Implementation of A Scalable and Highly Parallel Architecture for Restricted Boltzmann Machines Journal Article In: Circuits and Systems, vol. 7, no. 9, pp. 2132-2141, 2016. @article{motomura_00017,
title = {FPGA Implementation of A Scalable and Highly Parallel Architecture for Restricted Boltzmann Machines},
author = {Kodai Ueyoshi and Takao Marukame and Tetsuya Asai and Masato Motomura and Alexandre Schmid},
year = {2016},
date = {2016-07-01},
journal = {Circuits and Systems},
volume = {7},
number = {9},
pages = {2132-2141},
keywords = {Journal Papers},
pubstate = {published},
tppubtype = {article}
}
|
239. | Kodai Ueyoshi, Takao Marukame, Tetsuya Asai, Masato Motomura, Alexandre Schmid Robustness of Hardware-Oriented Restricted Boltzmann Machines in Deep Belief Networks for Reliable Processing Journal Article In: Nonlinear Theory and Its Applications, vol. E7-N, no. 3, pp. 395-406, 2016. @article{motomura_00018,
title = {Robustness of Hardware-Oriented Restricted Boltzmann Machines in Deep Belief Networks for Reliable Processing},
author = {Kodai Ueyoshi and Takao Marukame and Tetsuya Asai and Masato Motomura and Alexandre Schmid},
year = {2016},
date = {2016-07-01},
journal = {Nonlinear Theory and Its Applications},
volume = {E7-N},
number = {3},
pages = {395-406},
keywords = {Journal Papers},
pubstate = {published},
tppubtype = {article}
}
|
240. | Miho Ushida, Alexandre Schmid, Tetsuya Asai, Kazuyoshi Ishimura, Masato Motomura Motion Vector Estimation of Textureless Objects Exploiting Reaction-Diffusion Cellular Automata Journal Article In: International Journal of Unconventional Computing, vol. 12, no. 2-3, pp. 169-187, 2016. @article{motomura_00019,
title = {Motion Vector Estimation of Textureless Objects Exploiting Reaction-Diffusion Cellular Automata},
author = {Miho Ushida and Alexandre Schmid and Tetsuya Asai and Kazuyoshi Ishimura and Masato Motomura},
year = {2016},
date = {2016-07-01},
journal = {International Journal of Unconventional Computing},
volume = {12},
number = {2-3},
pages = {169-187},
keywords = {Journal Papers},
pubstate = {published},
tppubtype = {article}
}
|
241. | Kodai Ueyoshi, Takao Marukame, Tetsuya Asai, Masato Motomura, Alexandre Schmid Memory-Error Tolerance of Scalable and Highly Parallel Architecture for Restricted Boltzmann Machines in Deep Belief Network Proceedings Article In: IEEE International Symposium on Circuits and Systems, Montreal, Canada, 2016. @inproceedings{motomura_00161,
title = {Memory-Error Tolerance of Scalable and Highly Parallel Architecture for Restricted Boltzmann Machines in Deep Belief Network},
author = {Kodai Ueyoshi and Takao Marukame and Tetsuya Asai and Masato Motomura and Alexandre Schmid},
year = {2016},
date = {2016-05-01},
booktitle = {IEEE International Symposium on Circuits and Systems},
address = {Montreal, Canada},
keywords = {Conference Papers},
pubstate = {published},
tppubtype = {inproceedings}
}
|
242. | Kasho Yamamoto, Tetsuya Asai, Masato Motomura Hardware Architecture for Online Frequent Items Mining with Memory-Efficient Data Structure Proceedings Article In: COOL Chips XIX, Yokohama, Japan, 2016. @inproceedings{motomura_00168,
title = {Hardware Architecture for Online Frequent Items Mining with Memory-Efficient Data Structure},
author = {Kasho Yamamoto and Tetsuya Asai and Masato Motomura},
year = {2016},
date = {2016-04-01},
booktitle = {COOL Chips XIX},
address = {Yokohama, Japan},
keywords = {Conference Papers},
pubstate = {published},
tppubtype = {inproceedings}
}
|
243. | Kazuyoshi Ishimura, Alexandre Schmid, Tetsuya Asai, Masato Motomura Stochastic Resonance Induced by Internal Noise in A Unidirectional Network of Excitable FitzHugh-Nagumo Neurons Journal Article In: Nonlinear Theory and Its Applications, vol. 7, no. 2, pp. 164-175, 2016. @article{motomura_00020,
title = {Stochastic Resonance Induced by Internal Noise in A Unidirectional Network of Excitable FitzHugh-Nagumo Neurons},
author = {Kazuyoshi Ishimura and Alexandre Schmid and Tetsuya Asai and Masato Motomura},
year = {2016},
date = {2016-04-01},
journal = {Nonlinear Theory and Its Applications},
volume = {7},
number = {2},
pages = {164-175},
keywords = {Journal Papers},
pubstate = {published},
tppubtype = {article}
}
|
244. | Masayuki Ikebe, Daisuke Uchida, Yasuhiro Take, Makito Someya, Satoshi Chikuda, Kento Matsuyama, Tetsuya Asai, Tadahiro Kuroda, Masato Motomura 3D Stacked Imager Featuring Inductive Coupling Channels for High Speed/Low-Noise Image Transfer Journal Article In: ITE Transactions on Media Technology and Applications, vol. 4, no. 2, pp. 142-148, 2016. @article{motomura_00021,
title = {3D Stacked Imager Featuring Inductive Coupling Channels for High Speed/Low-Noise Image Transfer},
author = {Masayuki Ikebe and Daisuke Uchida and Yasuhiro Take and Makito Someya and Satoshi Chikuda and Kento Matsuyama and Tetsuya Asai and Tadahiro Kuroda and Masato Motomura},
year = {2016},
date = {2016-04-01},
journal = {ITE Transactions on Media Technology and Applications},
volume = {4},
number = {2},
pages = {142-148},
keywords = {Journal Papers},
pubstate = {published},
tppubtype = {article}
}
|
245. | Masashi Imai, Thiem Van Chu, Kenji Kise, Tomohiro Yoneda The Synchronous vs. Asynchronous NoC Routers: An Apple-to-Apple Comparison between Synchronous and Transition Signaling Asynchronous Designs Proceedings Article In: IEEE/ACM International Symposium on Networks-on-Chip (NOCS), pp. 1–8, 2016. @inproceedings{thiem-nocs2016,
title = {The Synchronous vs. Asynchronous NoC Routers: An Apple-to-Apple Comparison between Synchronous and Transition Signaling Asynchronous Designs},
author = {Masashi Imai and Thiem Van Chu and Kenji Kise and Tomohiro Yoneda},
year = {2016},
date = {2016-01-01},
booktitle = {IEEE/ACM International Symposium on Networks-on-Chip (NOCS)},
pages = {1--8},
keywords = {Conference Papers},
pubstate = {published},
tppubtype = {inproceedings}
}
|
246. | Tomoki Sugiura, Arif Ullah Khan, Jaehoon Yu, Yoshinori Takeuchi, Seiji Kameda, Takatsugu Kamata, Yuki Hayashida, Tetsuya Yagi, Masaharu Imai A Programmable Controller for Spatio-Temporal Pattern Stimulation of Cortical Visual Prosthesis Proceedings Article In: IEEE_C_BCAS, pp. 432–435, 2016, ((被引用件数: 2)). @inproceedings{sugiura2016programmable,
title = {A Programmable Controller for Spatio-Temporal Pattern Stimulation of Cortical Visual Prosthesis},
author = {Tomoki Sugiura and Arif Ullah Khan and Jaehoon Yu and Yoshinori Takeuchi and Seiji Kameda and Takatsugu Kamata and Yuki Hayashida and Tetsuya Yagi and Masaharu Imai},
year = {2016},
date = {2016-01-01},
booktitle = {IEEE_C_BCAS},
pages = {432--435},
note = {(被引用件数: 2)},
keywords = {Conference Papers},
pubstate = {published},
tppubtype = {inproceedings}
}
|
247. | Jun Kawabe, Yoshinori Takeuchi, Jaehoon Yu, Masaharu Imai Proposal of An Efficient Clock-Gating Mechanism for Multi-Core Processors to Reduce Power Supply Noise Proceedings Article In: Workshop on Synthesis And System Integration of Mixed Information technologies, pp. 178–183, 2016. @inproceedings{kawabe2016proposal,
title = {Proposal of An Efficient Clock-Gating Mechanism for Multi-Core Processors to Reduce Power Supply Noise},
author = {Jun Kawabe and Yoshinori Takeuchi and Jaehoon Yu and Masaharu Imai},
year = {2016},
date = {2016-01-01},
booktitle = {Workshop on Synthesis And System Integration of Mixed Information technologies},
pages = {178--183},
keywords = {Conference Papers},
pubstate = {published},
tppubtype = {inproceedings}
}
|
248. | Eric Aliwarga, Koichi Mitsunari, Jaehoon Yu, Takao Onoye, Toshitaka Azuma, Mitsuhiko Koga System Design of Vision-based Framework for Senior Driver Assistance Proceedings Article In: Workshop on Synthesis And System Integration of Mixed Information technologies, pp. 77–80, 2016. @inproceedings{aliwarga2016system,
title = {System Design of Vision-based Framework for Senior Driver Assistance},
author = {Eric Aliwarga and Koichi Mitsunari and Jaehoon Yu and Takao Onoye and Toshitaka Azuma and Mitsuhiko Koga},
year = {2016},
date = {2016-01-01},
booktitle = {Workshop on Synthesis And System Integration of Mixed Information technologies},
pages = {77--80},
keywords = {Conference Papers},
pubstate = {published},
tppubtype = {inproceedings}
}
|
249. | Mitsuhiko Koga, Takao Onoye, Jaehoon Yu, Toshitaka Azuma, Eric Aliwarga Vision-based Comprehensive Framework for Senior Driver Assistance Proceedings Article In: ERTICO, 2016. @inproceedings{koga2016vision,
title = {Vision-based Comprehensive Framework for Senior Driver Assistance},
author = {Mitsuhiko Koga and Takao Onoye and Jaehoon Yu and Toshitaka Azuma and Eric Aliwarga},
year = {2016},
date = {2016-01-01},
booktitle = {ERTICO},
keywords = {Conference Papers},
pubstate = {published},
tppubtype = {inproceedings}
}
|
250. | Yuuka Hirao, Jaehoon Yu, Yoshinori Takeuchi, Masaharu Imai Arrhythmia Detection Using a Deformable Part Model and Time Domain Features Proceedings Article In: pp. 94–99, 2016, ((Student Best Paper Award)). @inproceedings{hirao2016arrhythmia,
title = {Arrhythmia Detection Using a Deformable Part Model and Time Domain Features},
author = {Yuuka Hirao and Jaehoon Yu and Yoshinori Takeuchi and Masaharu Imai},
year = {2016},
date = {2016-01-01},
pages = {94--99},
note = {(Student Best Paper Award)},
keywords = {Conference Papers},
pubstate = {published},
tppubtype = {inproceedings}
}
|