Assistant Prof. Kawamura gave a talk at IPSJ-ONE on March 5, 2022. IPSJ-ONE is an event of the 84th National Convention of IPSJ. He introduced “combinatorial optimization & Ising machine” for beginners. IPSJ-ONE Web site (Japanese only) IPSJ-ONE YouTube archive (Japanese only)
Professor Motomura and Associate Professor Yu gave invited talks at The 84th National Convention of IPSJ held virtually on March 4.
At the 2022 International Solid-State Circuits Conference (ISSCC), known as the “Olympics of semiconductor integrated circuits”, we have presented “Hiddenite: 4K-PE Hidden Network Inference 4D-Tensor Engine Exploiting On-Chip Model Construction Achieving 34.8-to-16.0TOPS/W for CIFAR-100 and ImageNet” and provided a demonstration of DNN inference with a real chip.
Prof. Motomura gave an invited talk entitled “Trends in Machine Learning Accelerators in HotChips2021: Tokyo Tech’s DNN Inference Accelerator Announcement and Summary of other Presentations in the Field” at The 31st AI Chip Design Center Forum held virtually on January 28.
Our paper entitled “Hiddenite: 4K-PE Hidden Network Inference 4D-Tensor Engine Exploiting On-Chip Model Construction Achieving 34.8-to-16.0TOPS/W for CIFAR-100 and ImageNet” has been accepted to ISSCC 2022. Congratulations to the co-first authors, Ph.D. student Kazutoshi Hirose and Associate Professor Jaehoon Yu! Kazutoshi will give a presentation at the conference on February Read more…
Our paper entitled “Hidden-Fold Networks: Random Recurrent Residuals Using Sparse Supermasks” has been accepted to BMVC 2021. Ph.D. student Ángel López García-Arias will give a poster presentation at the conference. BMVC 2021 (held virtually on 22nd-25th November 2021)
Our paper entitled “A High-Performance and Flexible FPGA Inference Accelerator for Decision Forests Based on Prior Feature Space Partitioning” has been accepted to FPT 2021. Asst. Prof. Thiem will give a presentation at the conference. FPT 2021 (held virtually on 6th-10th December 2021)
Our poster entitled “Edge Inference Engine for Deep & Random Sparse Neural Networks with 4-bit Cartesian-Product MAC Array and Pipelined Activation Aligner” has been accepted to Hot Chips 2021. Asst. Prof. Ando will give a presentation at this conference that will be held virtually from August 22 to 24. Hot Read more…
Prof. Motomura gave an invited talk entitled “New Development of Structural Information Processing Enabled by LSI Technology” at The LSI and Systems Workshop 2021 held virtually on May 10.
Prof. Motomura gave an invited talk entitled “Information Processing Architecture in the Post-Neumann and Post-Moore Era” at The 68th JSAP Spring Meeting 2021 (Open Symposium: A Paradigm Shift to Post-Moore for AI/IoT Era) held virtually on March 18.