February 2024

Congrats to Yuta Nagahara on receiving the VLD Excellent Student Author Award for ASP-DAC 2024. Title: Sparse-Sparse Matrix Multiplication Accelerator on FPGA featuring Distribute-Merge Product Dataflow Congratulations!

Congrats to Junnosuke Suzuki on receiving the IEEE EDS Japan Joint Chapter Student Award (VLSI). Title: Pianissimo: A Sub-mW Class DNN Accelerator with Progressive Bit-by-Bit Datapath Architecture for Adaptive Inference at Edge Congratulations!