2021
|
51. | 雑誌記事 こんなとこにもイジングマシン Book Section In: 日経エレクトロニクス9月号,p.35-p37, 2021. @incollection{statica-nikkei,
title = {こんなとこにもイジングマシン},
author = {雑誌記事},
year = {2021},
date = {2021-09-01},
address = {日経エレクトロニクス9月号,p.35-p37},
keywords = {Press Releases},
pubstate = {published},
tppubtype = {incollection}
}
|
52. | 本村 真人 学習/数理モデルに基づく時空間展開型アーキテクチャの創出と応用 Presentation FIT2021, 27.08.2021. @misc{motomura-fit2021,
title = {学習/数理モデルに基づく時空間展開型アーキテクチャの創出と応用},
author = {本村 真人},
year = {2021},
date = {2021-08-27},
address = {FIT2021},
keywords = {Talks},
pubstate = {published},
tppubtype = {presentation}
}
|
53. | 東工大プレスリリース スマホやロボットなどで高効率なAI処理を行うプロセッサーアーキテクチャーを開発 Book Section In: 2021, (NEDO共同広報,マイナビ,monoist,等に掲載). @incollection{descartes-pr2021,
title = {スマホやロボットなどで高効率なAI処理を行うプロセッサーアーキテクチャーを開発},
author = {東工大プレスリリース},
url = {https://www.titech.ac.jp/news/2021/061720},
year = {2021},
date = {2021-08-25},
note = {NEDO共同広報,マイナビ,monoist,等に掲載},
keywords = {Press Releases},
pubstate = {published},
tppubtype = {incollection}
}
|
54. | Kota Ando, Jaehoon Yu, Kazutoshi Hirose, Hiroki Nakahara, Kazushi Kawamura, Thiem Van Chu, Masato Motomura Edge Inference Engine for Deep & Random Sparse Neural Networks with 4-bit Cartesian-Product MAC Array and Pipelined Activation Aligner Proceedings Article In: Hot Chips 33 (Poster), 2021. @inproceedings{ando-hotchips-2021,
title = {Edge Inference Engine for Deep & Random Sparse Neural Networks with 4-bit Cartesian-Product MAC Array and Pipelined Activation Aligner},
author = {Kota Ando and Jaehoon Yu and Kazutoshi Hirose and Hiroki Nakahara and Kazushi Kawamura and Thiem Van Chu and Masato Motomura},
year = {2021},
date = {2021-08-24},
booktitle = {Hot Chips 33 (Poster)},
keywords = {Conference Papers},
pubstate = {published},
tppubtype = {inproceedings}
}
|
55. | 本村 真人 [Invited] AIチップの現状と今後について Presentation JEITAシーオリエンテッド先端実装技術分科会, 28.07.2021. @misc{motomura-jeita-jul2021,
title = {[Invited] AIチップの現状と今後について},
author = {本村 真人},
year = {2021},
date = {2021-07-28},
address = {JEITAシーオリエンテッド先端実装技術分科会},
keywords = {Invited Talks},
pubstate = {published},
tppubtype = {presentation}
}
|
56. | Masato Motomura [Invited] CGRAs for Broad Embedded Market & for Neural Networks Presentation Position Talk in the "Panel: Coarse-Grained Reconfigurable Arrays and their Opportunities as Application Accelerators," IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP), 08.07.2021. @misc{motomura-asap2021,
title = {[Invited] CGRAs for Broad Embedded Market & for Neural Networks},
author = {Masato Motomura},
year = {2021},
date = {2021-07-08},
address = {Position Talk in the "Panel: Coarse-Grained Reconfigurable Arrays and their Opportunities as Application Accelerators," IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP)},
keywords = {Invited Talks},
pubstate = {published},
tppubtype = {presentation}
}
|
57. | Shungo Kumazawa, Kazushi Kawamura, Thiem Van Chu, Masato Motomura, Jaehoon Yu ExtraFerns: Fully Parallel Ensemble Learning Technique with Random Projection and Non-Greedy yet Minimal Memory Access Training Journal Article In: International Journal of Networking and Computing, vol. 11, no. 2, pp. 215-230, 2021. @article{kumazawa-ijnc-2021,
title = {ExtraFerns: Fully Parallel Ensemble Learning Technique with Random Projection and Non-Greedy yet Minimal Memory Access Training},
author = {Shungo Kumazawa and Kazushi Kawamura and Thiem Van Chu and Masato Motomura and Jaehoon Yu},
year = {2021},
date = {2021-07-08},
journal = {International Journal of Networking and Computing},
volume = {11},
number = {2},
pages = {215-230},
keywords = {Journal Papers},
pubstate = {published},
tppubtype = {article}
}
|
58. | Junnosuke Suzuki, Tomohiro Kaneko, Kota Ando, Kazutoshi Hirose, Kazushi Kawamura, Thiem Van Chu, Masato Motomura, Jaehoon Yu ProgressiveNN: Achieving Computational Scalability with Dynamic Bit-Precision Adjustment by MSB-first Accumulative Computation Journal Article In: International Journal of Networking and Computing, vol. 11, no. 2, pp. 338-353, 2021. @article{suzuki-ijnc-2021,
title = {ProgressiveNN: Achieving Computational Scalability with Dynamic Bit-Precision Adjustment by MSB-first Accumulative Computation},
author = {Junnosuke Suzuki and Tomohiro Kaneko and Kota Ando and Kazutoshi Hirose and Kazushi Kawamura and Thiem Van Chu and Masato Motomura and Jaehoon Yu},
year = {2021},
date = {2021-07-08},
journal = {International Journal of Networking and Computing},
volume = {11},
number = {2},
pages = {338-353},
keywords = {Journal Papers},
pubstate = {published},
tppubtype = {article}
}
|
59. | 北島 龍一, 川村 一志, 劉 載勲, 本村 真人, Thiem Van Chu 特徴空間事前分割に基づく決定木アンサンブルのFPGA推論アクセラレータ Technical Report 電子情報通信学会リコンフィギャラブルシステム研究会 (RECONF), 2021. @techreport{kitajima-reconf-2021,
title = {特徴空間事前分割に基づく決定木アンサンブルのFPGA推論アクセラレータ},
author = {北島 龍一 and 川村 一志 and 劉 載勲 and 本村 真人 and Thiem Van Chu},
year = {2021},
date = {2021-06-08},
address = {電子情報通信学会リコンフィギャラブルシステム研究会 (RECONF)},
keywords = {Technical Reports},
pubstate = {published},
tppubtype = {techreport}
}
|
60. | 熊澤 峻悟, 川村 一志, Thiem Van Chu, 本村 真人, 劉載勲 乱数生成ノードの並列閾値最適化に基づくエッジ指向決定木アンサンブル学習 Technical Report 電子情報通信学会リコンフィギャラブルシステム研究会 (RECONF), 2021. @techreport{kumazawa-reconf-2021,
title = {乱数生成ノードの並列閾値最適化に基づくエッジ指向決定木アンサンブル学習},
author = {熊澤 峻悟 and 川村 一志 and Thiem Van Chu and 本村 真人 and 劉載勲},
year = {2021},
date = {2021-06-08},
urldate = {2021-06-08},
address = {電子情報通信学会リコンフィギャラブルシステム研究会 (RECONF)},
keywords = {Technical Reports},
pubstate = {published},
tppubtype = {techreport}
}
|
61. | 鈴木 淳之介, 安藤 洸太, 廣瀬 一俊, 川村 一志, Thiem Van Chu, 本村 真人, 劉載勲 対称二進表現に基づくビットスケーラブルCNN推論手法 Technical Report 電子情報通信学会リコンフィギャラブルシステム研究会 (RECONF), 2021. @techreport{suzuki-reconf-2021,
title = {対称二進表現に基づくビットスケーラブルCNN推論手法},
author = {鈴木 淳之介 and 安藤 洸太 and 廣瀬 一俊 and 川村 一志 and Thiem Van Chu and 本村 真人 and 劉載勲},
year = {2021},
date = {2021-06-08},
address = {電子情報通信学会リコンフィギャラブルシステム研究会 (RECONF)},
keywords = {Technical Reports},
pubstate = {published},
tppubtype = {techreport}
}
|
62. | 熊澤 峻悟, 川村 一志, Thiem Van Chu, 本村 真人, 劉載勲 入力空間のランダム射影と分割に基づくFernアンサンブル学習 Technical Report LSIとシステムとワークショップ, 2021. @techreport{kumazawa-lsi-2021,
title = {入力空間のランダム射影と分割に基づくFernアンサンブル学習},
author = {熊澤 峻悟 and 川村 一志 and Thiem Van Chu and 本村 真人 and 劉載勲},
year = {2021},
date = {2021-05-10},
address = {LSIとシステムとワークショップ},
keywords = {Technical Reports},
pubstate = {published},
tppubtype = {techreport}
}
|
63. | 鈴木 淳之介, 安藤 洸太, 廣瀬 一俊, 川村 一志, Thiem Van Chu, 本村 真人, 劉載勲 ビットスケーラブルCNNにおける計算量・精度トレードオフ制御手法の検討 Technical Report LSIとシステムとワークショップ, 2021. @techreport{suzuki-lsi-2021,
title = {ビットスケーラブルCNNにおける計算量・精度トレードオフ制御手法の検討},
author = {鈴木 淳之介 and 安藤 洸太 and 廣瀬 一俊 and 川村 一志 and Thiem Van Chu and 本村 真人 and 劉載勲},
year = {2021},
date = {2021-05-10},
urldate = {2021-05-10},
address = {LSIとシステムとワークショップ},
keywords = {Technical Reports},
pubstate = {published},
tppubtype = {techreport}
}
|
64. | 本村 真人 [Invited] LSI技術が開く構造型情報処理の新展開 Presentation LSIとシステムのワークショップ, 10.05.2021. @misc{motomura-lsi-workshop-2021,
title = {[Invited] LSI技術が開く構造型情報処理の新展開},
author = {本村 真人},
year = {2021},
date = {2021-05-10},
address = {LSIとシステムのワークショップ},
keywords = {Invited Talks},
pubstate = {published},
tppubtype = {presentation}
}
|
65. | Masato Motomura [Moderator] "Hot" Techs for "Cool" AI Computing: Do We have Enough Tricks? Presentation Panel Discussion, Cool Chips 24., 14.04.2021. @misc{motomura-coolchips-2021,
title = {[Moderator] "Hot" Techs for "Cool" AI Computing: Do We have Enough Tricks?},
author = {Masato Motomura},
year = {2021},
date = {2021-04-14},
address = {Panel Discussion, Cool Chips 24.},
keywords = {Invited Talks},
pubstate = {published},
tppubtype = {presentation}
}
|
66. | 本村 真人 [Invited] ポストノイマン・ポストムーア時代の情報処理アーキテクチャ Presentation 2021年 第68回 応用物理学会春季学術講演会,一般公開シンポジウム:AI/IoT時代を支えるポストムーアパラダイムへの挑戦, 18.03.2021. @misc{motomura-jsap-spring-2021,
title = {[Invited] ポストノイマン・ポストムーア時代の情報処理アーキテクチャ},
author = {本村 真人},
year = {2021},
date = {2021-03-18},
address = {2021年 第68回 応用物理学会春季学術講演会,一般公開シンポジウム:AI/IoT時代を支えるポストムーアパラダイムへの挑戦},
keywords = {Invited Talks},
pubstate = {published},
tppubtype = {presentation}
}
|
67. | 本村 真人 [Invited] 全結合・全並列型アニーリングHWの紹介 ~ その数理モデルからLSI実装まで ~ Presentation Tohoku Forum for Creativity - 2021 Thematic Program,パネルディスカッション:量子アニーリングのハイパフォーマンスコンピューティング– 実世界のシステムの最適化, 08.03.2021. @misc{motomura-tohoku-creativity-2021,
title = {[Invited] 全結合・全並列型アニーリングHWの紹介 ~ その数理モデルからLSI実装まで ~},
author = {本村 真人},
year = {2021},
date = {2021-03-08},
address = {Tohoku Forum for Creativity - 2021 Thematic Program,パネルディスカッション:量子アニーリングのハイパフォーマンスコンピューティング– 実世界のシステムの最適化},
keywords = {Invited Talks},
pubstate = {published},
tppubtype = {presentation}
}
|
68. | Takashi Imagawa, Jaehoon Yu, Masanori Hashimoto, Hiroyuki Ochi MUX Granularity-Oriented Iterative Technology Mapping for Implementing Compute-Intensive Applications on Via-Switch FPGA Proceedings Article In: Design, Automation and Test in Europe Conference (DATE), 2021. @inproceedings{yu-date-2021,
title = {MUX Granularity-Oriented Iterative Technology Mapping for Implementing Compute-Intensive Applications on Via-Switch FPGA},
author = {Takashi Imagawa and Jaehoon Yu and Masanori Hashimoto and Hiroyuki Ochi},
year = {2021},
date = {2021-02-01},
booktitle = {Design, Automation and Test in Europe Conference (DATE)},
keywords = {Conference Papers},
pubstate = {published},
tppubtype = {inproceedings}
}
|
69. | Kota Shiba, Tatsuo Omori, Kodai Ueyoshi, Kota Ando, Kazutoshi Hirose, Shinya Takamaeda-Yamazaki, Masato Motomura, Mototsugu Hamada, Tadahiro Kuroda A 96-MB 3D-Stacked SRAM Using Inductive Coupling with 0.4-V Transmitter, Termination Scheme and 12:1 SerDes in 40-nm CMOS Journal Article In: IEEE Transactions on Circuits and Systems I, vol. 68, no. 2, pp. 692-703, 2021. @article{shiba-ieeetcs2020,
title = {A 96-MB 3D-Stacked SRAM Using Inductive Coupling with 0.4-V Transmitter, Termination Scheme and 12:1 SerDes in 40-nm CMOS},
author = {Kota Shiba and Tatsuo Omori and Kodai Ueyoshi and Kota Ando and Kazutoshi Hirose and Shinya Takamaeda-Yamazaki and Masato Motomura and Mototsugu Hamada and Tadahiro Kuroda},
year = {2021},
date = {2021-02-01},
journal = {IEEE Transactions on Circuits and Systems I},
volume = {68},
number = {2},
pages = {692-703},
keywords = {Journal Papers},
pubstate = {published},
tppubtype = {article}
}
|
2020
|
70. | Kazutoshi Hirose, Shinya Takamaeda-Yamazaki, Jaehoon Yu, Masato Motomura Selective Fine-Tuning on a Classifier Ensemble: Realizing Adaptive Neural Networks With a Diversified Multi-Exit Architecture Journal Article In: IEEE Access, vol. 9, pp. 6179-6187, 2020. @article{hirose-ieee-access-2020,
title = {Selective Fine-Tuning on a Classifier Ensemble: Realizing Adaptive Neural Networks With a Diversified Multi-Exit Architecture},
author = {Kazutoshi Hirose and Shinya Takamaeda-Yamazaki and Jaehoon Yu and Masato Motomura},
year = {2020},
date = {2020-12-28},
journal = {IEEE Access},
volume = {9},
pages = {6179-6187},
keywords = {Journal Papers},
pubstate = {published},
tppubtype = {article}
}
|
71. | Masato Motomura [Invited] Reconfigurable and Domain-Specific Hardware for AI Computing Presentation IEEE SSCS Distinguished Lecturer, 11.12.2020. @misc{motomura-sscs-2020,
title = {[Invited] Reconfigurable and Domain-Specific Hardware for AI Computing},
author = {Masato Motomura},
year = {2020},
date = {2020-12-11},
address = {IEEE SSCS Distinguished Lecturer},
keywords = {Invited Talks},
pubstate = {published},
tppubtype = {presentation}
}
|
72. | 本村 真人 [Invited] 学習/数理モデルに基づく時空間展開型アーキテクチャ Presentation 東京大学情報理工学系セミナー, 07.12.2020. @misc{motomura-todai-isseminar-2020,
title = {[Invited] 学習/数理モデルに基づく時空間展開型アーキテクチャ},
author = {本村 真人},
year = {2020},
date = {2020-12-07},
address = {東京大学情報理工学系セミナー},
keywords = {Invited Talks},
pubstate = {published},
tppubtype = {presentation}
}
|
73. | Masato Motomura [Invited] Domain-Specific Architectures for Boosting "Compute for Intelligence" Presentation International Workshop on Computer Systems and Architectures (CSA), 26.11.2020. @misc{motomura-csa2020,
title = {[Invited] Domain-Specific Architectures for Boosting "Compute for Intelligence"},
author = {Masato Motomura},
year = {2020},
date = {2020-11-26},
address = {International Workshop on Computer Systems and Architectures (CSA)},
keywords = {Invited Talks},
pubstate = {published},
tppubtype = {presentation}
}
|
74. | Shungo Kumazawa, Kazushi Kawamura, Thiem Van Chu, Masato Motomura, Jaehoon Yu ExtraFerns: Fully Parallel Ensemble Learning Technique with Non-Greedy yet Minimal Memory Access Training Proceedings Article In: International Symposium on Computing and Networking (CANDAR), 2020. @inproceedings{kumazawa-candar2020,
title = {ExtraFerns: Fully Parallel Ensemble Learning Technique with Non-Greedy yet Minimal Memory Access Training},
author = {Shungo Kumazawa and Kazushi Kawamura and Thiem Van Chu and Masato Motomura and Jaehoon Yu},
year = {2020},
date = {2020-11-24},
booktitle = {International Symposium on Computing and Networking (CANDAR)},
keywords = {Conference Papers},
pubstate = {published},
tppubtype = {inproceedings}
}
|
75. | Junnosuke Suzuki, Kota Ando, Kazutoshi Hirose, Kazushi Kawamura, Thiem Van Chu, Masato Motomura, Jaehoon Yu ProgressiveNN: Achieving Computational Scalability without Network Alteration by MSB-first Accumulative Computation Proceedings Article In: International Symposium on Computing and Networking (CANDAR), 2020. @inproceedings{suzuki-candar2020,
title = {ProgressiveNN: Achieving Computational Scalability without Network Alteration by MSB-first Accumulative Computation},
author = {Junnosuke Suzuki and Kota Ando and Kazutoshi Hirose and Kazushi Kawamura and Thiem Van Chu and Masato Motomura and Jaehoon Yu},
year = {2020},
date = {2020-11-24},
booktitle = {International Symposium on Computing and Networking (CANDAR)},
keywords = {Conference Papers},
pubstate = {published},
tppubtype = {inproceedings}
}
|
76. | Masato Motomura [Invited] Designing AI Accelerator Chips for the Smarter Future Presentation IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA), 23.11.2020. @misc{motomura-icta2020,
title = {[Invited] Designing AI Accelerator Chips for the Smarter Future},
author = {Masato Motomura},
year = {2020},
date = {2020-11-23},
address = {IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)},
keywords = {Invited Talks},
pubstate = {published},
tppubtype = {presentation}
}
|
77. | Masato Motomura [Invited] Stochastic Cellular Automata Annealing (SCA) and its Non-Quantum Silicon Chip Implementation Presentation Seminar at National University of Singapore, 10.11.2020. @misc{motomura-nus2020,
title = {[Invited] Stochastic Cellular Automata Annealing (SCA) and its Non-Quantum Silicon Chip Implementation},
author = {Masato Motomura},
year = {2020},
date = {2020-11-10},
address = {Seminar at National University of Singapore},
keywords = {Invited Talks},
pubstate = {published},
tppubtype = {presentation}
}
|
78. | Kasho Yamamoto, Kazushi Kawamura, Kota Ando, Normann Mertig, Takashi Takemoto, Masanao Yamaoka, Hiroshi Teramoto, Akira Sakai, Shinya Takamaeda-Yamazaki, Masato Motomura STATICA: A 512-Spin 0.25M-Weight Annealing Processor With an All-Spin-Updates-at-Once Architecture for Combinatorial Optimization With Complete Spin-Spin Interactions Journal Article In: IEEE Journal of Solid-State Circuits (JSSC), 2020. @article{statica-jssc,
title = {STATICA: A 512-Spin 0.25M-Weight Annealing Processor With an All-Spin-Updates-at-Once Architecture for Combinatorial Optimization With Complete Spin-Spin Interactions},
author = {Kasho Yamamoto and Kazushi Kawamura and Kota Ando and Normann Mertig and Takashi Takemoto and Masanao Yamaoka and Hiroshi Teramoto and Akira Sakai and Shinya Takamaeda-Yamazaki and Masato Motomura},
year = {2020},
date = {2020-10-13},
journal = {IEEE Journal of Solid-State Circuits (JSSC)},
keywords = {Journal Papers},
pubstate = {published},
tppubtype = {article}
}
|
79. | Ángel López García-Arias, Jaehoon Yu, Masanori Hashimoto Low-Cost Reservoir Computing using Cellular Automata and Random Forests Proceedings Article In: IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1-5, 2020. @inproceedings{reca-lopez-iscas2020,
title = {Low-Cost Reservoir Computing using Cellular Automata and Random Forests},
author = {Ángel López García-Arias and Jaehoon Yu and Masanori Hashimoto},
year = {2020},
date = {2020-10-10},
booktitle = {IEEE International Symposium on Circuits and Systems (ISCAS)},
pages = {1-5},
keywords = {Conference Papers},
pubstate = {published},
tppubtype = {inproceedings}
}
|
80. | Kota Shiba, Tatsuo Omori, Kodai Ueyoshi, Kota Ando, Kazutoshi Hirose, Shinya Takamaeda-Yamazaki, Masato Motomura, Mototsugu Hamada, Tadahiro Kuroda A 3D-Stacked SRAM Using Inductive Coupling with Low-Voltage Transmitter and 12:1 SerDes Proceedings Article In: IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1-5, 2020. @inproceedings{shiba-iscas2020,
title = {A 3D-Stacked SRAM Using Inductive Coupling with Low-Voltage Transmitter and 12:1 SerDes},
author = {Kota Shiba and Tatsuo Omori and Kodai Ueyoshi and Kota Ando and Kazutoshi Hirose and Shinya Takamaeda-Yamazaki and Masato Motomura and Mototsugu Hamada and Tadahiro Kuroda},
year = {2020},
date = {2020-10-10},
booktitle = {IEEE International Symposium on Circuits and Systems (ISCAS)},
pages = {1-5},
keywords = {Conference Papers},
pubstate = {published},
tppubtype = {inproceedings}
}
|
81. | Masato Motomura [Invited] Stochastic Cellular Automata Annealing (SCA) and its Non-Quantum Silicon Chip Implementation: Realizing Fully-Parallel Spin-Updates for Fully-Connected Spin Systems Presentation Conference on Quantum Annealing/Adiabatic Quantum Computation, 05.10.2020. @misc{motomura-quantumconf-2020,
title = {[Invited] Stochastic Cellular Automata Annealing (SCA) and its Non-Quantum Silicon Chip Implementation: Realizing Fully-Parallel Spin-Updates for Fully-Connected Spin Systems},
author = {Masato Motomura},
year = {2020},
date = {2020-10-05},
address = {Conference on Quantum Annealing/Adiabatic Quantum Computation},
keywords = {Invited Talks},
pubstate = {published},
tppubtype = {presentation}
}
|
82. | Kazuki Onishi, Jaehoon Yu, Masanori Hashimoto Memory Efficient Training using Lookup-Table-based Quantization for Neural Network Proceedings Article In: IEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS), pp. 251–255, IEEE 2020. @inproceedings{onishi2020memory,
title = {Memory Efficient Training using Lookup-Table-based Quantization for Neural Network},
author = {Kazuki Onishi and Jaehoon Yu and Masanori Hashimoto},
year = {2020},
date = {2020-09-04},
booktitle = {IEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS)},
pages = {251--255},
organization = {IEEE},
keywords = {Conference Papers},
pubstate = {published},
tppubtype = {inproceedings}
}
|
83. | 池田 泰我, 植吉 晃大, 安藤 洸太, 廣瀨 一俊, 浅井 哲也, 本村 真人, 高前田 伸也 効率的なDNN計算のための無効ニューロン予測手法の評価 Book Section In: 情報処理学会 システム・アーキテクチャ研究会 - 若手奨励賞, 2020. @incollection{award-ikeda20190725,
title = {効率的なDNN計算のための無効ニューロン予測手法の評価},
author = {池田 泰我 and 植吉 晃大 and 安藤 洸太 and 廣瀨 一俊 and 浅井 哲也 and 本村 真人 and 高前田 伸也},
year = {2020},
date = {2020-07-25},
booktitle = {情報処理学会 システム・アーキテクチャ研究会 - 若手奨励賞},
keywords = {Awards},
pubstate = {published},
tppubtype = {incollection}
}
|
84. | Yuki Hirayama, Tetsuya Asai, Masato Motomura, Shinya Takamaeda-Yamazaki A Hardware-Efficient Weight Sampling Circuit for Bayesian Neural Networks Journal Article In: International Journal of Networking and Computing, vol. 10, 2020. @article{hirayama-ijnc2020,
title = {A Hardware-Efficient Weight Sampling Circuit for Bayesian Neural Networks},
author = {Yuki Hirayama and Tetsuya Asai and Masato Motomura and Shinya Takamaeda-Yamazaki},
year = {2020},
date = {2020-07-01},
journal = {International Journal of Networking and Computing},
volume = {10},
keywords = {Journal Papers},
pubstate = {published},
tppubtype = {article}
}
|
85. | Tai-Yu Cheng, Yukata Masuda, Jun Chen, Jaehoon Yu, Masanori Hashimoto Logarithm-Approximate Floating-Point Multiplier is Applicable to Power-Efficient Neural Network Training Journal Article In: Integration, vol. 74, pp. 19–31, 2020. @article{cheng2020logarithm,
title = {Logarithm-Approximate Floating-Point Multiplier is Applicable to Power-Efficient Neural Network Training},
author = {Tai-Yu Cheng and Yukata Masuda and Jun Chen and Jaehoon Yu and Masanori Hashimoto},
year = {2020},
date = {2020-05-14},
journal = {Integration},
volume = {74},
pages = {19--31},
keywords = {Journal Papers},
pubstate = {published},
tppubtype = {article}
}
|
86. | 本村 真人, 高前田 伸也, 植吉 晃大, 安藤 洸太, 廣瀨 一俊 深層ニューラルネットワーク向けプロセッサ技術の実例と展望 Journal Article In: 電子情報通信学会和文論文誌C, vol. J103-C, no. 05, 2020. @article{Motomura-IEICE-C-2020,
title = {深層ニューラルネットワーク向けプロセッサ技術の実例と展望},
author = {本村 真人 and 高前田 伸也 and 植吉 晃大 and 安藤 洸太 and 廣瀨 一俊},
year = {2020},
date = {2020-05-01},
journal = {電子情報通信学会和文論文誌C},
volume = {J103-C},
number = {05},
keywords = {Journal Papers},
pubstate = {published},
tppubtype = {article}
}
|
87. | IEEE Spectrum Novel Annealing Processor Is the Best Ever at Solving Combinatorial Optimization Problems Book Section In: 2020. @incollection{statica-pressrelease-ieee,
title = {Novel Annealing Processor Is the Best Ever at Solving Combinatorial Optimization Problems},
author = {IEEE Spectrum},
url = {https://spectrum.ieee.org/tech-talk/computing/hardware/japanese-researchers-develop-a-novel-annealing-processor-thats-the-fastest-technology-yet-at-solving-combinatorial-optimization-problems},
year = {2020},
date = {2020-04-14},
keywords = {Press Releases},
pubstate = {published},
tppubtype = {incollection}
}
|
88. | Taiga Ikeda, Kento Sakurada, Atsuyoshi Nakamura, Masato Motomura, Shinya Takamaeda-Yamazaki Hardware/Algorithm Co-optimization for Fully-Parallelized Compact Decision Tree Ensembles on FPGAs Proceedings Article In: International Symposium on Applied Reconfigurable Computing (ARC), Universidad de Castilla-La Mancha, Toledo, Spain, 2020. @inproceedings{Motomura-ARC-2020,
title = {Hardware/Algorithm Co-optimization for Fully-Parallelized Compact Decision Tree Ensembles on FPGAs},
author = {Taiga Ikeda and Kento Sakurada and Atsuyoshi Nakamura and Masato Motomura and Shinya Takamaeda-Yamazaki},
year = {2020},
date = {2020-04-01},
booktitle = {International Symposium on Applied Reconfigurable Computing (ARC)},
address = {Universidad de Castilla-La Mancha, Toledo, Spain},
keywords = {Conference Papers},
pubstate = {published},
tppubtype = {inproceedings}
}
|
89. | 東工大プレスリリース 組合せ最適化問題を高速に解く新しいアニーリングマシンを開発 Book Section In: 2020, (日経新聞,毎日新聞,日経xTECH等各種ウェブメディアに掲載). @incollection{statica-pressrelease-tokodai,
title = {組合せ最適化問題を高速に解く新しいアニーリングマシンを開発},
author = {東工大プレスリリース},
url = {https://www.titech.ac.jp/news/2020/046309.html},
year = {2020},
date = {2020-02-18},
note = {日経新聞,毎日新聞,日経xTECH等各種ウェブメディアに掲載},
keywords = {Press Releases},
pubstate = {published},
tppubtype = {incollection}
}
|
90. | Masanori Hashimoto, Xu Bai, Naoki Banno, Munehiro Tada, Toshitsugu Sakamoto, Jaehoon Yu, Ryutaro Doi, Yusuke Araki, Hidetoshi Onodera, Takashi Imagawa, Hiroyuki Ochi, Kazutoshi Wakabayashi, Yukio Mitsuyama, Tadahiko Sugibayashi Via-Switch FPGA: 65nm CMOS Implementation and Architecture Extension for AI Applications Proceedings Article In: International Solid-State Circuits Conference (ISSCC), pp. 502–503, 2020. @inproceedings{id529,
title = {Via-Switch FPGA: 65nm CMOS Implementation and Architecture Extension for AI Applications},
author = {Masanori Hashimoto and Xu Bai and Naoki Banno and Munehiro Tada and Toshitsugu Sakamoto and Jaehoon Yu and Ryutaro Doi and Yusuke Araki and Hidetoshi Onodera and Takashi Imagawa and Hiroyuki Ochi and Kazutoshi Wakabayashi and Yukio Mitsuyama and Tadahiko Sugibayashi},
year = {2020},
date = {2020-02-17},
booktitle = {International Solid-State Circuits Conference (ISSCC)},
pages = {502--503},
keywords = {Conference Papers},
pubstate = {published},
tppubtype = {inproceedings}
}
|
91. | Kasho Yamamoto, Kota Ando, Normann Mertig, Takashi Takemoto, Masanao Yamaoka, Hiroshi Teramoto, Akira Sakai, Shinya Takamaeda-Yamazaki, Masato Motomura STATICA: A 512-Spin 0.25M-Weight Full-Digital Annealing Processor with a Near-Memory All-Spin-Updates-at-Once Architecture for Combinatorial Optimization with Complete Spin-Spin Interactions Proceedings Article In: International Solid-State Circuits Conference (ISSCC), pp. 138–139, 2020. @inproceedings{statica,
title = {STATICA: A 512-Spin 0.25M-Weight Full-Digital Annealing Processor with a Near-Memory All-Spin-Updates-at-Once Architecture for Combinatorial Optimization with Complete Spin-Spin Interactions},
author = {Kasho Yamamoto and Kota Ando and Normann Mertig and Takashi Takemoto and Masanao Yamaoka and Hiroshi Teramoto and Akira Sakai and Shinya Takamaeda-Yamazaki and Masato Motomura},
year = {2020},
date = {2020-02-17},
booktitle = {International Solid-State Circuits Conference (ISSCC)},
pages = {138--139},
keywords = {Conference Papers},
pubstate = {published},
tppubtype = {inproceedings}
}
|
92. | 本村 真人(監修) Q&Aで分かるAIチップ Book 週刊エコノミスト, 2020. @book{Motomura-ECONOMIST-2020,
title = {Q&Aで分かるAIチップ},
author = {本村 真人(監修)},
year = {2020},
date = {2020-02-04},
publisher = {週刊エコノミスト},
keywords = {Books},
pubstate = {published},
tppubtype = {book}
}
|
93. | 大羽 由華, 村上 大輔, 中江 達哉, 安藤 洸太, 浅井 哲也, 本村 真人, 高前田 伸也 二値化ニューラルネットワークのハードウェア指向精度向上手法の検討 Book Section In: 電子情報通信学会 コンピュータシステム研究会 - 優秀若手発表賞, 2020. @incollection{award-oba20200123,
title = {二値化ニューラルネットワークのハードウェア指向精度向上手法の検討},
author = {大羽 由華 and 村上 大輔 and 中江 達哉 and 安藤 洸太 and 浅井 哲也 and 本村 真人 and 高前田 伸也},
year = {2020},
date = {2020-01-23},
booktitle = {電子情報通信学会 コンピュータシステム研究会 - 優秀若手発表賞},
keywords = {Awards},
pubstate = {published},
tppubtype = {incollection}
}
|
94. | 植吉 晃大, 池田 泰我, 安藤 洸太, 廣瀨 一俊, 浅井 哲也, 高前田 伸也, 本村 真人 無効ニューロン予測によるDNN計算効率化手法 Book Section In: 電子情報通信学会 リコンフィギャラブルシステム研究会 - 優秀講演賞, 2020. @incollection{award-ueyoshi20200123,
title = {無効ニューロン予測によるDNN計算効率化手法},
author = {植吉 晃大 and 池田 泰我 and 安藤 洸太 and 廣瀨 一俊 and 浅井 哲也 and 高前田 伸也 and 本村 真人},
year = {2020},
date = {2020-01-23},
booktitle = {電子情報通信学会 リコンフィギャラブルシステム研究会 - 優秀講演賞},
keywords = {Awards},
pubstate = {published},
tppubtype = {incollection}
}
|
95. | Thiem Van Chu, Kenji Kise, Kiyofumi Tanaka Dependency-Driven Trace-Based Network-on-Chip Emulation on FPGAs Proceedings Article In: ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA), pp. 211–221, 2020. @inproceedings{thiem-fpga2020,
title = {Dependency-Driven Trace-Based Network-on-Chip Emulation on FPGAs},
author = {Thiem Van Chu and Kenji Kise and Kiyofumi Tanaka},
year = {2020},
date = {2020-01-01},
booktitle = {ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA)},
pages = {211--221},
keywords = {Conference Papers},
pubstate = {published},
tppubtype = {inproceedings}
}
|
96. | Yafei Ou, Prasoon Ambalathankandy, Masayuki Ikebe, Shinya Takamaeda, Masato Motomura, Tetsuya Asai Real-time Tone Mapping: A State of the Art Report Journal Article In: IEEE Transactions on Circuits and Systems for Video Technology, 2020. @article{Motomura-TCSVT-2020,
title = {Real-time Tone Mapping: A State of the Art Report},
author = {Yafei Ou and Prasoon Ambalathankandy and Masayuki Ikebe and Shinya Takamaeda and Masato Motomura and Tetsuya Asai},
year = {2020},
date = {2020-01-01},
journal = {IEEE Transactions on Circuits and Systems for Video Technology},
keywords = {Journal Papers},
pubstate = {published},
tppubtype = {article}
}
|
2019
|
97. | Masato Motomura [Invited] AI Computing: The Promised Land for Computer Architecture Innovation? Presentation Future Chips Forum, Tsinghua University, Beijin, China, 17.12.2019. @misc{Motomura-FCF-2019,
title = {[Invited] AI Computing: The Promised Land for Computer Architecture Innovation?},
author = {Masato Motomura},
year = {2019},
date = {2019-12-17},
address = {Future Chips Forum, Tsinghua University, Beijin, China},
keywords = {Invited Talks},
pubstate = {published},
tppubtype = {presentation}
}
|
98. | Prasoon Ambalathankandy, Yafei Ou, Jyotsna Kochiyil, Shinya Takamaeda-Yamazaki, Masato Motomura, Tetsuya Asai, Masayuki Ikebe Radiography Contrast Enhancement: Smoothed LHE Filter, a Practical Solution for Digital X-rays with Mach Band Proceedings Article In: International Conference on Digital Image Computing: Techniques and Applications, University of Western Australia, Perth, Australia, 2019. @inproceedings{Motomura-DICTA-2019,
title = {Radiography Contrast Enhancement: Smoothed LHE Filter, a Practical Solution for Digital X-rays with Mach Band},
author = {Prasoon Ambalathankandy and Yafei Ou and Jyotsna Kochiyil and Shinya Takamaeda-Yamazaki and Masato Motomura and Tetsuya Asai and Masayuki Ikebe},
year = {2019},
date = {2019-12-02},
booktitle = {International Conference on Digital Image Computing: Techniques and Applications},
address = {University of Western Australia, Perth, Australia},
keywords = {Conference Papers},
pubstate = {published},
tppubtype = {inproceedings}
}
|
99. | 本村 真人 AIエッジコンピューティングへの希望と展望 Book OKIテクニカルレビュー、「AIエッジコンピューティングが拓く高度IoT社会」特集, 2019. @book{Motomura-OKI-2019,
title = {AIエッジコンピューティングへの希望と展望},
author = {本村 真人},
year = {2019},
date = {2019-12-01},
number = {234},
publisher = {OKIテクニカルレビュー、「AIエッジコンピューティングが拓く高度IoT社会」特集},
keywords = {Books},
pubstate = {published},
tppubtype = {book}
}
|
100. | Kasho Yamamoto, Masayuki Ikebe, Tetsuya Asai, Masato Motomura, Shinya Takamaeda-Yamazaki FPGA-Based Annealing Processor with Time-Division Multiplexing Journal Article In: IEICE Transactions on Information and Systems, vol. E102, 2019. @article{motomura_00002,
title = {FPGA-Based Annealing Processor with Time-Division Multiplexing},
author = {Kasho Yamamoto and Masayuki Ikebe and Tetsuya Asai and Masato Motomura and Shinya Takamaeda-Yamazaki},
year = {2019},
date = {2019-12-01},
journal = {IEICE Transactions on Information and Systems},
volume = {E102},
keywords = {Journal Papers},
pubstate = {published},
tppubtype = {article}
}
|