2026

AQPIM: Breaking the PIM Capacity Wall for LLMs with In-Memory Activation Quantization
(日本語) Kosuke Matsushima, (日本語) Yasuyuki Okoshi, (日本語) Masato Motomura, (日本語) Daichi Fujiki
2026 IEEE International Symposium on High-Performance Computer Architecture (HPCA),International Conference,2026
BibTeX
Memory-Efficient and Trustworthy Neural Networks via Random Seed-Based Design
(日本語) Hiroaki Ito, (日本語) Hikari Otsuka, Ryota Yasudo, Zhiqiang Que, Jose G. F. Coutinho, (日本語) Daichi Fujiki, (日本語) Masato Motomura, Ce Guo, Wayne Luk
IEEE Access,Journal Papers,2026
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The Strong Lottery Ticket Hypothesis for Multi-Head Attention Mechanisms
(日本語) Hikari Otsuka, Daiki Chijiwa, (日本語) Yasuyuki Okoshi, (日本語) Daichi Fujiki, Susumu Takeuchi, (日本語) Masato Motomura
The Fortieth AAAI Conference on Artificial Intelligence (AAAI 2026),International Conference,2026
BibTeX

2025

TF-GNN: Memory-Efficient GNNs via Tensor Train Decomposition and Network Folding
(日本語) Hiroaki Ito, (日本語) Jiale Yan, (日本語) Kazushi Kawamura, (日本語) Masato Motomura, (日本語) Thiem Van Chu, (日本語) Daichi Fujiki
COOL Chips 28,International Conference,2025
BibTeX
Accelerating Decision Forest Training via Node-Level Random Data Sampling
(日本語) Tsukasa Yamakura, (日本語) Kazushi Kawamura, (日本語) Daichi Fujiki, (日本語) Masato Motomura, (日本語) Thiem Van Chu
Workshop,2025
BibTeX
Amorphica: A Fully Connected Annealer Supporting Metamorphic Annealing and Scalable Multi Chip Integration
(日本語) Daiki Okonogi, (日本語) Jaehoon Yu, (日本語) Satoru Jimbo, (日本語) Genta Inoue, (日本語) Akira Hyodo, (日本語) Kota Ando, Hideki Fukushima-Kimura Bruno, Yasudo Ryota, (日本語) Thiem Van Chu, (日本語) Masato Motomura, (日本語) Kazushi Kawamura
IEEE Access,Journal Papers,2025
BibTeX
Binary Quadratic Quantization: Beyond First-Order Quantization for Real-Valued Matrix Compression
(日本語) Kyo Kuroki, (日本語) Yasuyuki Okoshi, (日本語) Thiem Van Chu, (日本語) Kazushi Kawamura, (日本語) Masato Motomura
39th Annual Conference on Neural Information Processing Systems (NeurIPS 2025),International Conference,2025
BibTeX
BingoGCN: Towards Scalable and Efficient GNN Acceleration with Fine-Grained Partitioning and SLT
(日本語) Jiale Yan, (日本語) Hiroaki Ito, (日本語) Yuta Nagahara, (日本語) Kazushi Kawamura, (日本語) Masato Motomura, (日本語) Thiem Van Chu, (日本語) Daichi Fujiki
International Symposium on Computer Architecture (ISCA 2025),International Conference,2025
BibTeX
Boltzmann Machine Is Useful for Enhancing Search Performance of Ising Machines
(日本語) Satoru Jimbo, (日本語) Kazushi Kawamura
The Genetic and Evolutionary Computation Conference (GECCO),International Conference,2025
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DMSA: An Efficient Architecture for Sparse–Sparse Matrix Multiplication Based on Distribute-Merge Product Dataflow
(日本語) Yuta Nagahara, (日本語) Jiale Yan, (日本語) Kazushi Kawamura, (日本語) Daichi Fujiki, (日本語) Masato Motomura, (日本語) Thiem Van Chu
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,Journal Papers,2025
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DX100: Programmable Data Access Accelerator for Indirection
Alireza Khadem, Kamalavasan Kamalakkannan, Zhenyan Zhu, Akash Poptani, Yufeng Gu, Jered Benjamin Dominguez-Trujillo, Nishil Talati, (日本語) Daichi Fujiki, Scott Mahlke, Galen Shipman, Reetuparna Das
International Symposium on Computer Architecture (ISCA 2025),International Conference,2025
BibTeX
Multi-Dimensional Vector ISA Extension for Mobile In-Cache Computing
Alireza Khadem, (日本語) Daichi Fujiki, Hilbert Chen, Yufeng Gu, Nishil Talati, Scott Mahlke, Reetuparna Das
IEEE International Symposium on High Performance Computer Architecture (HPCA 2025),International Conference,2025
BibTeX
On the Existence of Hidden Subnetworks Within a Randomly Weighted Multi-Head Attention Mechanism
(日本語) Hikari Otsuka, (日本語) Yasuyuki Okoshi, (日本語) Daichi Fujiki, Susumu Takeuchi, (日本語) Masato Motomura, Daiki Chijiwa
Workshop,2025
BibTeX
Partially Frozen Random Networks Contain Compact Strong Lottery Tickets
Transactions on Machine Learning Research,Journal Papers,2025
BibTeX
PIM による動的量子化を用いた大規模言語モデル推論の効率化
(日本語) Kosuke Matsushima, (日本語) Yasuyuki Okoshi, (日本語) Masato Motomura, (日本語) Daichi Fujiki
Workshop,2025
BibTeX
Rethinking Optimal Verification Granularity for Compute-Efficient Test-Time Scaling
Hao Mark Chen, Guanxi Lu, (日本語) Yasuyuki Okoshi, Zhiwen Mo, (日本語) Masato Motomura, Hongxiang Fan
39th Annual Conference on Neural Information Processing Systems (NeurIPS 2025),International Conference,2025
BibTeX
SharK: Enabling High-Performance Range Queries in Key-Value Store Through Vlog Resharding
Naoto Sugiura, (日本語) Daichi Fujiki
IEEE Access,Journal Papers,2025
BibTeX
TicketLLM: Next-Generation Sparse and Low-bit Transformers with Supermask-based Method
(日本語) Yasuyuki Okoshi, (日本語) Hikari Otsuka, (日本語) Daichi Fujiki, (日本語) Masato Motomura
Transactions on Machine Learning Research,Journal Papers,2025
BibTeX
Uncovering Strong Lottery Tickets in Graph Transformers: A Path to Memory Efficient and Robust Graph Learning
(日本語) Hiroaki Ito, (日本語) Jiale Yan, (日本語) Hikari Otsuka, (日本語) Kazushi Kawamura, (日本語) Masato Motomura, (日本語) Thiem Van Chu, (日本語) Daichi Fujiki
Transactions on Machine Learning Research,Journal Papers,2025
BibTeX
Unlocking the Potential of Extremely Low-Bit Sparse Transformers through Adaptive Multi-bit Supermasks and Random Weights
(日本語) Yasuyuki Okoshi, (日本語) Hikari Otsuka, (日本語) Junnosuke Suzuki, (日本語) Daichi Fujiki, (日本語) Masato Motomura
Workshop,2025
BibTeX
WhiteDwarf: A Holistic Co-Design Approach to Ultra-Compact Neural Inference Acceleration
(日本語) Ángel López García-Arias, (日本語) Yasuyuki Okoshi, (日本語) Jaehoon Yu, (日本語) Junnosuke Suzuki, (日本語) Hikari Otsuka, (日本語) Kazushi Kawamura, (日本語) Thiem Van Chu, (日本語) Daichi Fujiki, (日本語) Masato Motomura
IEEE Access,Journal Papers,2025
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キオクシア奨励研究優秀研究賞
(日本語) Daichi Fujiki
Workshop,2025
BibTeX
グラフトランスフォーマーにおける強い宝くじの発見
(日本語) Hiroaki Ito, (日本語) Jiale Yan, (日本語) Hikari Otsuka, (日本語) Kazushi Kawamura, (日本語) Masato Motomura, (日本語) Thiem Van Chu, (日本語) Daichi Fujiki
Workshop,2025
BibTeX
令和7年度 文部科学大臣表彰 科学技術賞 (開発部門) 「動的再構成プロセッサ技術とAI処理プロセッサの開発」
(日本語) Masato Motomura
Workshop,2025
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2024

[Invited] AIチップ開発の最先端
(日本語) Masato Motomura
Workshop,2024
BibTeX
[Invited] Algorithm-Architecture Centric Approach Towards Energy Efficient AI Hardware
(日本語) Masato Motomura
Workshop,2024
BibTeX
[Invited] Algorithm-Architecture Centric Approach Towards Energy Efficient AI Hardware
(日本語) Masato Motomura
Workshop,2024
BibTeX
[Invited] Algorithm-Architecture Centric Approach Towards Low Power AI Hardware
(日本語) Masato Motomura
Workshop,2024
BibTeX
[Invited] Reconfigurable AI Processing for Embedded Systems
(日本語) Masato Motomura
Workshop,2024
BibTeX
[Invited] Towards Multi-Layer Processing-in-Memory Systems for General Applications
(日本語) Daichi Fujiki
Workshop,2024
BibTeX
[Invited] Will AI Bite the Industry That Feeds It?
(日本語) Masato Motomura
Workshop,2024
BibTeX
[Invited] エッジ知能の実現に向けたAIコンピューティングの展望
(日本語) Masato Motomura
Workshop,2024
BibTeX
[PMRU研究奨励賞] 強い宝くじ仮説に基づく超軽量物体検出ニューラルネットワーク
(日本語) Hikari Otsuka
Workshop,2024
BibTeX
[優秀学生賞] 負荷均等配分を目指した高並列疎行列積アーキテクチャの研究
(日本語) Yuta Nagahara
Workshop,2024
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[基調講演] 組み込み市場を変革するエッジAIの今後の展開
(日本語) Masato Motomura
Workshop,2024
BibTeX
[記念講演] MVC: Enabling Fully Coherent Multi-Data-Views through the Memory Hierarchy with Processing in Memory
(日本語) Daichi Fujiki
Workshop,2024
BibTeX
[記念講演] 分散マージ乗算手法に基づく疎行列疎行列積アクセラレータ
(日本語) Yuta Nagahara, (日本語) Jiale Yan, (日本語) Kazushi Kawamura, (日本語) Masato Motomura, (日本語) Thiem Van Chu
Workshop,2024
BibTeX
2スピン同時フリップの並列試行により高効率な解探索を行うアニーリングプロセッサ
(日本語) Akira Hyodo, (日本語) Satoru Jimbo, (日本語) Daiki Okonogi, (日本語) Genta Inoue, (日本語) Thiem Van Chu, (日本語) Masato Motomura, (日本語) Kazushi Kawamura
Workshop,2024
BibTeX
A GPU-Based Ising Machine With a Multi-Spin-Flip Capability for Constrained Combinatorial Optimization
(日本語) Satoru Jimbo, Tatsuhiko Shirai, Nozomu Togawa, (日本語) Masato Motomura, (日本語) Kazushi Kawamura
IEEE Access,Journal Papers,2024
BibTeX
A Parallel-trial Double-update Annealing Algorithm for Enabling Highly-effective State Transition on Annealing Processors
(日本語) Akira Hyodo, (日本語) Satoru Jimbo, (日本語) Daiki Okonogi, (日本語) Genta Inoue, Thiem Chua, (日本語) Masato Motomura, (日本語) Kazushi Kawamura
Workshop,2024
BibTeX
An Accurate FPGA-Based ORB Feature Extractor for SLAM with Row-Wise Keypoint Selection
(日本語) Yuki Ichikawa, (日本語) Akihiro Shioda, (日本語) Kazushi Kawamura, (日本語) Thiem Van Chu, (日本語) Masato Motomura
International Conference on Consumer Electronics (ICCE),International Conference,2024
BibTeX
Classical Thermodynamics-based Parallel Annealing Algorithm for High-speed and Robust Combinatorial Optimization
(日本語) Kyo Kuroki, (日本語) Satoru Jimbo, (日本語) Thiem Van Chu, (日本語) Masato Motomura, (日本語) Kazushi Kawamura
The Genetic and Evolutionary Computation Conference (GECCO),International Conference,2024
BibTeX
Data centric computing and machine learning
(日本語) Daichi Fujiki
Workshop,2024
BibTeX
Efficient Co-Design of Hardware and Algorithms for SLT-based Graph Neural Networks
(日本語) Jiale Yan, (日本語) Hiroaki Ito, (日本語) Kazushi Kawamura, (日本語) Thiem Van Chu, (日本語) Daichi Fujiki, (日本語) Masato Motomura
6th R-CCS International Symposium,International Conference,2024
BibTeX
Efficient COO to CSR Conversion for Accelerating Sparse Matrix Processing on FPGA
(日本語) Yuta Nagahara, (日本語) Jiale Yan, (日本語) Kazushi Kawamura, (日本語) Masato Motomura, (日本語) Thiem Van Chu
International Conference on Consumer Electronics (ICCE),International Conference,2024
BibTeX
Efficient Stereo Visual Odometry on FPGA Featuring On-Chip Map Management and Pipelined Descriptor-Based Block Matching
(日本語) Yuki Ichikawa, (日本語) Kazushi Kawamura, (日本語) Masato Motomura, (日本語) Thiem Van Chu
IEEE Access,Journal Papers,2024
BibTeX
ETreeNet: Ensemble Model Fusing Decision Trees and Neural Networks for Small Tabular Data
(日本語) Tsukasa Yamakura, (日本語) Kazushi Kawamura, (日本語) Masato Motomura, (日本語) Thiem Van Chu
International Joint Conference on Neural Networks (IJCNN),International Conference,2024
BibTeX
Exploiting N: M Sparsity in Quantized-Folded ResNets: Signed Multicoat Supermasks and Iterative Pruning-Quantization
(日本語) Akihiro Shioda, (日本語) Ángel López García-Arias, (日本語) Hikari Otsuka, (日本語) Yuki Ichikawa, (日本語) Yasuyuki Okoshi, (日本語) Kazushi Kawamura, (日本語) Thiem Van Chu, (日本語) Daichi Fujiki, (日本語) Masato Motomura
2024 Twelfth International Symposium on Computing and Networking (CANDAR),International Conference,2024
BibTeX
Exploration of Hyperdimensional Computing Using Locality-Sensitive Hashing Mechanism on FPGA
(日本語) Masato Watanabe, (日本語) Shungo Kumazawa, (日本語) Thiem Van Chu, (日本語) Kazushi Kawamura, (日本語) Jaehoon Yu, (日本語) Masato Motomura
International Conference on Consumer Electronics (ICCE),International Conference,2024
BibTeX
GPB: An Efficient GBDT Training Method with Tree-Level Parallelism Using Binary Feature Decomposition
(日本語) Tsukasa Yamakura, (日本語) Kazushi Kawamura, (日本語) Daichi Fujiki, (日本語) Masato Motomura, (日本語) Thiem Van Chu
Workshop,2024
BibTeX
High Throughput Datapath Design for Vision Permutator FPGA Accelerator
(日本語) Mari Yasunaga, (日本語) Junnosuke Suzuki, (日本語) Masato Watanabe, (日本語) Kazushi Kawamura, (日本語) Thiem Van Chu, (日本語) Masato Motomura
International Conference on Consumer Electronics (ICCE),International Conference,2024
BibTeX
Memory-efficient Methods for Graph Transformer Using Strong Lottery Tickets Hypothesis
(日本語) Hiroaki Ito, (日本語) Jiale Yan, (日本語) Kazushi Kawamura, (日本語) Thiem Van Chu, (日本語) Daichi Fujiki, (日本語) Masato Motomura
6th R-CCS International Symposium,International Conference,2024
BibTeX
OSA-HCIM: On-The-Fly Saliency-Aware Hybrid SRAM CIM with Dynamic Precision Configuration
YC Chen, S Ando, D Fujiki, S Takamaeda-Yamazaki, K Yoshioka
Workshop,2024
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Partially Frozen Random Networks Contain Compact Strong Lottery Tickets
Workshop,2024
BibTeX
Progressive Variable Precision DNN with Bitwise Ternary Accumulation
(日本語) Junnosuke Suzuki, (日本語) Mari Yasunaga, (日本語) Kazushi Kawamura, (日本語) Thiem Van Chu, (日本語) Masato Motomura
International Conference on Artificial Intelligence Circuits and Systems (AICAS),International Conference,2024
BibTeX
Ramanujan Edge-Popup: Finding Strong Lottery Tickets with Ramanujan Graph Properties for Efficient DNN Inference Execution
(日本語) Hikari Otsuka, (日本語) Yasuyuki Okoshi, (日本語) Ángel López García-Arias, (日本語) Kazushi Kawamura, (日本語) Thiem Van Chu, (日本語) Masato Motomura
Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI),International Conference,2024
BibTeX
Restricted Random Pruning at Initialization for High Compression Range
(日本語) Hikari Otsuka, (日本語) Yasuyuki Okoshi, (日本語) Ángel López García-Arias, (日本語) Kazushi Kawamura, (日本語) Thiem Van Chu, (日本語) Daichi Fujiki, (日本語) Masato Motomura
Transactions on Machine Learning Research (TMLR),Journal Papers,2024
BibTeX
Sparse-Sparse Matrix Multiplication Accelerator on FPGA featuring Distribute-Merge Product Dataflow
(日本語) Yuta Nagahara, (日本語) Jiale Yan, (日本語) Kazushi Kawamura, (日本語) Masato Motomura, (日本語) Thiem Van Chu
Asia and South Pacific Design Automation Conference (ASP-DAC),International Conference,2024
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The Case for Coherence Directories in Memory Cubes
2024 17th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC-2024),International Conference,2024
BibTeX
The Trichromatic Strong Lottery Ticket Hypothesis: Neural Compression With Three Primary Supermasks
(日本語) Ángel López García-Arias, (日本語) Yasuyuki Okoshi, (日本語) Hikari Otsuka, Daiki Chijiwa, Yasuhiro Fujiwara, Susumu Takeuchi, (日本語) Masato Motomura
Workshop,2024
BibTeX
Toward Improving Ensemble-Based Collaborative Inference at the Edge
(日本語) Shungo Kumazawa, (日本語) Jaehoon Yu, (日本語) Kazushi Kawamura, (日本語) Thiem Van Chu, (日本語) Masato Motomura
IEEE Access,Journal Papers,2024
BibTeX
WhiteDwarf: 12.24 TFLOPS/W 40 nm Versatile Neural Inference Engine for Ultra-Compact Execution of CNNs and MLPs Through Triple Unstructured Sparsity Exploitation and Triple Model Compression
(日本語) Yasuyuki Okoshi, (日本語) Ángel López García-Arias, (日本語) Jaehoon Yu, Junnnosuke Suzuki, (日本語) Hikari Otsuka, (日本語) Thiem Van Chu, (日本語) Kazushi Kawamura, (日本語) Daichi Fujiki, (日本語) Masato Motomura
2024 IEEE Asian Solid-State Circuits Conference (A-SSCC),International Conference,2024
BibTeX
パイプライン処理と画像特徴の転用によるSLAMアクセラレータの効率化
(日本語) Yuki Ichikawa, (日本語) Kazushi Kawamura, (日本語) Masato Motomura, (日本語) Thiem Van Chu
Workshop,2024
BibTeX
平均場アニーリングに基づく高性能全並列型アニーリングアルゴリズム
(日本語) Kyo Kuroki, (日本語) Satoru Jimbo, (日本語) Thiem Van Chu, (日本語) Masato Motomura, (日本語) Kazushi Kawamura
Workshop,2024
BibTeX
農機シェアリング問題を対象としたスケーラブルなイジングモデル定式化手法
(日本語) Daiki Okonogi, (日本語) Satoru Jimbo, (日本語) Thiem Van Chu, (日本語) Masato Motomura, (日本語) Kazushi Kawamura
Workshop,2024
BibTeX

2023

[Best Paper Nomination] Vector-Processing for Mobile Devices: Benchmark and Analysis
Alireza Khadem, (日本語) Daichi Fujiki, Nishil Talati, Scott A. Mahlke, Reetuparna Das
IEEE International Symposium on Workload Characterization,International Conference,2023
BibTeX
[Best Poster Award] Optimized Deep MLP for Tensor Train-based Inference Engine
(日本語) Jiale Yan, (日本語) Masato Motomura
IEEE Symposium on Low-Power and High-Speed Chips and Systems (COOL Chips),International Conference,2023
BibTeX
[Invited – Keynote] The Future of Low-bitwidth Reconfigurable and Parallel AI Computing
(日本語) Masato Motomura
Workshop,2023
BibTeX
[Invited] AI Computing – Tackling the Explosions of Data to Process and Decisions to Make
(日本語) Masato Motomura
Workshop,2023
BibTeX
[Invited] AIエッジの今後を展望する
(日本語) Masato Motomura
Workshop,2023
BibTeX
[Invited] Pianissimo: A Sub-mW Class DNN Accelerator with Progressive Bit-by-Bit Datapath Architecture for Adaptive Inference at Edge
(日本語) Junnosuke Suzuki, (日本語) Mari Yasunaga, (日本語) Ángel López García-Arias, (日本語) Yasuyuki Okoshi, (日本語) Shungo Kumazawa, (日本語) Kota Ando, (日本語) Kazushi Kawamura, (日本語) Thiem Van Chu, (日本語) Masato Motomura
Workshop,2023
BibTeX
[Invited] エッジ知能の実現に向けた低ビット幅表現・並列処理AIエンジン群の研究
(日本語) Masato Motomura
Workshop,2023
BibTeX
[Invited] 動的再構成プロセッサの研究開発と事業化 及びAI分野への展開
(日本語) Masato Motomura
Workshop,2023
BibTeX
[Invited] 問題に応じて計算手法を選択・最適化するアニーリングプロセッサLSI「Amorphica」
(日本語) Kazushi Kawamura
Workshop,2023
BibTeX
[Invited] 学習/数理モデルに基づく時空間展開型アーキテクチャの創出と応用プロジェクトの社会実装
(日本語) Kazushi Kawamura
Workshop,2023
BibTeX
[Invited] 超高次元分散ベクトル表現を基軸とする 融合型AIコンピューティング基盤の開拓
(日本語) Masato Motomura
Workshop,2023
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[Invited] 非フォンノイマン・デジタル コンピューティングの研究動向
(日本語) Masato Motomura
Workshop,2023
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[Keynote] Tackling the Explosions of Data and Solutions with Low-Bitwidth Computing Architectures
(日本語) Masato Motomura
Workshop,2023
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[優秀ポスター賞-学生部門] アニーリングプロセッサにおける解探索効率化のための動的温度制御法の検討
(日本語) Genta Inoue, (日本語) Daiki Okonogi, (日本語) Thiem Van Chu, (日本語) Jaehoon Yu, (日本語) Masato Motomura, (日本語) Kazushi Kawamura
Workshop,2023
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[優秀構想発表賞] ニューラルネットワークの学習コスト削減に向けた学習前刈込・強い宝くじ仮説の研究
(日本語) Hikari Otsuka
Workshop,2023
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[研究会優秀講演賞-若手部門] Pianissimo: エッジでの適応的な推論を実現するサブmWクラスDNNアクセラレータ
(日本語) Junnosuke Suzuki, (日本語) Mari Yasunaga, (日本語) Ángel López García-Arias, (日本語) Yasuyuki Okoshi, (日本語) Shungo Kumazawa, (日本語) Kota Ando, (日本語) Kazushi Kawamura, (日本語) Thiem Van Chu, (日本語) Masato Motomura
Workshop,2023
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A Fully-Parallel Annealing Algorithm with Autonomous Pinning Effect Control for Various Combinatorial Optimization Problems
(日本語) Daiki Okonogi, (日本語) Satoru Jimbo, (日本語) Kota Ando, (日本語) Thiem Van Chu, (日本語) Jaehoon Yu, (日本語) Masato Motomura, (日本語) Kazushi Kawamura
IEICE Transactions on Information and Systems,Journal Papers,2023
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A Highly Accurate and Parallel Vision MLP FPGA Accelerator based on FP7/8 SIMD Operations
(日本語) Mari Yasunaga, (日本語) Junnosuke Suzuki, (日本語) Masato Watanabe, (日本語) Kazushi Kawamura, (日本語) Thiem Van Chu, (日本語) Jaehoon Yu, (日本語) Masato Motomura
International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC),International Conference,2023
BibTeX
Amorphica: 4-Replica 512 Fully Connected Spin 336MHz Metamorphic Annealer with Programmable Optimization Strategy and Compressed-Spin-Transfer Multi-Chip Extension
(日本語) Kazushi Kawamura, (日本語) Jaehoon Yu, (日本語) Daiki Okonogi, (日本語) Satoru Jimbo, (日本語) Genta Inoue, (日本語) Akira Hyodo, (日本語) Ángel López García-Arias, (日本語) Kota Ando, Bruno Hideki Fukushima-Kimura, Ryota Yasudo, (日本語) Thiem Van Chu, (日本語) Masato Motomura
International Solid-State Circuits Conference (ISSCC),International Conference,2023
BibTeX
Decision Forest Training Accelerator Based on Binary Feature Decomposition
(日本語) Thiem Van Chu, (日本語) Yu Mizutani, (日本語) Yuta Nagahara, (日本語) Shungo Kumazawa, (日本語) Kazushi Kawamura, (日本語) Jaehoon Yu, (日本語) Masato Motomura
International Symposium on Field-Programmable Custom Computing Machines (FCCM),International Conference,2023
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Flexibly Controllable Dynamic Cooling Methods for Solid-State Annealing Processors to Improve Combinatorial Optimization Performance
(日本語) Genta Inoue, (日本語) Daiki Okonogi, (日本語) Thiem Van Chu, (日本語) Jaehoon Yu, (日本語) Masato Motomura, (日本語) Kazushi Kawamura
IEEE Symposium on Low-Power and High-Speed Chips and Systems, COOL Chips 26,International Conference,2023
BibTeX
FP8 SIMD演算に基づく高精度・高並列なFPGA向けNNアクセラレータ
(日本語) Mari Yasunaga, (日本語) Junnosuke Suzuki, (日本語) Kazushi Kawamura, (日本語) Thiem Van Chu, (日本語) Masato Motomura, (日本語) Jaehoon Yu
Workshop,2023
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Mixing time and simulated annealing for the stochastic cellular automata
Bruno Hideki Fukushima-Kimura, Satoshi Handa, Katsuhiro Kamakura, Yoshinori Kamijima, (日本語) Kazushi Kawamura, Akira Sakai
Journal of Statistical Physics,Journal Papers,2023
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Multicoated and Folded Graph Neural Networks with Strong Lottery Tickets
(日本語) Jiale Yan, (日本語) Hiroaki Ito, (日本語) Ángel López García-Arias, (日本語) Yasuyuki Okoshi, (日本語) Hikari Otsuka, (日本語) Kazushi Kawamura, (日本語) Thiem Van Chu, (日本語) Masato Motomura
Learning on Graph Conference 2023,International Conference,2023
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MVC: Enabling Fully Coherent Multi-Data-Views through the Memory Hierarchy with Processing in Memory
(日本語) Daichi Fujiki
Proceedings of the 56th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO 2023),International Conference,2023
BibTeX
Pianissimo: A Sub-mW Class DNN Accelerator with Progressive Bit-by-Bit Datapath Architecture for Adaptive Inference at Edge
(日本語) Junnosuke Suzuki, (日本語) Jaehoon Yu, (日本語) Mari Yasunaga, (日本語) Ángel López García-Arias, (日本語) Yasuyuki Okoshi, (日本語) Shungo Kumazawa, (日本語) Kota Ando, (日本語) Kazushi Kawamura, (日本語) Thiem Van Chu, (日本語) Masato Motomura
Symposium on VLSI Technology and Circuits, 2023,International Conference,2023
BibTeX
Pianissimo: A Sub-mW Class DNN Accelerator With Progressively Adjustable Bit-Precision
(日本語) Junnosuke Suzuki, (日本語) Jaehoon Yu, (日本語) Mari Yasunaga, (日本語) Ángel López García-Arias, (日本語) Yasuyuki Okoshi, (日本語) Shungo Kumazawa, (日本語) Kota Ando, (日本語) Kazushi Kawamura, (日本語) Thiem Van Chu, (日本語) Masato Motomura
IEEE Access,Journal Papers,2023
BibTeX
Recurrent Residual Networks Contain Stronger Lottery Tickets
(日本語) Ángel López García-Arias, (日本語) Yasuyuki Okoshi, Masanori Hashimoto, (日本語) Masato Motomura, (日本語) Jaehoon Yu
IEEE Access,Journal Papers,2023
BibTeX
Stochastic optimization: Glauber dynamics versus stochastic cellular automata
Bruno Hideki Fukushima-Kimura, Yoshinori Kamijima, (日本語) Kazushi Kawamura, Akira Sakai
Transactions of the Institute of Systems, Control and Information Engineers,Journal Papers,2023
BibTeX
TT-MLP: Tensor Train Decomposition on Deep MLPs
(日本語) Jiale Yan, (日本語) Kota Ando, (日本語) Jaehoon Yu, (日本語) Masato Motomura
IEEE Access,Journal Papers,2023
BibTeX
同変性ネットワークに基づく自律走行向け強化学習手法
(日本語) Akihiro Shioda, (日本語) Yuki Ichikawa, (日本語) Kazushi Kawamura, (日本語) Thiem Van Chu, (日本語) Masato Motomura, (日本語) Jaehoon Yu
Workshop,2023
BibTeX
強い宝くじ仮説に基づく超軽量物体検出ニューラルネットワーク
(日本語) Hikari Otsuka, (日本語) Yasuyuki Okoshi, (日本語) Ángel López García-Arias, (日本語) Kazushi Kawamura, (日本語) Thiem Van Chu, (日本語) Jaehoon Yu, (日本語) Masato Motomura
Workshop,2023
BibTeX
表形式データを対象とした決定木とニューラルネットワークの融合型機械学習手法の研究
(日本語) Tsukasa Yamakura, (日本語) Kazushi Kawamura, (日本語) Masato Motomura, (日本語) Thiem Van Chu
Workshop,2023
BibTeX

2022

[Invited] AI Algorithm Innovation Calls for Innovative AI Accelerator Designs
(日本語) Masato Motomura
Workshop,2022
BibTeX
[Invited] AI-コンピューティング-集積回路:技術変革のうねりとその未来
(日本語) Masato Motomura
Workshop,2022
BibTeX
[Invited] Exploring AI Computing Architectures Toward Future SoC
(日本語) Masato Motomura
Workshop,2022
BibTeX
[Invited] Hiddenite: CNN Inference Accelerator for Randomly Weighted Neural Networks
(日本語) Jaehoon Yu
Workshop,2022
BibTeX
[Invited] Hiddenite: オンチップモデル構築を用いる隠れニューラルネットワーク理論の推論テンソルエンジン
(日本語) Kazutoshi Hirose
Workshop,2022
BibTeX
[Invited] HotChips2021にみる機械学習アクセラレータの動向:東工大DNN推論アクセラレータの発表内容紹介,及びその他の同分野発表サマリ
(日本語) Masato Motomura
Workshop,2022
BibTeX
[Invited] エッジAIの現状と展望: アルゴリズムと ハードウェアの協創の観点から
(日本語) Masato Motomura
Workshop,2022
BibTeX
[Invited] データ再利用性を考慮した高効率CNN推論アーキテクチャ
(日本語) Jaehoon Yu
Workshop,2022
BibTeX
[Invited] 動的再構成プロセッサの研究開発と事業化 及びAI分野への展開
(日本語) Masato Motomura
Workshop,2022
BibTeX
[Invited] 学習/数理モデルに基づく時空間展開型アーキテクチャ
(日本語) Masato Motomura
Workshop,2022
BibTeX
[Invited] 学習/数理モデルに基づく時空間展開型アーキテクチャの創出と応用
(日本語) Masato Motomura
Workshop,2022
BibTeX
[Invited] 構造型情報処理に関する先駆的研究とそのAI情報処理への展開
(日本語) Masato Motomura
Workshop,2022
BibTeX
[Invited] 構造型情報処理基盤の確立を目指して
(日本語) Jaehoon Yu
Workshop,2022
BibTeX
[Invited] 特徴空間事前分割型決定森推論アクセラレータ
(日本語) Thiem Van Chu
Workshop,2022
BibTeX
[Invited] 知能コンピューティングを加速するアーキテクチャ基盤技術
(日本語) Masato Motomura
Workshop,2022
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[Invited] 隠れネットワーク理論に基づく新たなDNN推論エンジンチップ(Hiddenite)の紹介
(日本語) Masato Motomura
Workshop,2022
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[Keynote] Exploring AI Computing Architectures Toward Future SoC
(日本語) Masato Motomura
Workshop,2022
BibTeX
[WIP最優秀賞] 2スピン同時フリップを並列試行可能なシミュレーテッドアニーリング手法の検討
(日本語) Akira Hyodo, (日本語) Satoru Jimbo, (日本語) Thiem Van Chu, (日本語) Jaehoon Yu, (日本語) Masato Motomura, (日本語) Kazushi Kawamura
Workshop,2022
BibTeX
[第22回山﨑貞一賞-半導体及びシステム・情報・エレクトロニクス分野] 動的再構成プロセッサの研究開発と事業化及びAI分野への展開
(日本語) Masato Motomura
Workshop,2022
BibTeX
[第54回市村学術賞 功績賞] 構造型情報処理に関する先駆的研究とそのAI処理分野への展開
(日本語) Masato Motomura
Workshop,2022
BibTeX
A Hybrid Integer Encoding Method for Obtaining High-quality Solutions of Quadratic Knapsack Problems on Solid-state Annealers
(日本語) Satoru Jimbo, (日本語) Daiki Okonogi, (日本語) Kota Ando, (日本語) Thiem Van Chu, (日本語) Jaehoon Yu, (日本語) Masato Motomura, (日本語) Kazushi Kawamura
IEICE Transactions on Information and Systems,Journal Papers,2022
BibTeX
A Unhealthy Plant Identification System Using a Generative Adversarial Network
Satida Sookpong, Teerasit Kasetkasem, Teera Phatrapornnant, (日本語) Jaehoon Yu
International Conference on Electrical Engineering/Electronics, Computer, Telecommunications and Information Technology (ECTI-CON),International Conference,2022
BibTeX
Hiddenite: 4K-PE Hidden Network Inference 4D-Tensor Engine Exploiting On-Chip Model Construction Achieving 34.8-to-16.0TOPS/W for CIFAR-100 and ImageNet
(日本語) Kazutoshi Hirose, (日本語) Jaehoon Yu, (日本語) Kota Ando, (日本語) Yasuyuki Okoshi, (日本語) Ángel López García-Arias, (日本語) Junnosuke Suzuki, (日本語) Thiem Van Chu, (日本語) Kazushi Kawamura, (日本語) Masato Motomura
International Solid-State Circuits Conference (ISSCC),International Conference,2022
BibTeX
IEEE Fellow “for contributions to memory-logic integration of reconfigurable chip architecture.”
(日本語) Masato Motomura
Workshop,2022
BibTeX
Investigating Small Device Implementation of FRET-based Optical Reservoir Computing
Masafumi Tanaka, (日本語) Jaehoon Yu, Masaki Nakagawa, Naoya Tate, Masanori Hashimoto
The IEEE International Midwest Symposium on Circuits and Systems (MWSCAS),International Conference,2022
BibTeX
Multicoated Supermasks Enhance Hidden Networks
(日本語) Yasuyuki Okoshi, (日本語) Ángel López García-Arias, (日本語) Kazutoshi Hirose, (日本語) Kota Ando, (日本語) Kazushi Kawamura, (日本語) Thiem Van Chu, (日本語) Masato Motomura, (日本語) Jaehoon Yu
International Conference on Machine Learning (ICML),International Conference,2022
BibTeX
QKP-QUBO変換におけるHybridエンコーディング方式
(日本語) Satoru Jimbo, (日本語) Daiki Okonogi, (日本語) Kota Ando, (日本語) Thiem Van Chu, (日本語) Jaehoon Yu, (日本語) Masato Motomura, (日本語) Kazushi Kawamura
Workshop,2022
BibTeX
Via-switch FPGA with transistor-free programmability enabling energy-efficient near-memory parallel computation
Masanori Hashimoto, X Bai, Naoki Banno, Munehiro Tada, Toshitsugu Sakamoto, (日本語) Jaehoon Yu, Ryutaro Doi, Hidetoshi Onodera, Takashi Imagawa, Hiroyuki Ochi
Japanese Journal of Applied Physics,Journal Papers,2022
BibTeX
イジング計算機の解探索を効率化させる整数エンコーディング手法の提案と評価
(日本語) Satoru Jimbo, (日本語) Daiki Okonogi, (日本語) Thiem Van Chu, (日本語) Jaehoon Yu, (日本語) Masato Motomura, (日本語) Kazushi Kawamura
Workshop,2022
BibTeX
ピンニングパラメータの自律制御機構を搭載した全スピン並列更新アニーリング マシン
(日本語) Daiki Okonogi, (日本語) Satoru Jimbo, (日本語) Thiem Van Chu, (日本語) Jaehoon Yu, (日本語) Masato Motomura, (日本語) Kazushi Kawamura
Workshop,2022
BibTeX
全並列アニーリングのための自律的パラメータ制御
(日本語) Daiki Okonogi, (日本語) Satoru Jimbo, (日本語) Kota Ando, (日本語) Thiem Van Chu, (日本語) Jaehoon Yu, (日本語) Masato Motomura, (日本語) Kazushi Kawamura
Workshop,2022
BibTeX
外部メモリアクセス抑制による高効率疎行列積アクセラレータの研究
(日本語) Yuta Nagahara, (日本語) Kota Ando, (日本語) Kazushi Kawamura, (日本語) Jaehoon Yu, (日本語) Masato Motomura, (日本語) Thiem Van Chu
Workshop,2022
BibTeX
巡回セールスマン問題を対象とした並列アニーリング手法の評価
(日本語) Genta Inoue, (日本語) Daiki Okonogi, (日本語) Thiem Van Chu, (日本語) Jaehoon Yu, (日本語) Masato Motomura, (日本語) Kazushi Kawamura
Workshop,2022
BibTeX

2021

[Best Paper Award] A High-Performance and Flexible FPGA Inference Accelerator for Decision Forests Based on Prior Feature Space Partitioning
(日本語) Thiem Van Chu, (日本語) Ryuichi Kitajima, (日本語) Kazushi Kawamura, (日本語) Jaehoon Yu, (日本語) Masato Motomura
International Conference on Field-Programmable Technology (FPT),International Conference,2021
BibTeX
[Invited] AIチップの現状と今後について
(日本語) Masato Motomura
Workshop,2021
BibTeX
[Invited] CGRAs for Broad Embedded Market & for Neural Networks
(日本語) Masato Motomura
Workshop,2021
BibTeX
[Invited] LSI技術が開く構造型情報処理の新展開
(日本語) Masato Motomura
Workshop,2021
BibTeX
[Invited] ポストノイマン・ポストムーア時代の情報処理アーキテクチャ
(日本語) Masato Motomura
Workshop,2021
BibTeX
[Invited] ⼆値・三値・量⼦化ニューラルネットワークの推論LSIと学習アルゴリズム
(日本語) Kota Ando
Workshop,2021
BibTeX
[Invited] 全結合・全並列型アニーリングHWの紹介 ~ その数理モデルからLSI実装まで ~
(日本語) Masato Motomura
Workshop,2021
BibTeX
[Moderator] “Hot” Techs for “Cool” AI Computing: Do We have Enough Tricks?
(日本語) Masato Motomura
Workshop,2021
BibTeX
[セッション特別賞] GPUを活用した全結合・全並列アニーリング手法の高速化検討
(日本語) Kaisei Okawa, (日本語) Kazushi Kawamura, Gregory Gutmann, (日本語) Thiem Van Chu, (日本語) Jaehoon Yu, (日本語) Masato Motomura
Workshop,2021
BibTeX
[優秀構想発表賞] 多ビットマスクを用いた高精度・軽量HNNの研究
(日本語) Yasuyuki Okoshi
Workshop,2021
BibTeX
A 96-MB 3D-Stacked SRAM Using Inductive Coupling with 0.4-V Transmitter, Termination Scheme and 12:1 SerDes in 40-nm CMOS
Kota Shiba, Tatsuo Omori, Kodai Ueyoshi, (日本語) Kota Ando, (日本語) Kazutoshi Hirose, Shinya Takamaeda-Yamazaki, (日本語) Masato Motomura, Mototsugu Hamada, Tadahiro Kuroda
IEEE Transactions on Circuits and Systems I,Journal Papers,2021
BibTeX
Edge Inference Engine for Deep & Random Sparse Neural Networks with 4-bit Cartesian-Product MAC Array and Pipelined Activation Aligner
(日本語) Kota Ando, (日本語) Jaehoon Yu, (日本語) Kazutoshi Hirose, Hiroki Nakahara, (日本語) Kazushi Kawamura, (日本語) Thiem Van Chu, (日本語) Masato Motomura
Hot Chips 33 (Poster),International Conference,2021
BibTeX
ExtraFerns: Fully Parallel Ensemble Learning Technique with Random Projection and Non-Greedy yet Minimal Memory Access Training
(日本語) Shungo Kumazawa, (日本語) Kazushi Kawamura, (日本語) Thiem Van Chu, (日本語) Masato Motomura, (日本語) Jaehoon Yu
International Journal of Networking and Computing,Journal Papers,2021
BibTeX
Hidden-Fold Networks: Random Recurrent Residuals Using Sparse Supermasks
(日本語) Ángel López García-Arias, Masanori Hashimoto, (日本語) Masato Motomura, (日本語) Jaehoon Yu
The British Machine Vision Conference (BMVC),International Conference,2021
BibTeX
MUX Granularity-Oriented Iterative Technology Mapping for Implementing Compute-Intensive Applications on Via-Switch FPGA
Takashi Imagawa, (日本語) Jaehoon Yu, Masanori Hashimoto, Hiroyuki Ochi
Design, Automation and Test in Europe Conference (DATE),International Conference,2021
BibTeX
ProgressiveNN: Achieving Computational Scalability with Dynamic Bit-Precision Adjustment by MSB-first Accumulative Computation
(日本語) Junnosuke Suzuki, Tomohiro Kaneko, (日本語) Kota Ando, (日本語) Kazutoshi Hirose, (日本語) Kazushi Kawamura, (日本語) Thiem Van Chu, (日本語) Masato Motomura, (日本語) Jaehoon Yu
International Journal of Networking and Computing,Journal Papers,2021
BibTeX
こんなとこにもイジングマシン
雑誌記事
Books,2021
BibTeX
スマホやロボットなどで高効率なAI処理を行うプロセッサーアーキテクチャーを開発
東工大プレスリリース
Books,2021
BibTeX
ビットスケーラブルCNNにおける計算量・精度トレードオフ制御手法の検討
(日本語) Junnosuke Suzuki, (日本語) Kota Ando, 廣瀬 一俊, (日本語) Kazushi Kawamura, (日本語) Thiem Van Chu, (日本語) Masato Motomura, (日本語) Jaehoon Yu
Workshop,2021
BibTeX
乱数生成ノードの並列閾値最適化に基づくエッジ指向決定木アンサンブル学習
(日本語) Shungo Kumazawa, (日本語) Kazushi Kawamura, (日本語) Thiem Van Chu, (日本語) Masato Motomura, (日本語) Jaehoon Yu
Workshop,2021
BibTeX
入力空間のランダム射影と分割に基づくFernアンサンブル学習
(日本語) Shungo Kumazawa, (日本語) Kazushi Kawamura, (日本語) Thiem Van Chu, (日本語) Masato Motomura, (日本語) Jaehoon Yu
Workshop,2021
BibTeX
学習/数理モデルに基づく時空間展開型アーキテクチャの創出と応用
(日本語) Masato Motomura
Workshop,2021
BibTeX
対称二進表現に基づくビットスケーラブルCNN推論手法
(日本語) Junnosuke Suzuki, (日本語) Kota Ando, 廣瀬 一俊, (日本語) Kazushi Kawamura, (日本語) Thiem Van Chu, (日本語) Masato Motomura, (日本語) Jaehoon Yu
Workshop,2021
BibTeX
特徴空間事前分割に基づく決定木アンサンブルのFPGA推論アクセラレータ
(日本語) Ryuichi Kitajima, (日本語) Kazushi Kawamura, (日本語) Jaehoon Yu, (日本語) Masato Motomura, (日本語) Thiem Van Chu
Workshop,2021
BibTeX

2020

[IEEE CS Tokyo/Japan Joint Local Chapters Young Author Award 2022] SeedEx: A Genome Sequencing Accelerator for Optimal Alignments in Subminimal Space
(日本語) Daichi Fujiki, Shunhao Wu, Nathan Ozog, Kush Goliya, David T. Blaauw, Satish Narayanasamy, Reetuparna Das
International Symposium on Microarchitecture (MICRO),International Conference,2020
BibTeX
[Invited] Designing AI Accelerator Chips for the Smarter Future
(日本語) Masato Motomura
Workshop,2020
BibTeX
[Invited] Domain-Specific Architectures for Boosting “Compute for Intelligence”
(日本語) Masato Motomura
Workshop,2020
BibTeX
[Invited] Reconfigurable and Domain-Specific Hardware for AI Computing
(日本語) Masato Motomura
Workshop,2020
BibTeX
[Invited] Stochastic Cellular Automata Annealing (SCA) and its Non-Quantum Silicon Chip Implementation
(日本語) Masato Motomura
Workshop,2020
BibTeX
[Invited] Stochastic Cellular Automata Annealing (SCA) and its Non-Quantum Silicon Chip Implementation: Realizing Fully-Parallel Spin-Updates for Fully-Connected Spin Systems
(日本語) Masato Motomura
Workshop,2020
BibTeX
[Invited] 学習/数理モデルに基づく時空間展開型アーキテクチャ
(日本語) Masato Motomura
Workshop,2020
BibTeX
[優秀構想発表賞] エッジAIのための推論精度と計算量のトレードオフ向上に関する研究
(日本語) Junnosuke Suzuki
Workshop,2020
BibTeX
[優秀若手発表賞] 二値化ニューラルネットワークのハードウェア指向精度向上手法の検討
大羽 由華, 村上 大輔, 中江 達哉, (日本語) Kota Ando, 浅井 哲也, (日本語) Masato Motomura, 高前田 伸也
Workshop,2020
BibTeX
[優秀講演賞] 無効ニューロン予測によるDNN計算効率化手法
植吉 晃大, 池田 泰我, (日本語) Kota Ando, (日本語) Kazutoshi Hirose, 浅井 哲也, 高前田 伸也, (日本語) Masato Motomura
Workshop,2020
BibTeX
[若手奨励賞] 効率的なDNN計算のための無効ニューロン予測手法の評価
池田 泰我, 植吉 晃大, (日本語) Kota Ando, (日本語) Kazutoshi Hirose, 浅井 哲也, (日本語) Masato Motomura, 高前田 伸也
Workshop,2020
BibTeX
A 3D-Stacked SRAM Using Inductive Coupling with Low-Voltage Transmitter and 12:1 SerDes
Kota Shiba, Tatsuo Omori, Kodai Ueyoshi, (日本語) Kota Ando, (日本語) Kazutoshi Hirose, Shinya Takamaeda-Yamazaki, (日本語) Masato Motomura, Mototsugu Hamada, Tadahiro Kuroda
IEEE International Symposium on Circuits and Systems (ISCAS),International Conference,2020
BibTeX
A Hardware-Efficient Weight Sampling Circuit for Bayesian Neural Networks
Yuki Hirayama, Tetsuya Asai, (日本語) Masato Motomura, Shinya Takamaeda-Yamazaki
International Journal of Networking and Computing,Journal Papers,2020
BibTeX
Dependency-Driven Trace-Based Network-on-Chip Emulation on FPGAs
(日本語) Thiem Van Chu, Kenji Kise, Kiyofumi Tanaka
ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA),International Conference,2020
BibTeX
ExtraFerns: Fully Parallel Ensemble Learning Technique with Non-Greedy yet Minimal Memory Access Training
(日本語) Shungo Kumazawa, (日本語) Kazushi Kawamura, (日本語) Thiem Van Chu, (日本語) Masato Motomura, (日本語) Jaehoon Yu
International Symposium on Computing and Networking (CANDAR),International Conference,2020
BibTeX
Hardware/Algorithm Co-optimization for Fully-Parallelized Compact Decision Tree Ensembles on FPGAs
Taiga Ikeda, Kento Sakurada, Atsuyoshi Nakamura, (日本語) Masato Motomura, Shinya Takamaeda-Yamazaki
International Symposium on Applied Reconfigurable Computing (ARC),International Conference,2020
BibTeX
Logarithm-Approximate Floating-Point Multiplier is Applicable to Power-Efficient Neural Network Training
Tai-Yu Cheng, Yukata Masuda, Jun Chen, (日本語) Jaehoon Yu, Masanori Hashimoto
Integration,Journal Papers,2020
BibTeX
Low-Cost Reservoir Computing using Cellular Automata and Random Forests
(日本語) Ángel López García-Arias, (日本語) Jaehoon Yu, Masanori Hashimoto
IEEE International Symposium on Circuits and Systems (ISCAS),International Conference,2020
BibTeX
Memory Efficient Training using Lookup-Table-based Quantization for Neural Network
Kazuki Onishi, (日本語) Jaehoon Yu, Masanori Hashimoto
IEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS),International Conference,2020
BibTeX
Novel Annealing Processor Is the Best Ever at Solving Combinatorial Optimization Problems
IEEE Spectrum
Books,2020
BibTeX
ProgressiveNN: Achieving Computational Scalability without Network Alteration by MSB-first Accumulative Computation
(日本語) Junnosuke Suzuki, (日本語) Kota Ando, (日本語) Kazutoshi Hirose, (日本語) Kazushi Kawamura, (日本語) Thiem Van Chu, (日本語) Masato Motomura, (日本語) Jaehoon Yu
International Symposium on Computing and Networking (CANDAR),International Conference,2020
BibTeX
Q&Aで分かるAIチップ
本村 真人(監修)
Books,2020
BibTeX
Real-time Tone Mapping: A State of the Art Report
Yafei Ou, Prasoon Ambalathankandy, Masayuki Ikebe, Shinya Takamaeda, (日本語) Masato Motomura, Tetsuya Asai
IEEE Transactions on Circuits and Systems for Video Technology,Journal Papers,2020
BibTeX
Selective Fine-Tuning on a Classifier Ensemble: Realizing Adaptive Neural Networks With a Diversified Multi-Exit Architecture
(日本語) Kazutoshi Hirose, Shinya Takamaeda-Yamazaki, (日本語) Jaehoon Yu, (日本語) Masato Motomura
IEEE Access,Journal Papers,2020
BibTeX
STATICA: A 512-Spin 0.25M-Weight Annealing Processor With an All-Spin-Updates-at-Once Architecture for Combinatorial Optimization With Complete Spin-Spin Interactions
Kasho Yamamoto, (日本語) Kazushi Kawamura, (日本語) Kota Ando, Normann Mertig, Takashi Takemoto, Masanao Yamaoka, Hiroshi Teramoto, Akira Sakai, Shinya Takamaeda-Yamazaki, (日本語) Masato Motomura
IEEE Journal of Solid-State Circuits (JSSC),Journal Papers,2020
BibTeX
STATICA: A 512-Spin 0.25M-Weight Full-Digital Annealing Processor with a Near-Memory All-Spin-Updates-at-Once Architecture for Combinatorial Optimization with Complete Spin-Spin Interactions
Kasho Yamamoto, (日本語) Kota Ando, Normann Mertig, Takashi Takemoto, Masanao Yamaoka, Hiroshi Teramoto, Akira Sakai, Shinya Takamaeda-Yamazaki, (日本語) Masato Motomura
International Solid-State Circuits Conference (ISSCC),International Conference,2020
BibTeX
Via-Switch FPGA: 65nm CMOS Implementation and Architecture Extension for AI Applications
Masanori Hashimoto, Xu Bai, Naoki Banno, Munehiro Tada, Toshitsugu Sakamoto, (日本語) Jaehoon Yu, Ryutaro Doi, Yusuke Araki, Hidetoshi Onodera, Takashi Imagawa, Hiroyuki Ochi, Kazutoshi Wakabayashi, Yukio Mitsuyama, Tadahiko Sugibayashi
International Solid-State Circuits Conference (ISSCC),International Conference,2020
BibTeX
深層ニューラルネットワーク向けプロセッサ技術の実例と展望
(日本語) Masato Motomura, 高前田 伸也, 植吉 晃大, (日本語) Kota Ando, (日本語) Kazutoshi Hirose
電子情報通信学会和文論文誌C,Journal Papers,2020
BibTeX
組合せ最適化問題を高速に解く新しいアニーリングマシンを開発
東工大プレスリリース
Books,2020
BibTeX

2019

[2019年度研究会優秀賞] 決定論的変分推論に基づくベイジアンCNNの検討
平山 侑樹, 浅井 哲也, (日本語) Masato Motomura, 高前田 伸也
Workshop,2019
BibTeX
[Invited] AI Computing: The Promised Land for Computer Architecture Innovation?
(日本語) Masato Motomura
Workshop,2019
BibTeX
[Invited] AI Computing: The Promised Land for Hardware?
(日本語) Masato Motomura
Workshop,2019
BibTeX
[Invited] AIチップ: 世界の研究動向と東工大の研究戦略
(日本語) Masato Motomura
Workshop,2019
BibTeX
[Invited] AIチップの世界動向と日本がとるべき戦略
(日本語) Masato Motomura
Workshop,2019
BibTeX
[Invited] AI関連半導体技術の動向
(日本語) Masato Motomura
Workshop,2019
BibTeX
[Invited] Intelligence at the Edge: Frontiers for Energy-Efficient Hardware Architectures
(日本語) Masato Motomura
Workshop,2019
BibTeX
[Tutorial] AI Computing: What it is about & How hardware can help it out
(日本語) Masato Motomura
Workshop,2019
BibTeX
[若手優秀講演賞] 効率的なDNN計算のための無効ニューロン予測手法の評価
池田 泰我, 植吉 晃大, (日本語) Kota Ando, (日本語) Kazutoshi Hirose, 浅井 哲也, (日本語) Masato Motomura, 高前田 伸也
Workshop,2019
BibTeX
A Resource-Efficient Weight Sampling Method for Bayesian Neural Networks Accelerators
Yuki Hirayama, Tetsuya Asai, (日本語) Masato Motomura, Shinya Takamaeda-Yamazaki
International Symposium on Computing and Networking (CANDAR),International Conference,2019
BibTeX
A Study on a Low Power Optimization Algorithm for An Edge-AI Device
(日本語) Tatsuya Kaneko, Kentaro Orimo, Itaru Hida, Shinya Takamaeda-Yamazaki, Masayuki Ikebe, (日本語) Masato Motomura, Tetsuya Asai
Nonlinear Theory and Its Applications,Journal Papers,2019
BibTeX
AIエッジコンピューティングへの希望と展望
(日本語) Masato Motomura
Books,2019
BibTeX
AIエッジコンピューティングへの希望と展望
(日本語) Masato Motomura
Books,2019
BibTeX
An Adaptive Global and Local Tone Mapping Algorithm Implemented on FPGA
Prasoon Ambalathankandy, Masayuki Ikebe, Takashi Yoshida, Takeshi Shimada, Shinya Takamaeda-Yamazaki, (日本語) Masato Motomura, Tetsuya Asai
IEEE Transactions on Circuits and Systems for Video Technology,Journal Papers,2019
BibTeX
Approach to Reservoir Computing with Schmitt Trigger Oscillator-Based Analog Neural Circuits
Seunggoo Rim, Shunya Suzuki, Shinya Takamaeda-Yamazaki, Masayuki Ikebe, (日本語) Masato Motomura, Tetsuya Asai
Japan-Korea Joint Workshop on Complex Communication Sciences,International Conference,2019
BibTeX
DeltaNet: Differential Binary Neural Network
Yuka Oba, (日本語) Kota Ando, Tetsuya Asai, (日本語) Masato Motomura, Shinya Takamaeda-Yamazaki
IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP),International Conference,2019
BibTeX
Distilling Knowledge for Non-Neural Networks
Shota Fukui, (日本語) Jaehoon Yu, Masanori Hashimoto
Asia-Pacific Signal and Information Processing Association (APSIPA),International Conference,2019
BibTeX
Dither NN: Hardware/Algorithm Co-Design for Accurate Quantized Neural Networks
(日本語) Kota Ando, Kodai Ueyoshi, Yuka Oba, (日本語) Kazutoshi Hirose, Ryota Uematsu, Takumi Kudo, Masayuki Ikebe, Tetsuya Asai, Shinya Takamaeda-Yamazaki, (日本語) Masato Motomura
IEICE Transactions on Information and Systems,Journal Papers,2019
BibTeX
Experimental Demonstration of Physical Reservoir Computing with Nonlinear Electronic Devices
Shunya Suzuki, Seunggoo Rim, Shinya Takamaeda-Yamazaki, Masayuki Ikebe, (日本語) Masato Motomura, Tetsuya Asai
RISP International Workshop on Nonlinear Circuits, Communications and Signal Processing,International Conference,2019
BibTeX
FPGA-Based Annealing Processor with Time-Division Multiplexing
Kasho Yamamoto, Masayuki Ikebe, Tetsuya Asai, (日本語) Masato Motomura, Shinya Takamaeda-Yamazaki
IEICE Transactions on Information and Systems,Journal Papers,2019
BibTeX
FPGA-Based FORCE Learning Accelerator towards Real-Time Online Reservoir Computing
Koyo Minamikawa, Shinya Takamaeda-Yamazaki, Masayuki Ikebe, (日本語) Masato Motomura, Tetsuya Asai
RISP International Workshop on Nonlinear Circuits, Communications and Signal Processing,International Conference,2019
BibTeX
Hardware-Oriented Algorithm and Architecture for Generative Adversarial Networks
(日本語) Tatsuya Kaneko, Masayuki Ikebe, Shinya Takamaeda-Yamazaki, (日本語) Masato Motomura, Tetsuya Asai
Journal of Signal Processing,Journal Papers,2019
BibTeX
Hardware-Oriented Algorithm and Architecture for Generative Adversarial Networks
(日本語) Tatsuya Kaneko, Masayuki Ikebe, Shinya Takamaeda-Yamazaki, (日本語) Masato Motomura, Tetsuya Asai
RISP International Workshop on Nonlinear Circuits, Communications and Signal Processing,International Conference,2019
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LEF: An Effective Routing Algorithm for Two-Dimensional Meshes
(日本語) Thiem Van Chu, Kenji Kise
IEICE Transactions on Information and Systems,Journal Papers,2019
BibTeX
Minimizing Energy for Neural Network Training with Logarithm-Approximate Floating-Point Multiplier
Tai-Yu Cheng, (日本語) Jaehoon Yu, Masanori Hashimoto
International Symposium on Power and Timing Modeling, Optimization and Simulation,International Conference,2019
BibTeX
Parallelism-Flexible Convolution Core for Sparse Convolutional Neural Networks on FPGA
Salita Sombatsiri, Seiya Shibata, Yuki Kobayashi, Hiroaki Inoue, Takashi Takenaka, Takeo Hosomi, (日本語) Jaehoon Yu, Yoshinori Takeuchi
Journal Papers,2019
BibTeX
QUEST: Multi-Purpose Log-Quantized DNN Inference Engine Stacked on 96-MB 3-D SRAM Using Inductive Coupling Technology in 40-nm CMOS
Kodai Ueyoshi, (日本語) Kota Ando, (日本語) Kazutoshi Hirose, Shinya Takamaeda-Yamazaki, Mototsugu Hamada, Tadahiro Kuroda, (日本語) Masato Motomura
IEEE Journal of Solid-State Circuits,Journal Papers,2019
BibTeX
Radiography Contrast Enhancement: Smoothed LHE Filter, a Practical Solution for Digital X-rays with Mach Band
Prasoon Ambalathankandy, Yafei Ou, Jyotsna Kochiyil, Shinya Takamaeda-Yamazaki, (日本語) Masato Motomura, Tetsuya Asai, Masayuki Ikebe
International Conference on Digital Image Computing: Techniques and Applications,International Conference,2019
BibTeX
Sneak Path Free Reconfiguration with Minimized Programming Steps for Via-switch Crossbar Based FPGA
Ryutaro Doi, (日本語) Jaehoon Yu, Masanori Hashimoto
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems,Journal Papers,2019
BibTeX
Ternarized Backpropagation: A Hardware-Oriented Optimization Algorithm for Edge-Oriented AI Devices
(日本語) Tatsuya Kaneko, Masayuki Ikebe, Shinya Takamaeda-Yamazaki, (日本語) Masato Motomura, Tetsuya Asai
RIEC International Symposium on Brain Functions and Brain Computer,International Conference,2019
BibTeX
Training Data Reduction using Support Vectors for Neural Networks
Toranosuke Tanio, Kouya Takeda, (日本語) Jaehoon Yu, Masanori Hashimoto
Asia-Pacific Signal and Information Processing Association (APSIPA),International Conference,2019
BibTeX
コンピューティングアーキテクチャ
(日本語) Masato Motomura
Books,2019
BibTeX
深層学習プロセッサの展望
(日本語) Masato Motomura
Books,2019
BibTeX

2018

[Best Paper Nomination] AxNoC: Low-power Approximate Network-on-Chips using Critical-Path Isolation
Akram Ben Ahmed, (日本語) Daichi Fujiki, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano
International Symposium on Networks-on-Chip (NOCS),International Conference,2018
BibTeX
[Invited] Hardware-Oriented Approaches for Accelerating “AI” Workloads
(日本語) Masato Motomura
Workshop,2018
BibTeX
[Invited] Intelligence at the Edge: Frontiers for Energy-Efficient Hardware Architectures
(日本語) Masato Motomura
Workshop,2018
BibTeX
[Invited] Structure-Oriented Computing: Where Software Redefines Hardware Architecture
(日本語) Masato Motomura
Workshop,2018
BibTeX
A Novel Iris-Center Detection Algorithm towards Gaze Estimation Targeting Molecular Cellular Automata
Naoto Iwamaru, Shinya Takamaeda-Yamazaki, Masayuki Ikebe, (日本語) Masato Motomura, Tetsuya Asai
International Workshop on Molecular Architectonics,International Conference,2018
BibTeX
A Study on Ternary Back Propagation Algorithm for Embedded Egde-AI Processing
(日本語) Tatsuya Kaneko, Masayuki Ikebe, Shinya Takamaeda-Yamazaki, (日本語) Masato Motomura, Tetsuya Asai
Joint Workshop of UCL-ICN, NTT, UCL-Gatsby and AIBS: Analysis and Synthesis for Human/Artificial Cognition and Behaviour,International Conference,2018
BibTeX
Adapting Soft Cascade to MAC Operations of Convolutional Neural Networks
Kenshi Ito, (日本語) Jaehoon Yu, Masanori Hashimoto
International Symposium on Multimedia and Communication Technology,International Conference,2018
BibTeX
Analysis of Smoothed LHE Methods for Processing Images with Optical Illusions
Prasoon Ambalathankandy, Takeshi Shimada, Shinya Takamaeda-Yamazaki, (日本語) Masato Motomura, Tetsuya Asai, Masayuki Ikebe
IEEE International Conference on Visual Communications and Image Processing,International Conference,2018
BibTeX
Area and Energy Optimization for Bit-Serial Log-Quantized DNN Accelerator with Shared Accumulators
Takumi Kudo, Kodai Ueyoshi, (日本語) Kota Ando, (日本語) Kazutoshi Hirose, Ryota Uematsu, Yuka Oba, Masayuki Ikebe, Tetsuya Asai, (日本語) Masato Motomura, Shinya Takamaeda-Yamazaki
IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip,International Conference,2018
BibTeX
BRein Memory: A Single-Chip Binary/Ternary Reconfigurable In-Memory Deep Neural Network Accelerator Achieving 1.4TOPS at 0.6W
(日本語) Kota Ando, Kodai Ueyoshi, Kentaro Orimo, Haruyoshi Yonekawa, Shimpei Sato, Hiroki Nakahara, Shinya Takamaeda-Yamazaki, Masayuki Ikebe, Tetsuya Asai, Tadahiro Kuroda, (日本語) Masato Motomura
IEEE Journal of Solid-State Circuits,Journal Papers,2018
BibTeX
Decomposed Vector Histograms of Oriented Gradients for Efficient Hardware Implementation
Koichi Mitsunari, Yoshinori Takeuchi, Masaharu Imai, (日本語) Jaehoon Yu
IEICE_J_FECACS,Journal Papers,2018
BibTeX
Dither NN: An Accurate Neural Network with Dithering for Low Bit-Precision Hardware
(日本語) Kota Ando, Kodai Ueyoshi, Yuka Oba, (日本語) Kazutoshi Hirose, Ryota Uematsu, Takumi Kudo, Masayuki Ikebe, Tetsuya Asai, Shinya Takamaeda-Yamazaki, (日本語) Masato Motomura
International Conference on Field-Programmable Technology (FPT),International Conference,2018
BibTeX
Exploring CNN Accelerator Design Space on a Dynamically Reconfigurable Hardware Platform
Ryota Uematsu, (日本語) Kota Ando, Kodai Ueyoshi, (日本語) Kazutoshi Hirose, Masayuki Ikebe, Tetsuya Asai, Shinya Takamaeda-Yamazaki, (日本語) Masato Motomura
Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI),International Conference,2018
BibTeX
Hardware Architecture for Fast General Object Detection Using Aggregated Channel Features
Koichi Mitsunari, (日本語) Jaehoon Yu, Masanori Hashimoto
International Conference,2018
BibTeX
Hardware Architecture for High-Speed Object Detection Using Decision Tree Ensemble
Koichi Mitsunari, (日本語) Jaehoon Yu, Takao Onoye, Masanori Hashimoto
IEICE_J_FECACS,Journal Papers,2018
BibTeX
Interconnect Delay Analysis for RRAM Crossbar Based FPGA
Masanori Hashimoto, Yuki Nakazawa, (日本語) Jaehoon Yu
IEEE Computer Society Annual Symposium on VLSI (ISVLSI),International Conference,2018
BibTeX
Interconnect Delay Analysis for RRAM Crossbar Based FPGA
Masanori Hashimoto, Yuki Nakazawa, Ryutaro Doi, (日本語) Jaehoon Yu
International Conference,2018
BibTeX
New Generation Dynamically Reconfigurable Processor Technology for Accelerating Embedded AI Applications
Taro Fujii, Takao Toi, Teruhito Tanaka, Katsumi Togawa, Toshiro Kitaoka, Kengo Nishino, Noritsugu Nakamura, Hiroki Nakahara, (日本語) Masato Motomura
Symposia on VLSI Technology and Circuits,International Conference,2018
BibTeX
Phase Locking Value Calculator based on Hardware-oriented Mathematical Expression
Tomoki Sugiura, (日本語) Jaehoon Yu, Yoshinori Takeuchi
Journal Papers,2018
BibTeX
Proto-Computing Architecture over A Digital Medium Aiming at Real-Time Video Processing
Aoi Tanibata, Alexandre Schmid, Shinya Takamaeda-Yamazaki, Masayuki Ikebe, (日本語) Masato Motomura, Tetsuya Asai
Complexity,Journal Papers,2018
BibTeX
Quantization Error-Based Regularization for Hardware-Aware Neural Network Training
(日本語) Kazutoshi Hirose, Ryota Uematsu, (日本語) Kota Ando, Kodai Ueyoshi, Masayuki Ikebe, Tetsuya Asai, (日本語) Masato Motomura, Shinya Takamaeda-Yamazaki
Nonlinear Theory and Its Applications,Journal Papers,2018
BibTeX
QUEST: A 7.49-TOPS Multi-Purpose Log-Quantized DNN Inference Engine Stacked on 96MB 3D SRAM using Inductive-Coupling Technology in 40nm CMOS
Kodai Ueyoshi, (日本語) Kota Ando, (日本語) Kazutoshi Hirose, Shinya Takamaeda-Yamazaki, Junichiro Kadomoto, Tomoki Miyata, Mototsugu Hamada, Tadahiro Kuroda, (日本語) Masato Motomura
International Solid-State Circuits Conference (ISSCC 2018),International Conference,2018
BibTeX
Real-time HDTV to 4K and 8K-UHD Conversions Using Anti-Aliasing Based Super Resolution Algorithm on FPGA
Prasoon Ambalathankandy, Shinya Takamaeda-Yamazaki, (日本語) Masato Motomura, Tetsuya Asai, Masayuki Ikebe, Hotaka Kusano
Microprocessors and Microsystems,Journal Papers,2018
BibTeX
Sneak Path Free Reconfiguration of Via-switch Crossbars Based FPGA
Ryutaro Doi, (日本語) Jaehoon Yu, Masanori Hashimoto
International Conference,2018
BibTeX
Sparse Disparity Estimation Using Global Phase Only Correlation for Stereo Matching Acceleration
Takeshi Shimada, Masayuki Ikebe, Prasoon Ambalathankandy, Shinya Takamaeda-Yamazaki, (日本語) Masato Motomura, Tetsuya Asai
IEEE International Conference on Acoustics, Speech and Signal Processing,International Conference,2018
BibTeX
Via-Switch FPGA: Highly Dense Mixed-Grained Reconfigurable Architecture with Overlay Via-Switch Crossbars
Hiroyuki Ochi, Kosei Yamaguchi, Tetsuaki Fujimoto, Junshi Hotate, Takashi Kishimoto, Toshiki Higashi, Takashi Imagawa, Ryutaro Doi, Munehiro Tada, Tadahiko Sugibayashi, Wataru Takahashi, Kazutoshi Wakabayashi, Hidetoshi Onodera, Yukio Mitsuyama, (日本語) Jaehoon Yu, Masanori Hashimoto
Journal Papers,2018
BibTeX
ビアスイッチ FPGA 再構成時のスニークパス問題を回避するプログラミング順決定手法
土井龍太郎, (日本語) Jaehoon Yu, 橋本昌宜, others
DA シンポジウム 2018 論文集,International Conference,2018
BibTeX
ビアスイッチ FPGA 向け配線解析手法の検討 (VLSI 設計技術)
中澤祐希, 土井龍太郎, (日本語) Jaehoon Yu, 橋本昌宜
電子情報通信学会技術研究報告= IEICE technical report: 信学技報,International Conference,2018
BibTeX

2017

[Invited] A Binary/Ternary Reconfigurable in-Memory Deep Neural Network Accelerator
(日本語) Masato Motomura
Workshop,2017
BibTeX
[Invited] Research Activity on Deep Neural Network Accelerators
(日本語) Masato Motomura
Workshop,2017
BibTeX
[Invited] Rise of Deep Neural Network Accelerators
(日本語) Masato Motomura
Workshop,2017
BibTeX
[Invited] Trends toward Reconfigurable and in-Memory Processing Architectures for Deep Neural Networks
(日本語) Masato Motomura
Workshop,2017
BibTeX
[Invited] Trends toward Reconfigurable and in-Memory Processing Architectures for Deep Neural Networks
(日本語) Masato Motomura
Workshop,2017
BibTeX
6-DoF Camera Position and Posture Estimation Based on Local Patches of Image Sequence
Takuto Tsuji, Masayuki Ikebe, Shinya Takamaeda-Yamazaki, (日本語) Masato Motomura, Tetsuya Asai
Journal of Signal Processing,Journal Papers,2017
BibTeX
6-DoF Camera-Position and Posture Estimation Based on Local Patches of Image Sequence
Takuto Tsuji, Masayuki Ikebe, Shinya Takamaeda-Yamazaki, (日本語) Masato Motomura, Tetsuya Asai
RISP International Workshop on Nonlinear Circuits, Communications and Signal Processing,International Conference,2017
BibTeX
A Batch Normalization Free Binarized Convolutional Deep Neural Network on an FPGA
Hiroki Nakahara, Haruyoshi Yonekawa, Hisashi Iwamoto, (日本語) Masato Motomura
International Symposium on Field-Programmable Gate Array (FPGA),International Conference,2017
BibTeX
A High Performance and Energy Efficient Microprocessor with a Novel Restricted Dynamically Reconfigurable Accelerator
Itaru Hida, Shinya Takamaeda-Yamazaki, Masayuki Ikebe, (日本語) Masato Motomura, Tetsuya Asai
Circuits and Systems,Journal Papers,2017
BibTeX
A Low-Energy Application Specific Instruction-Set Processor towards a Low-Computational Lossless Compression Method for Stimuli Position Data of Artificial Vision Systems
Tomoki Sugiura, Masaharu Imai, (日本語) Jaehoon Yu, Yoshinori Takeuchi
Journal Papers,2017
BibTeX
A Multithreaded CGRA for Convolutional Neural Network Processing
(日本語) Kota Ando, Shinya Takamaeda-Yamazaki, Masayuki Ikebe, Tetsuya Asai, (日本語) Masato Motomura
Circuits and Systems,Journal Papers,2017
BibTeX
A Regularization Approach for Quantized Neural Networks
(日本語) Kazutoshi Hirose, Ryota Uematsu, (日本語) Kota Ando, Kodai Ueyoshi, Masayuki Ikebe, Tetsuya Asai, (日本語) Masato Motomura, Shinya Takamaeda-Yamazaki
International Workshop on Highly Efficient Neural Networks Design (HENND),International Conference,2017
BibTeX
A Scalable Ising Model Implementation on An FPGA
Kasho Yamamoto, Shinya Takamaeda-Yamazaki, Masayuki Ikebe, Tetsuya Asai, (日本語) Masato Motomura
COOL Chips,International Conference,2017
BibTeX
A Time-Division Multiplexing Ising Machine on FPGAs
Kasho Yamamoto, Weiqiang Huang, Shinya Takamaeda-Yamazaki, Masayuki Ikebe, Tetsuya Asai, (日本語) Masato Motomura
International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies (HEART),International Conference,2017
BibTeX
A Versatile and Energy-Efficient Reconfigurable Accelerator for Embedded Microprocessors
Itaru Hida, Shinya Takamaeda-Yamazaki, Masayuki Ikebe, (日本語) Masato Motomura, Tetsuya Asai
GI-CoRE GSQ, GSB, & IGM Joint Symposium -Quantum, Informatics, Biology, & Medicine -,International Conference,2017
BibTeX
Accelerating Deep Learning by Binarized Hardware
Shinya Takamaeda-Yamazaki, Kodai Ueyoshi, (日本語) Kota Ando, Ryota Uematsu, (日本語) Kazutoshi Hirose, Masayuki Ikebe, Tetsuya Asai, (日本語) Masato Motomura
Asia-Pacific Signal and Information Processing Association Annual Summit and Conference (APSIPA ASC),International Conference,2017
BibTeX
An Energy-Efficient Dynamic Branch Predictor with a Two-Clock-Cycle Naive Bayes Classifier for Pipelined RISC Microprocessors
Itaru Hida, Shinya Takamaeda-Yamazaki, Masayuki Ikebe, (日本語) Masato Motomura, Tetsuya Asai
Nonlinear Theory and Its Applications,Journal Papers,2017
BibTeX
An FPGA Realization of a Deep Convolutional Neural Network Using A Threshold Neuron Pruning
Tomoya Fujii, Shimpei Sato, Hiroki Nakahara, (日本語) Masato Motomura
International Symposium on Applied Reconfigurable Computing (ARC),International Conference,2017
BibTeX
BRein Memory: A 13-Layer 4.2 K Neuron/0.8 M Synapse Binary/Ternary Reconfigurable In-Memory Deep Neural Network Accelerator in 65 nm CMOS
(日本語) Kota Ando, Kodai Ueyoshi, Kentaro Orimo, Haruyoshi Yonekawa, Shimpei Sato, Hiroki Nakahara, Masayuki Ikebe, Tetsuya Asai, Shinya Takamaeda-Yamazaki, Tadahiro Kuroda, (日本語) Masato Motomura
Symposia on VLSI Technology and Circuits,International Conference,2017
BibTeX
Deformable Part Model Based Arrhythmia Detection Using Time Domain Features
Yuuka Hirao, Yoshinori Takeuchi, Masaharu Imai, (日本語) Jaehoon Yu
IEICE_J_FECACS,Journal Papers,2017
BibTeX
Error Tolerance Analysis of Deep Learning Hardware Using Restricted Boltzmann Machine towards Low-Power Memory Implementation
Takao Marukame, Kodai Ueyoshi, Tetsuya Asai, (日本語) Masato Motomura, Alexandre Schmid, Masamichi Suzuki, Yusuke Higashi, Yuichiro Mitani
IEEE Transactions on Circuits and Systems II,Journal Papers,2017
BibTeX
Exploring Optimized Accelerator Design for Binarized Convolutional Neural Networks
Kodai Ueyoshi, (日本語) Kota Ando, Kentaro Orimo, Masayuki Ikebe, Tetsuya Asai, (日本語) Masato Motomura
International Joint Conference on Neural Networks,International Conference,2017
BibTeX
Fast and Cycle-Accurate Emulation of Large-Scale Networks-on-Chip Using a Single FPGA
(日本語) Thiem Van Chu, Shimpei Sato, Kenji Kise
ACM Transactions on Reconfigurable Technology and Systems (TRETS),Journal Papers,2017
BibTeX
Feature Extraction System Using Restricted Boltzmann Machines on FPGA
Kodai Ueyoshi, Takao Marukame, Tetsuya Asai, (日本語) Masato Motomura, Alexandre Schmid
IEEE International Symposium on Circuits & Systems,International Conference,2017
BibTeX
FPGA Implementation of Edge-Guided Pattern Generation for Motion-Vector Estimation of Textureless Objects (Demo Night)
Aoi Tanibata, Alexandre Schmid, Shinya Takamaeda-Yamazaki, Masayuki Ikebe, (日本語) Masato Motomura, Tetsuya Asai
International Conference on Field-Programmable Logic and Applications (FPL),International Conference,2017
BibTeX
Hardware Accelerator Design for Convolutional Neural Networks with Low Bit Precision
Kodai Ueyoshi, Masayuki Ikebe, Tetsuya Asai, Shinya Takamaeda-Yamazaki, (日本語) Masato Motomura
GI-CoRE GSQ, GSB, & IGM Joint Symposium - Quantum, Informatics, Biology, & Medicine -,International Conference,2017
BibTeX
Hardware-Oriented Algorithm for Phase Synchronization Analysis of Biomedical Signals
Tomoki Sugiura, (日本語) Jaehoon Yu, Yoshinori Takeuchi
IEEE_C_BCAS,International Conference,2017
BibTeX
High-Performance Hardware Merge Sorter
Susumu Mashimo, (日本語) Thiem Van Chu, Kenji Kise
IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM),International Conference,2017
BibTeX
In-Memory Area-Efficient Signal Streaming Processor Design for Binary Neural Networks
(日本語) Kota Ando, Kodai Ueyoshi, (日本語) Kazutoshi Hirose, Kentaro Orimo, Haruyoshi Yonekawa, Shimpei Sato, Hiroki Nakahara, Masayuki Ikebe, Shinya Takamaeda-Yamazaki, Tetsuya Asai, Tadahiro Kuroda, (日本語) Masato Motomura
IEEE International Midwest Symposium on Circuits and Systems (MWSCAS),International Conference,2017
BibTeX
Logarithmic Compression for Memory Footprint Reduction in Neural Network Training
(日本語) Kazutoshi Hirose, Ryota Uematsu, (日本語) Kota Ando, Kentaro Orimo, Kodai Ueyoshi, Masayuki Ikebe, Tetsuya Asai, Shinya Takamaeda-Yamazaki, (日本語) Masato Motomura
International Workshop on Computer Systems and Architectures (CSA),International Conference,2017
BibTeX
Low latency divider using ensemble of moving average curves
Yuhan Fu, Masayuki Ikebe, Takeshi Shimada, (日本語) Masato Motomura, Tetsuya Asai
International Symposium on Quality Electronic Design (ISQED),International Conference,2017
BibTeX
Quantization Error-based Regularization in Neural Networks
(日本語) Kazutoshi Hirose, (日本語) Kota Ando, Kodai Ueyoshi, Masayuki Ikebe, Tetsuya Asai, (日本語) Masato Motomura, Shinya Takamaeda-Yamazaki
SGAI International Conference on Artificial Intelligence (SGAI),International Conference,2017
BibTeX
Sign-Invariant Unsupervised Learning Facilitates Weighted-Sum Computation in Analog Neural-Network Devices
Itaru Hida, Kodai Ueyoshi, Shinya Takamaeda-Yamazaki, Masayuki Ikebe, (日本語) Masato Motomura, Tetsuya Asai
International Symposium on Nonlinear Theory and Its Applications,International Conference,2017
BibTeX
Throughput Analysis of A Data-Flow Reconfigurable Array Architecture for Convolutional Neural Networks
(日本語) Kota Ando, Kodai Ueyoshi, Kentaro Orimo, Masayuki Ikebe, Shinya Takamaeda-Yamazaki, Tetsuya Asai, (日本語) Masato Motomura
RIEC International Symposium on Brain Functions and Brain Computer,International Conference,2017
BibTeX
Time-Division Multiplexing
Kasho Yamamoto, Masayuki Ikebe, Tetsuya Asai, (日本語) Masato Motomura, Shinya Takamaeda-Yamazaki
GI-CoRE GSQ, GSB, & IGM Joint Symposium - Quantum, Informatics, Biology, & Medicine -,International Conference,2017
BibTeX

2016

[Invited] 3D Stacked Image Sensor Featuring Low Noise Inductive Coupling Channels
Masayuki Ikebe, Daisuke Uchida, Yasuhiro Take, Tetsuya Asai, Tadahiro Kuroda, (日本語) Masato Motomura
International Workshop on Image Sensors and Imaging Systems,International Conference,2016
BibTeX
[Invited] AI and SoC
(日本語) Masato Motomura
Workshop,2016
BibTeX
3D Stacked Imager Featuring Inductive Coupling Channels for High Speed/Low-Noise Image Transfer
Masayuki Ikebe, Daisuke Uchida, Yasuhiro Take, Makito Someya, Satoshi Chikuda, Kento Matsuyama, Tetsuya Asai, Tadahiro Kuroda, (日本語) Masato Motomura
ITE Transactions on Media Technology and Applications,Journal Papers,2016
BibTeX
A Hardware Cellular-Automaton Architecture for Spatial Pattern Generation towards Motion-Vector Estimation of Textureless Objects
Aoi Tanibata, Miho Ushida, Alexandre Schmid, Masayuki Ikebe, Tetsuya Asai, (日本語) Masato Motomura
International Symposium on Nonlinear Theory and its Applications,International Conference,2016
BibTeX
A Memory-Based Realization of A Binarized Deep Convolutional Neural Network
Hiroki Nakahara, Haruyoshi Yonekawa, Tsutomu Sasao, Hisashi Iwamoto, (日本語) Masato Motomura
International Conference on Field-Programmable Technology (FPT),International Conference,2016
BibTeX
A Programmable Controller for Spatio-Temporal Pattern Stimulation of Cortical Visual Prosthesis
Tomoki Sugiura, Arif Ullah Khan, (日本語) Jaehoon Yu, Yoshinori Takeuchi, Seiji Kameda, Takatsugu Kamata, Yuki Hayashida, Tetsuya Yagi, Masaharu Imai
IEEE_C_BCAS,International Conference,2016
BibTeX
A Two-Clock-Cycle Naive Bayes Classifier for Dynamic Branch Prediction in Pipelined RISC Microprocessors
Itaru Hida, Masayuki Ikebe, Tetsuya Asai, (日本語) Masato Motomura
IEEE Asia Pacific Conference on Circuits and Systems,International Conference,2016
BibTeX
An FPGA-Optimized Architecture of Anti-Aliasing Based Super Resolution for Real-time HDTV to 4K- and 8K-UHD Conversions
Hotaka Kusano, Masayuki Ikebe, Tetsuya Asai, (日本語) Masato Motomura
International Conference on Reconfigurable Computing and FPGAs,International Conference,2016
BibTeX
Arrhythmia Detection Using a Deformable Part Model and Time Domain Features
Yuuka Hirao, (日本語) Jaehoon Yu, Yoshinori Takeuchi, Masaharu Imai
International Conference,2016
BibTeX
Cognitive Motion Processing in Imager/Neural Processor 3D Stacked Systems
Tetsuya Asai, Masayuki Ikebe, (日本語) Masato Motomura
Workshop,2016
BibTeX
ECG の可変形状モデルに基づく不整脈検出アルゴリズム (スマートインフォメディアシステム)
平尾優香, (日本語) Jaehoon Yu, 武内良典, 今井正治
電子情報通信学会技術研究報告= IEICE technical report: 信学技報,International Conference,2016
BibTeX
FPGA Architecture for Feed-Forward Sequential Memory Network Targeting Long-Term Time-Series Forecasting
Kentaro Orimo, (日本語) Kota Ando, Kodai Ueyoshi, Masayuki Ikebe, Tetsuya Asai, (日本語) Masato Motomura
International Conference on Reconfigurable Computing and FPGAs,International Conference,2016
BibTeX
FPGA Implementation of A Scalable and Highly Parallel Architecture for Restricted Boltzmann Machines
Kodai Ueyoshi, Takao Marukame, Tetsuya Asai, (日本語) Masato Motomura, Alexandre Schmid
Circuits and Systems,Journal Papers,2016
BibTeX
FPGA-Based Stream Processing for Frequent Itemset Mining with Incremental Multiple Hashes
Kasho Yamamoto, Masayuki Ikebe, Tetsuya Asai, (日本語) Masato Motomura
Circuits and Systems,Journal Papers,2016
BibTeX
Hardware Architecture for Online Frequent Items Mining with Memory-Efficient Data Structure
Kasho Yamamoto, Tetsuya Asai, (日本語) Masato Motomura
COOL Chips XIX,International Conference,2016
BibTeX
Influence of Numerical Precision on Machine Learning and Embedded Systems
Koichi Mitsunari, (日本語) Jaehoon Yu
C_SISA,International Conference,2016
BibTeX
Memory-Error Tolerance of Scalable and Highly Parallel Architecture for Restricted Boltzmann Machines in Deep Belief Network
Kodai Ueyoshi, Takao Marukame, Tetsuya Asai, (日本語) Masato Motomura, Alexandre Schmid
IEEE International Symposium on Circuits and Systems,International Conference,2016
BibTeX
Motion Vector Estimation of Textureless Objects Exploiting Reaction-Diffusion Cellular Automata
Miho Ushida, Alexandre Schmid, Tetsuya Asai, Kazuyoshi Ishimura, (日本語) Masato Motomura
International Journal of Unconventional Computing,Journal Papers,2016
BibTeX
Motion-Vector Estimation and Cognitive Classification on An Image Sensor/Processor 3D Stacked System Featuring ThruChip Interfaces
Tetsuya Asai, Masafumi Mori, Toshiyuki Itou, Yasuhiro Take, Masayuki Ikebe, Tadahiro Kuroda, (日本語) Masato Motomura
European Solid-State Circuits Conference,International Conference,2016
BibTeX
Object Tracking based on Path Similarity of Boosted Decision Trees
Koichi Mitsunari, (日本語) Jaehoon Yu, Yoshinori Takeuchi, Masaharu Imai
International Conference,2016
BibTeX
Proposal of An Efficient Clock-Gating Mechanism for Multi-Core Processors to Reduce Power Supply Noise
Jun Kawabe, Yoshinori Takeuchi, (日本語) Jaehoon Yu, Masaharu Imai
Workshop on Synthesis And System Integration of Mixed Information technologies,International Conference,2016
BibTeX
Reconfigurable Processor Array Architecture for Deep Convolutional Neural Networks
(日本語) Kota Ando, Kentaro Orimo, Kodai Ueyoshi, Masayuki Ikebe, Tetsuya Asai, (日本語) Masato Motomura
Workshop on Synthesis And System Integration of Mixed Information Technologies,International Conference,2016
BibTeX
Reconfigurable Processor Array Architecture for Deep Convolutional Neural Networks
(日本語) Kota Ando, Kentaro Orimo, Kodai Ueyoshi, Masayuki Ikebe, Tetsuya Asai, (日本語) Masato Motomura
Workshop on Synthesis And System Integration of Mixed Information Technologies,International Conference,2016
BibTeX
Robustness of Hardware-Oriented Restricted Boltzmann Machines in Deep Belief Networks for Reliable Processing
Kodai Ueyoshi, Takao Marukame, Tetsuya Asai, (日本語) Masato Motomura, Alexandre Schmid
Nonlinear Theory and Its Applications,Journal Papers,2016
BibTeX
Stochastic Resonance Induced by Internal Noise in A Unidirectional Network of Excitable FitzHugh-Nagumo Neurons
Kazuyoshi Ishimura, Alexandre Schmid, Tetsuya Asai, (日本語) Masato Motomura
Nonlinear Theory and Its Applications,Journal Papers,2016
BibTeX
System Design of Vision-based Framework for Senior Driver Assistance
Eric Aliwarga, Koichi Mitsunari, (日本語) Jaehoon Yu, Takao Onoye, Toshitaka Azuma, Mitsuhiko Koga
Workshop on Synthesis And System Integration of Mixed Information technologies,International Conference,2016
BibTeX
The Synchronous vs. Asynchronous NoC Routers: An Apple-to-Apple Comparison between Synchronous and Transition Signaling Asynchronous Designs
Masashi Imai, (日本語) Thiem Van Chu, Kenji Kise, Tomohiro Yoneda
IEEE/ACM International Symposium on Networks-on-Chip (NOCS),International Conference,2016
BibTeX
Vision-based Comprehensive Framework for Senior Driver Assistance
Mitsuhiko Koga, Takao Onoye, (日本語) Jaehoon Yu, Toshitaka Azuma, Eric Aliwarga
ERTICO,International Conference,2016
BibTeX
心疾患発症を検出するための就寝時心電計測システムの提案
武内良典, (日本語) Jaehoon Yu, 今井正治, others
研究報告システム・アーキテクチャ (ARC),International Conference,2016
BibTeX
電源ノイズ削減のためのマルチコアプロセッサ向けクロックゲーティング機構の提案
川部純, 武内良典, (日本語) Jaehoon Yu, 今井正治, others
DA シンポジウム 2016 論文集,International Conference,2016
BibTeX

2015

A Low-Energy ASIP with Flexible Exponential Golomb Codec for Lossless Data Compression toward Artificial Vision Systems
Tomoki Sugiura, (日本語) Jaehoon Yu, Yoshinori Takeuchi, Masaharu Imai
International Conference,2015
BibTeX
A New Architecture for Feature Extraction to Perform Machine Learning by Using Motion Vectors and Its Implementation in An FPGA
Toshiyuki Itou, Masafumi Mori, Masayuki Ikebe, Tetsuya Asai, Tadahiro Kuroda, (日本語) Masato Motomura
RISP International Workshop on Nonlinear Circuits, Communications and Signal Processing,International Conference,2015
BibTeX
A Reaction-Diffusion Algorithm for Texture Generation towards Motion-Vector Estimation of Textureless-Objects
Miho Ushida, Kazuyoshi Ishimura, Tetsuya Asai, (日本語) Masato Motomura
RISP International Workshop on Nonlinear Circuits, Communications and Signal Processing,International Conference,2015
BibTeX
An Accelerator for Frequent Itemset Mining from Data Stream with Parallel Item Tree
Kasho Yamamoto, Eric S Fukuda, Tetsuya Asai, (日本語) Masato Motomura
Workshop on Synthesis And System Integration of Mixed Information Technologies,International Conference,2015
BibTeX
Crosstalk Rejection in 3D-Stacked Inter-Chip Communication with Blind Source Separation
Kamal El-Sankary, Tetsuya Asai, Tadahiro Kuroda, (日本語) Masato Motomura
IEEE Transactions on Circuits and Systems II,Journal Papers,2015
BibTeX
Design of Generic Hardware for Soft Cascade-Based Linear SVM Classification
Eric Aliwarga, (日本語) Jaehoon Yu, Masahide Hatanaka, Takao Onoye
International Conference,2015
BibTeX
Enhancing Memcached by Caching its Data and Functionalities at Network Interface
Eric S Fukuda, Hiroaki Inoue, Takashi Takenaka, Dahoo Kim, Tsunaki Sadahisa, Tetsuya Asai, (日本語) Masato Motomura
IPSJ Journal,Journal Papers,2015
BibTeX
FPGA Implementation of Hardware-Oriented Reaction-Diffusion Cellular Automata Models
Kazuyoshi Ishimura, Katsuro Komuro, Alexandre Schmid, Tetsuya Asai, (日本語) Masato Motomura
Nonlinear Theory and Its Applications,Journal Papers,2015
BibTeX
Image Sensor/Digital Logic 3D Stacked Module Featuring Inductive Coupling Channels for High Speed/Low-Noise Image Transfer
Masayuki Ikebe, Daisuke Uchida, Yasuhiro Take, Makito Someya, Satoshi Chikuda, Kento Matsuyama, Tetsuya Asai, Tadahiro Kuroda, (日本語) Masato Motomura
Symposia on VLSI Technology and Circuits,International Conference,2015
BibTeX
Motion Vector Estimation of Textureless Objects Exploiting Reaction-Diffusion Cellular Automata
Miho Ushida, Kazuyoshi Ishimura, Alexandre Schmid, Tetsuya Asai, (日本語) Masato Motomura
International Symposium on Nonlinear Theory and its Applications,International Conference,2015
BibTeX
Scalable and Highly-Parallel Architecture for Restricted Boltzmann Machines
Kodai Ueyoshi, Tetsuya Asai, (日本語) Masato Motomura
RISP International Workshop on Nonlinear Circuits, Communications and Signal Processing,International Conference,2015
BibTeX
Through Chip Interface Based Three-Dimensional FPGA Architecture Exploration
Li-Chung Hsu, (日本語) Masato Motomura, Yasuhiro Take, Tadahiro Kuroda
IEICE Transactions on Electronics,Journal Papers,2015
BibTeX
就寝時心電取得のための無意識生体電位計測システムの提案
武内良典, (日本語) Jaehoon Yu, 山中達哉, 関根正樹, 今井正治, others
研究報告組込みシステム (EMB),International Conference,2015
BibTeX

2014

A 4.5 to 13 Times Energy-Efficient Embedded Microprocessor with Mainly-Static/Partially-Dynamic Reconfigurable Array Accelerator
Itaru Hida, Dahoo Kim, Tetsuya Asai, (日本語) Masato Motomura
Asian Solid-State Circuits Conference,International Conference,2014
BibTeX
A Study of Transparent On-Chip Instruction Cache for NV Microcontrollers
Dahoo Kim, Itaru Hida, Eric S Fukuda, Tetsuya Asai, (日本語) Masato Motomura
International Conference on Advances in Circuits, Electronics and Micro-electronics,International Conference,2014
BibTeX
Achieving Higher Performance of Memcached by Caching at Network Interface
Eric S Fukuda, Hiroaki Inoue, Takashi Takenaka, Dahoo Kim, Tsunaki Sadahisa, Tetsuya Asai, (日本語) Masato Motomura
International Conference on Field Programmable Technology (FPT),International Conference,2014
BibTeX
An Efficient Data Compression Method for Artificial Vision Systems and Its Low Energy Implementation Using ASIP Technology
Tomoki Sugiura, Shoko Nakatsuka, (日本語) Jaehoon Yu, Yoshinori Takeuchi, Masaharu Imai
IEEE_C_BCAS,International Conference,2014
BibTeX
Application of Nonlinear Systems for Designing Low-Power Logic Gates Based on Stochastic Resonance
Gonzalez-Carabarin Lizeth, Tetsuya Asai, (日本語) Masato Motomura
Nonlinear Theory and Its Applications,Journal Papers,2014
BibTeX
Caching Memcached at Reconfigurable Network Interface
Eric S Fukuda, Hiroaki Inoue, Takashi Takenaka, Dahoo Kim, Tsunaki Sadahisa, Tetsuya Asai, (日本語) Masato Motomura
International Conference on Field Programmable Logic and Applications (FPL),International Conference,2014
BibTeX
Dual-Rail Asynchronous Pipeline Based on Stochastic Resonance Logic Gates
Gonzalez-Carabarin Lizeth, Tetsuya Asai, (日本語) Masato Motomura
International Symposium on Nonlinear Theory and its Applications,International Conference,2014
BibTeX
FPGA Implementation of A Memory-Efficient Stereo Vision Algorithm Based on 1-D Guided Filtering
Yuki Sanada, Katsuki Ohata, Tetsuro Ogaki, Kento Matsuyama, Takanori Ohira, Satoshi Chikuda, Masaki Igarashi, Tadahiro Kuroda, Masayuki Ikebe, Tetsuya Asai, (日本語) Masato Motomura
International Conference on Circuits, Systems, and Control,International Conference,2014
BibTeX
FPGA-Based Design for Motion-Vector Estimation Exploiting High-Speed Imaging and Its Application to Machine Learning
Masafumi Mori, Toshiyuki Itou, Masayuki Ikebe, Tetsuya Asai, Tadahiro Kuroda, (日本語) Masato Motomura
RISP International Workshop on Nonlinear Circuits, Communications and Signal Processing,International Conference,2014
BibTeX
FPGA-Based Design for Motion-Vector Estimation Exploiting High-Speed Imaging and Its Application to Motion Classification with Neural Networks
Masafumi Mori, Toshiyuki Itou, Masayuki Ikebe, Tetsuya Asai, Tadahiro Kuroda, (日本語) Masato Motomura
Journal of Signal Processing,Journal Papers,2014
BibTeX
Hardware Architecture for Accelerating Key-Value Retrieval Implemented on FPGA
Dahoo Kim, Eric S Fukuda, Tsunaki Sadahisa, Tetsuya Asai, (日本語) Masato Motomura
Japan-Korea Joint Workshop on Complex Communication Sciences,International Conference,2014
BibTeX
Image Steganography Based on Reaction Diffusion Models toward Hardware Implementation
Kazuyoshi Ishimura, Katsuro Komuro, Alexandre Schmid, Tetsuya Asai, (日本語) Masato Motomura
Nonlinear Theory and Its Applications,Journal Papers,2014
BibTeX
Low-Power Asynchronous Digital Pipeline Based on Mismatch-Tolerant Logic Gates
Gonzalez-Carabarin Lizeth, Tetsuya Asai, (日本語) Masato Motomura
IEICE Electronics Express,Journal Papers,2014
BibTeX
Normalized Channel Features for Accurate Pedestrian Detection
Ryusuke Miyamoto, (日本語) Jaehoon Yu, Takao Onoye
International Symposium on Communications, Control and Signal Processing,International Conference,2014
BibTeX
Reducing Power and Energy Consumption of Nonvolatile Microcontrollers with Transparent On-Chip Instruction Cache
Dahoo Kim, Itaru Hida, Eric S Fukuda, Tetsuya Asai, (日本語) Masato Motomura
Circuits and Systems,Journal Papers,2014
BibTeX
Stochastic Resonance in A Unidirectional Network of Nonlinear Oscillators Driven by Internal Noise
Kazuyoshi Ishimura, Katsuro Komuro, Alexandre Schmid, Tetsuya Asai, (日本語) Masato Motomura
International Symposium on Nonlinear Theory and its Applications,International Conference,2014
BibTeX
コンパイラ生成のための ASIP 必要命令セット判定手法
由井暁大, (日本語) Jaehoon Yu, 武内良典, 今井正治, others
DA シンポジウム 論文集,International Conference,2014
BibTeX
ソフトカスケードを用いた SVM 識別器の専用ハードウェア実装 (スマートインフォメディアシステム)
竹内一貴, (日本語) Jaehoon Yu, 宮本龍介, 尾上孝雄
電子情報通信学会技術研究報告= IEICE technical report: 信学技報,International Conference,2014
BibTeX
回転変化に対する耐性を持つ画像認識のための特徴抽出手法 (スマートインフォメディアシステム)
岩崎裕也, (日本語) Jaehoon Yu, 宮本龍介, 尾上孝雄
電子情報通信学会技術研究報告= IEICE technical report: 信学技報,International Conference,2014
BibTeX
圧縮センシングに基づく超解像処理の高速化 (信号処理)
山下智博, (日本語) Jaehoon Yu, 武内良典, 今井正治
電子情報通信学会技術研究報告= IEICE technical report: 信学技報,International Conference,2014
BibTeX

2013

A Restricted Dynamically Reconfigurable Architecture for Low Power Processors
Takeshi Hirao, Dahoo Kim, Itaru Hida, Tetsuya Asai, (日本語) Masato Motomura
International Conference on ReConFigurable Computing and FPGAs,International Conference,2013
BibTeX
A Restricted Dynamically Reconfigurable Architecture for Low Power Processors
Takeshi Hirao, Dahoo Kim, Itaru Hida, Tetsuya Asai, (日本語) Masato Motomura
Workshop on Synthesis And System Integration of Mixed Information Technologies,International Conference,2013
BibTeX
A Speed-Up Scheme Based on Multiple-Instance Pruning for Pedestrian Detection Using A Support Vector Machine
(日本語) Jaehoon Yu, Ryusuke Miyamoto, Takao Onoye
Journal Papers,2013
BibTeX
Asynchronous Digital Circuit Design Using Noise-Driven Stochastic Gates
Gonzalez-Carabarin Lizeth, Tetsuya Asai, (日本語) Masato Motomura
International Symposium on Nonlinear Theory and its Applications,International Conference,2013
BibTeX
C-Based Adaptive Stream Processing on Dynamically Reconfigurable Hardware: Window Join Case Study
Eric S Fukuda, Hideyuki Kawashima, Hiroaki Inoue, Taro Fujii, Koichiro Furuta, Tetsuya Asai, (日本語) Masato Motomura
International Symposium on Applied Reconfigurable Computing (ARC),International Conference,2013
BibTeX
C-Based Complex Event Processing on Reconfigurable Hardware
Hiroaki Inoue, Takashi Takenaka, (日本語) Masato Motomura
IEEE Transactions on Very Large Scale Integration Systems,Journal Papers,2013
BibTeX
C-Based Design of Window Join for Dynamically Reconfigurable Hardware
Eric S Fukuda, Hideyuki Kawashima, Hiroaki Inoue, Tetsuya Asai, (日本語) Masato Motomura
Journal of Computer Science and Engineering,Journal Papers,2013
BibTeX
Chaotic Resonance in Forced Chua’s Oscillators
Kazuyoshi Ishimura, Tetsuya Asai, (日本語) Masato Motomura
Journal of Signal Processing,Journal Papers,2013
BibTeX
CoHOG 特徴を用いた歩行者検出の確率的サンプリングに基づく高速化
(日本語) Jaehoon Yu, 宮本龍介, 尾上孝雄
画像電子学会誌,Journal Papers,2013
BibTeX
Exploiting Hardware Reconfigurability on Window Join
Eric S Fukuda, Hideyuki Kawashima, Hiroaki Inoue, Tetsuya Asai, (日本語) Masato Motomura
International Conference on High Performance Computing & Simulation,International Conference,2013
BibTeX
FPGA Implementation of 60-FPS QVGA-to-VGA Single-Image Super Resolution
Satoshi Chikuda, Takanori Ohira, Yuki Sanada, Masaki Igarashi, Masayuki Ikebe, Tetsuya Asai, (日本語) Masato Motomura
International Conference on Solid State Devices and Materials,International Conference,2013
BibTeX
FPGA Implementation of Single-Image Super Resolution Based on Frame-Bufferless Box Filtering
Yuki Sanada, Takanori Ohira, Satoshi Chikuda, Masaki Igarashi, Masayuki Ikebe, Tetsuya Asai, (日本語) Masato Motomura
Journal of Signal Processing,Journal Papers,2013
BibTeX
FPGA Implementation of Single-Image Super Resolution Based on Frame-Bufferless Box Filtering
Yuki Sanada, Takanori Ohira, Satoshi Chikuda, Masaki Igarashi, Masayuki Ikebe, Tetsuya Asai, (日本語) Masato Motomura
RISP International Workshop on Nonlinear Circuits, Communications and Signal Processing,International Conference,2013
BibTeX
Hardware-Oriented Stereo Vision Algorithm Based on 1-D Guided Filtering and Its FPGA Implementation
Katsuki Ohata, Yuki Sanada, Tetsuro Ogaki, Kento Matsuyama, Takanori Ohira, Satoshi Chikuda, Masaki Igarashi, Masayuki Ikebe, Tetsuya Asai, (日本語) Masato Motomura, Tadahiro Kuroda
IEEE International Conference on Electronics, Circuits, and Systems,International Conference,2013
BibTeX
High Level Synthesis with Stream Query to C Parser: Eliminating Hardware Development Difficulties for Software Developers
Eric S Fukuda, Takashi Takenaka, Hiroaki Inoue, Hideyuki Kawashima, Tetsuya Asai, (日本語) Masato Motomura
Workshop on Synthesis And System Integration of Mixed Information Technologies,International Conference,2013
BibTeX
Image steganography based on hardware-oriented reaction-diffusion models
Kazuyoshi Ishimura, Alexandre Schmid, Tetsuya Asai, (日本語) Masato Motomura
International Symposium on Nonlinear Theory and its Applications,International Conference,2013
BibTeX
Image Steganography on Digital Reaction-Diffusion Processor
Kazuyoshi Ishimura, Alexandre Schmid, Tetsuya Asai, (日本語) Masato Motomura
Nonlinear Dynamics of Electronic Systems,International Conference,2013
BibTeX
Towards Asynchronous Digital Circuit Design Based on Stochastic Resonance
Gonzalez-Carabarin Lizeth, Tetsuya Asai, (日本語) Masato Motomura
International Conference on Nanoenergy,International Conference,2013
BibTeX
狭帯域ボディエリアネットワーク向け命令セットプロセッサの提案
百谷和幸, (日本語) Jaehoon Yu, 武内良典, 今井正治
IEEE COMS 関西チャプタ 学生研究発表会,International Conference,2013
BibTeX

2012

A Memristor-Based Synaptic Device Having an Asymmetric STDP Time Window
Taku Adachi, Tetsuya Asai, (日本語) Masato Motomura
RISP International Workshop on Nonlinear Circuits, Communications and Signal Processing,International Conference,2012
BibTeX
Chaotic Resonance in Forced Chua’s Oscillator
Kazuyoshi Ishimura, Tetsuya Asai, (日本語) Masato Motomura
RISP International Workshop on Nonlinear Circuits, Communications and Signal Processing,International Conference,2012
BibTeX
Excitable Reaction-Diffusion Media with Memristors
Xiyuan Gong, Tetsuya Asai, (日本語) Masato Motomura
Journal of Signal Processing,Journal Papers,2012
BibTeX
Excitable Reaction-Diffusion Media with Memristors
Xiyuan Gong, Tetsuya Asai, (日本語) Masato Motomura
RISP International Workshop on Nonlinear Circuits, Communications and Signal Processing,International Conference,2012
BibTeX
Impact of Noise on Spike Transmission through Serially-Connected Electrical FitzHugh-Nagumo Circuits with Subthreshold and Suprathreshold Interconductances
Gonzalez-Carabarin Lizeth, Tetsuya Asai, (日本語) Masato Motomura
Journal of Signal Processing,Journal Papers,2012
BibTeX
Noise Impact on Spike Transmission through Serially-Connected Electrical FitzHugh-Nagumo Model with Subthreshold and Suprathreshold Interconductances
Gonzalez-Carabarin Lizeth, Tetsuya Asai, (日本語) Masato Motomura
International Conference On Cognitive and Neural Systems,International Conference,2012
BibTeX
Noise-Assisted Spike Transmission on An Array of Electrical FitzHugh-Nagumo Models
Gonzalez-Carabarin Lizeth, Tetsuya Asai, (日本語) Masato Motomura
RISP International Workshop on Nonlinear Circuits, Communications and Signal Processing,International Conference,2012
BibTeX
Noise-Induced Phase Synchronization among Simple Digital Counters
Masakazu Matsuura, Tetsuya Asai, (日本語) Masato Motomura
Journal of Signal Processing,Journal Papers,2012
BibTeX
Noise-Induced Phase Synchronization in Digital Counters
Masakazu Matsuura, Tetsuya Asai, (日本語) Masato Motomura
RISP International Workshop on Nonlinear Circuits, Communications and Signal Processing,International Conference,2012
BibTeX
Pedestrian Localization Using CoHOG-based Detection and HSV-based Tracking
(日本語) Jaehoon Yu, Ryusuke Miyamoto, Takao Onoye, Hiroki Sugano, Yukihiro Nakamura
C_ITC-CSCC,International Conference,2012
BibTeX
Reaction-Diffusion Media with Excitable Oregonators Coupled by Memristors
Xiyuan Gong, Tetsuya Asai, (日本語) Masato Motomura
International Workshop on Cellular Nanoscale Networks and their Applications (Memristor and Memristive Symposium),International Conference,2012
BibTeX
Spatio-Temporal Pattern Formation on Memristive Reaction-Diffusion Systems
Xiyuan Gong, Tetsuya Asai, (日本語) Masato Motomura
Asia Conference on Nanoscience and Nanotechnology,International Conference,2012
BibTeX
Spike Propagation in Excitable Systems Enhanced by Membrane-Potential-Dependent Noise
Gonzalez-Carabarin Lizeth, Tetsuya Asai, (日本語) Masato Motomura
International Symposium on Nonlinear Theory and its Applications,International Conference,2012
BibTeX
Spike Transmission in Locally Coupled Excitable Circuits Enhanced by Membrane-Potential-Dependent Noise
Gonzalez-Carabarin Lizeth, Tetsuya Asai, (日本語) Masato Motomura
Asia Conference on Nanoscience and Nanotechnology 2012,International Conference,2012
BibTeX
メトロポリス・ヘイスティングス法を用いた物体検出手法の並列化検討
(日本語) Jaehoon Yu, 宮本龍介, 尾上孝雄
電子情報通信学会技術研究報告. SIS, スマートインフォメディアシステム,International Conference,2012
BibTeX

2011

20Gbps C-Based Complex Event Processing
Hiroaki Inoue, Takashi Takenaka, (日本語) Masato Motomura
International Conference on Field Programmable Logic and Applications (FPL),International Conference,2011
BibTeX
A Subthreshold Memory Cell Utilizing Nonlinear Characteristics of Positive-Feedback Operational Transconductance Amplifier
Kazunori Yoshida, Tetsuya Asai, (日本語) Masato Motomura
Kyoto Workshop on NOLTA,International Conference,2011
BibTeX
Test Compression for Dynamically Reconfigurable Processors
Hiroaki Inoue, Junya Yamada, Hideyuki Yoneda, Katsumi Togawa, (日本語) Masato Motomura, Koichiro Furuta
ACM Transactions on Reconfigurable Technology and Systems (TRETS),Journal Papers,2011
BibTeX
Time and Space-Multiplexed Compilation Challenge for Dynamically Reconfigurable Processors
Takao Toi, Toru Awashima, (日本語) Masato Motomura, Hideharu Amano
IEEE International Midwest Symposium on Circuits and Systems (MWSCAS),International Conference,2011
BibTeX
多重領域分割に基づく複数の手掛りを用いた画像構造識別手法
(日本語) Jaehoon Yu, 宮本龍介, 尾上孝雄
電子情報通信学会技術研究報告. SIS, スマートインフォメディアシステム,International Conference,2011
BibTeX

2010

AS-2-4 階層探索による Full HD 対応 H. 264 小面積動き検出回路の開発 (AS-2. ディジタル信号処理システムの実装技術, シンポジウムセッション)
渡邊賢治, 平井直行, 今川隆司, (日本語) Jaehoon Yu, 橋本亮司, 藤田玄
電子情報通信学会総合大会講演論文集,International Conference,2010
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Computationally Efficient Pedestrian Detection Based on Markov Chain Monte Carlo
(日本語) Jaehoon Yu, Hiroki Sugano, Ryusuke Miyamoto, Takao Onoye
APSIPA Annual Summit and Conference,International Conference,2010
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GPU Implementation of Efficient Pedestrian Detection Based on MCMC
(日本語) Jaehoon Yu, Hiroki Sugano, Ryusuke Miyamoto, Takao Onoye
Joint International Conference on Soft Computing and Intelligent Systems and International Symposium on Advanced Intelligent Systems,International Conference,2010
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MCMC を用いた効率的な歩行者認識に関する研究
(日本語) Jaehoon Yu, 菅野裕揮, 宮本龍介, 尾上孝雄
電子情報通信学会技術研究報告. SIS, スマートインフォメディアシステム,International Conference,2010
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2009

STP Engine, a C-based Programmable HW Core featuring Massively Parallel and Reconfigurable PE Array: Its Architecture, Tool, and System Implications
(日本語) Masato Motomura
IEEE Symposium on Low-Power and High-Speed Chips (Cool Chips),International Conference,2009
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2007

Implementation of AV Streaming System Using Peer-to-Peer Communication
Norihiro Ishikawa, Hiroshi Tsutsui, (日本語) Jaehoon Yu, Tomonori Izumi, Hiroyuki Ochi, Yukihiro Nakamura, Takaaki Komura, Yoshitaka Uchida
IEEE Consumer Communications and Networking Conference,International Conference,2007
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可変ウィンドウ手法に基づく高精度ステレオマッチングプロセッサ
宮本龍介, (日本語) Jaehoon Yu, 筒井弘, 中村行宏
画像電子学会誌,Journal Papers,2007
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2006

可変ウィンドウステレオマッチングプロセッサのアーキテクチャ (映像信号処理)
宮本龍介, (日本語) Jaehoon Yu, 筒井弘
回路とシステム軽井沢ワークショップ論文集,International Conference,2006
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2005

Implementation of AV Control System Over Universal P2P Network
Tomonori Izumi, (日本語) Jaehoon Yu, Tetsuya Kimata, Hiroyuki Ochi, Yukihiro Nakamura
International Conference on Computing, Communications and Control Technologies,International Conference,2005
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情報家電ネットワークと携帯端末ネットワークをつなぐ P2P 動画配信システムの構築
(日本語) Jaehoon Yu, 木全哲也, 越智直紀, 泉知論, 越智裕之, 中村行宏, 小俣栄治, 石川憲洋, others
情報処理学会研究報告モバイルコンピューティングとユビキタス通信 (MBL),International Conference,2005
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2002

A Dynamically Reconfigurable Processor Architecture
(日本語) Masato Motomura
Microprocessor Forum (MPF),International Conference,2002
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New NEC Array Speeds Data NEC Introduces Its Dynamically Reconfigurable 512-Processor Array
Microprocessor Report
Books,2002
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