2005年京都大学電気電子工学科学士,2007年同大学情報学修士,2013年大阪大学情報科学博士.2013年より大阪大学情報科学研究科助教.2019年10月より東京工業大学科学技術創成研究院准教授.IEEE/IEICE/IPSJ に所属.

Work Experience

  • 2019.10 — Present
    Tokyo Institute of Technology / Associate Professor
  • 2013.06 — 2019.09
    Osaka University / Assistant Professor
  • 2013.04 — 2013.05
    RayTron, INC. / Contract Employee (RTL Designer)
  • 2009.12 — 2010.03
    Synthesis Corporation / Contract Employee (RTL Designer)
  • 2005.04 — 2007.03
    Synthesis Corporation / Contract Employee (RTL Designer)

Education

  • 2010.04 — 2013.03
    Graduate School of Information Science and Technology / Osaka University / Doctor of Informatics
  • 2009.10 — 2010.03
    Graduate School of Informatics / Kyoto University / Research Student
  • 2005.04 — 2007.03
    Graduate School of Informatics / Kyoto University / Master of Informatics
  • 2001.04 — 2005.03
    Undergraduate School of Electrical and Electronic Engineering / Kyoto University / Bachelor of Engineering
  • 2000.10 — 2001.03
    Osaka University of Foreign Studies / Japanese Language Course
  • 2000.03 — 2001.08
    Institute of International Education / Kyung Hee University / Japanese Language Course
  • 1997.03 — 2000.02
    Myung-Duk Foreign High School, Republic of Korea

Scholarships

  • 2010.04 — 2013.03
    Japan Society for the Promotion of Science / Research Fellowship for Young Scientists (DC1)
  • 2005.04 — 2007.03
    KDDI Foundation International Communication Fund / Scholarship Student
  • 2000.03 — 2005.03
    Japan-Korea Joint Program for Science & Engineering Students / Scholarship Student

Transactions (International)

  1. J. Suzuki, T. Kaneko, K. Ando, K. Hirose, K. Kawamura, T. V. Chu, M. Motomura, and J. Yu, “ProgressiveNN: Achieving computational scalability with dynamic bit-precision adjustment by MSB-first accumulative computation,” International Journal of Networking and Computing, 2021 (accepted).
  2. S. Kumazawa, K. Kawamura, T. V. Chu, M. Motomura, and J. Yu, “ExtraFerns: Fully parallel ensemble learning technique with random projection and non-greedy yet minimal memory access training,” International Journal of Networking and Computing, 2021 (accepted).
  3. K. Hirose, S. Takamaeda-Yamazaki, J. Yu, M. Motomura, “Selective fine-tuning on a classifier ensemble: Realizing adaptive neural networks with a diversified multi-exit architecture,” IEEE Access, vol. 9, pp. 6179 – 6187, 2021.
  4. T. Cheng, Y. Masuda, and J. Chen, J. Yu, and H. Masanori, “Logarithm-approximate floating-point multiplier is applicable to power-efficient neural network training,” Integration, vol. 74, pp. 19 – 31, 2020.
  5. R. Doi, J. Yu, M. Hashimoto, “Sneak path free reconfiguration with minimized programming steps for via-switch crossbar based FPGA,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 39, no. 10, pp. 2572 – 2587, Oct. 2020.
  6. S. Sombatsiri, S. Shibata, Y. Kobayashi, H. Inoue, T. Takenaka, T. Hosomi, J. Yu, and Y. Takeuchi, “Parallelism-flexible convolution core for sparse convolutional neural networks on FPGA,” IPSJ Transactions on System LSI Design Methodology, vol. 12, pp. 22 – 37, 2019.
  7. K. Mitsunari, Y. Takeuchi, M. Imai, and J. Yu, “Decomposed vector histograms of oriented gradients for efficient hardware implementation,” IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, vol. 101, no. 11, pp. 1766 – 1775, 2018.
  8. K. Mitsunari, J. Yu, T. Onoye, and M. Hashimoto, “Hardware architecture for high-speed object detection using decision tree ensemble,” IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, vol. 101, no. 9, pp. 1298 – 1307, 2018.
  9. H. Ochi, K. Yamaguchi, T. Fujimoto, J. Hotate, T. Kishimoto, T. Higashi, T. Imagawa, R. Doi, M. Tada, T. Sugibayashi, W. Takahashi, K. Wakabayashi, H. Onodera, Y. Mitsuyama, J. Yu, and M. Hashimoto, “Via-switch FPGA: Highly dense mixed-grained reconfigurable architecture with overlay via-switch crossbars,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, no. 99, pp. 1 – 14, 2018.
  10. T. Sugiura, J. Yu, and Y. Takeuchi, “Phase locking value calculator based on hardware-oriented mathematical expression,” IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, vol. 101, no. 12, pp. 2254 – 2261, 2018.
  11. T. Sugiura, M. Imai, J. Yu, and Y. Takeuchi, “A low-energy application specific instruction-set processor towards a low-computational lossless compression method for stimuli position data of artificial vision systems,” Journal of Information Processing, vol. 25, pp. 210 – 219, 2017.
  12. Y. Hirao, Y. Takeuchi, M. Imai, and J. Yu, “Deformable part model based arrhythmia detection using time domain features,” IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, vol. 100, no. 11, pp. 2221 – 2229, 2017.
  13. J. Yu, R. Miyamoto, and T. Onoye, “A speed-up scheme based on multiple-instance pruning for pedestrian detection using a support vector machine,” IEEE Transactions on Image Processing, vol. 22, no. 12, pp. 4752 – 4761, 2013.

 

Transactions (Domestic)

  1. 劉載勲, 宮本龍介, and 尾上孝雄, “CoHOG 特徴を用いた歩行者検出の確率的サンプリングに基づく高速化,” 画像電子学会誌, vol. 42, no. 1, pp. 30 – 40, 2013
  2. 宮本龍介, 劉載勲, 筒井弘, and 中村行宏, “可変ウィンドウ手法に基づく高精度ステレオマッチングプロセッサ,” 画像電子学会誌, vol. 36, no. 3, pp. 210 – 218, 2007

 

Conference Papers (International)

  1. K. Ando, J. Yu, K. Hirose, H. Nakahara, K. Kawamura, T. V. Chu, and M. Motomura, “Edge Inference Enginefor Deep & Random Sparse Neural Networks with 4-bit Cartesian-Product MAC Array and Pipelined Activation Aligner,” Hot Chips, 2021 (Accepted).
  2. T. Imagawa, J. Yu, M. Hashimoto, H. Ochi, “MUX granularity oriented iterative technology mapping for implementing compute-intensive applications on via-switch FPGA,” Design, Automation and Test in Europe Conference (DATE), 2021.
  3. J. Suzuki, K. Ando, K. Hirose, K. Kawamura, T. V. Chu, M. Motomura, J. Yu, “ProgressiveNN: Achieving computational scalability without network alteration by MSB-first accumulative computation,” Proceedings of International Symposium on Computing and Networking (CANDAR), 2020, pp. 215 – 220.
  4. S. Kumazawa, K. Kawamura, T. Van Chu, M. Motomura and J. Yu, “ExtraFerns: Fully parallel ensemble learning technique with non-greedy yet minimal memory access training,” Proceedings of International Symposium on Computing and Networking (CANDAR), 2020, pp. 146 – 152.
  5. M. Hashimoto, X. Bai, N. Banno, M. Tada, T. Sakamoto, J. Yu, R. Doi, Y. Araki, H. Onodera, T. Imagawa, H. Ochi, K. Wakabayashi, Y. Mitsuyama, T. Sugibayashi, “Via-Switch FPGA: 65nm CMOS Implementation and Architecture Extension for AI Applications,” in Proceedings of IEEE International Solid-State Circuits Conference (ISSCC), 2020, pp. 502 – 503.
  6. A. Lopez, J. Yu, and M. Hashimoto, “Low-cost reservoir computing using cellular automata and random forests,” Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS), 2020, pp. 1 – 5.
  7. K. Onishi, J. Yu, and M. Hashimoto, “Memory efficient training using lookup-table-based quantization for neural network,” in Proceedings of IEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS), 2020, pp. 251 – 255.
  8. T.-Y. Cheng, J. Yu, and M. Hashimoto, “Minimizing energy for neural network training with logarithm-approximate floating-point multiplier,” in Proceedings of International Symposium on Power and Timing Modeling, Optimization and Simulation, 2019, pp. 91 – 96.
  9. T. Tanio, K. Takeda, J. Yu, J, and H. Masanori, “Training Data Reduction using Support Vectors for Neural Networks,” in Proceedings of Asia-Pacific Signal and Information Processing Association Annual Summit and Conference, 2019, pp 1405 – 1410.
  10. S. Fukui, J. Yu, and H. Masanori, “Distilling Knowledge for Non-Neural Networks,” in Proceedings of Asia-Pacific Signal and Information Processing Association Annual Summit and Conference, 2019, pp 1411 – 1416.
  11. K. Mitsunari, J. Yu, and M. Hashimoto, “Hardware architecture for fast general object detection using aggregated channel features,” in Proceedings of IEEE Asian Solid-State Circuits Conference, 2018, pp. 55 – 58.
  12. R. Doi, J. Yu, and M. Hashimoto, “Sneak path free reconfiguration of via-switch crossbar based FPGA,” in Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2018, pp. 68:1 – 68:8.
  13. K. Ito, J. Yu, and M. Hashimoto, “Adapting soft cascade to MAC operations of convolutional neural networks,” in Proceedings of International Symposium on Multimedia and Communication Technology, 2018, pp. 101 – 104.
  14. M. Hashimoto, Y. Nakazawa, R. Doi, and J. Yu, “Interconnect delay analysis for RRAM crossbar based FPGA,” in Proceedings of IEEE Computer Society Annual Symposium on VLSI, 2018, pp. 522 – 527.
  15. T. Sugiura, J. Yu, and Y. Takeuchi, “Hardware-oriented algorithm for phase synchronization analysis of biomedical signals,” in Proceedings of IEEE Biomedical Circuits and Systems Conference, 2017, pp. 1 – 4.
  16. T. Sugiura, A. U. Khan, J. Yu, Y. Takeuchi, S. Kameda, T. Kamata, Y. Hayashida, T. Yagi, and M. Imai, “A programmable controller for spatio-temporal pattern stimulation of cortical visual prosthesis,” in Proceedings of IEEE Biomedical Circuits and Systems Conference, 2016, pp. 432 – 435.
  17. M. Koga, T. Onoye, J. Yu, T. Azuma, and E. Aliwarga, “Vision-based comprehensive framework for senior driver assistance,” in Proceedings of ERTICO, 2016.
  18. Y. Hirao, J. Yu, Y. Takeuchi, and M. Imai, “Arrhythmia detection using a deformable part model and time domain features,” in Proceedings of International Workshop on Smart Info-Media Systems in Asia, 2016, pp. 94 – 99, (Student Best Paper Award).
  19. K. Mitsunari and J. Yu, “Influence of numerical precision on machine learning and embedded systems,” in Proceedings of International Workshop on Smart Info-Media Systems in Asia, 2016, pp. 164 – 169.
  20. K. Mitsunari, J. Yu, Y. Takeuchi, and M. Imai, “Object tracking based on path similarity of boosted decision trees,” in Proceedings of International Technical Conference on Circuits/Systems, Computers and Communications, 2016, pp. 563 – 566.
  21. J. Kawabe, Y. Takeuchi, J. Yu, and M. Imai, “Proposal of an efficient clock-gating mechanism for multi-core processors to reduce power supply noise,” in Proceedings of The 20th Workshop on Synthesis And System Integration of Mixed Information technologies, 2016, pp. 178 – 183.
  22. E. Aliwarga, K. Mitsunari, J. Yu, T. Onoye, T. Azuma, and M. Koga, “System design of vision-based framework for senior driver assistance,” in Proceedings of The 20th Workshop on Synthesis And System Integration of Mixed Information technologies, 2016, pp. 77 – 80.
  23. E. Aliwarga, J. Yu, M. Hatanaka, and T. Onoye, “Design of generic hardware for soft cascade-based linear SVM classification,” in Proceedings of IEEE International Symposium on Intelligent Signal Processing and Communication Systems, 2015, pp. 257 – 262
  24. T. Sugiura, J. Yu, Y. Takeuchi, and M. Imai, “A low-energy ASIP with flexible exponential Golomb codec for lossless data compression toward artificial vision systems,” in Proceedings of IEEE Biomedical Circuits and Systems Conference, 2015, pp. 97 – 100.
  25. R. Miyamoto, J. Yu, and T. Onoye, “Normalized channel features for accurate pedestrian detection,” in Proceedings of 6th International Symposium on Communications, Control and Signal Processing, 2014, pp. 582 – 585.
  26. T. Sugiura, S. Nakatsuka, J. Yu, Y. Takeuchi, and M. Imai, “An efficient data compression method for artificial vision systems and its low energy implementation using ASIP technology,” in Proceedings of IEEE Biomedical Circuits and Systems Conference, 2014, pp. 81 – 84.
  27. J. Yu, R. Miyamoto, T. Onoye, H. Sugano, and Y. Nakamura, “Pedestrian localization using CoHOG-based detection and HSV-based tracking,” in Proceedings of International Technical Conference on Circuits/Systems, Computers and Communications, 2012.
  28. J. Yu, H. Sugano, R. Miyamoto, and T. Onoye, “GPU implementation of efficient pedestrian detection based on MCMC,” in Proceedings of Joint 5th International Conference on Soft Computing and Intelligent Systems and 11th International Symposium on Advanced Intelligent Systems, 2010, pp. 1624 – 1629.
  29. J. Yu, H. Sugano, R. Miyamoto, and T. Onoye, “Computationally efficient pedestrian detection based on Markov chain Monte Carlo,” in Proceedings of the Second APSIPA Annual Summit and Conference, 2010, pp. 879 – 882.
  30. N. Ishikawa, H. Tsutsui, J. Yu, T. Izumi, H. Ochi, Y. Nakamura, T. Komura, and Y. Uchida, “Implementation of AV streaming system using peer-to-peer communication,” in 2007 4th IEEE Consumer Communications and Networking Conference, 2007, pp. 778 – 782.
  31. T. Izumi, J. Yu, T. Kimata, H. Ochi, and Y. Nakamura, “Implementation of AV control system over universal P2P network,” in Proceedings of International Conference on Computing, Communications and Control Technologies, 2005, pp. 9 – 14.

Invited Talks

  1. IEEE Computer Society Kansai Chapter 第1回技術講演会 機械学習の社会実装に向けた最新エンジニアリング「機械学習のためのアルゴリズムとハードウェア設計技術の現状と未来」2019年7月22日
  2. 電子情報通信学会 北海道支部 平成30年度専門講習会 次世代ICT技術と将来展望「機械学習とニューラルネットワーク」2019年2月4日

Patents

  1. PCT/JP2019/032455 土井龍太郎、劉載勲、橋本昌宜 「信号線の接続方法、プログラム、及び、半導体集積回路」2019年8月20日
  2. 特願2017-127405 劉載勲、光成浩一、武内良典、今井正治「 勾配方向ヒストグラム生成装置及び勾配方向ヒストグラム生成方法」2017年6月29日
  3. 特願2017-080747 水野雄介、尾上孝雄、劉載勲、光成浩一「画像処理装置, 画像処理システム, 情報処理システム及び画像処理方法」2017年4月14日
  4. 特願2017-080744 水野雄介、尾上孝雄、劉載勲、光成浩一「画像処理装置, 画像処理システム, 情報処理システム及び画像処理方法」2017年4月14日
  5. 特願2016-141865・特許第6677889号 小西雅彦、武内良典、劉載勲、今井正治「電気信号取得用床」2016年6月30日
  6. 特願2016-046274・特許第6650090号 小西雅彦、武内良典、劉載勲、今井正治「電気信号取得用着衣」2016年2月22日
  7. 特願2013-188673 劉載勲、宮本龍介、尾上孝雄「対象物検出装置, 方法およびプログラム, ならびに, 特徴量導出方法およびプログラム」2013年9月11日
  8. 特願2013-021863 劉載勲、宮本龍介、尾上孝雄「識別装置、データ判別装置、ソフトカスケード識別器を構成する方法、データの識別方法、および、プログラム」2013年2月7日