@article{ito_2026_Memory-Efficient,
title = {Memory-Efficient and Trustworthy Neural Networks via Random Seed-Based Design},
author = {Hiroaki Ito and Hikari Otsuka and Ryota Yasudo and Zhiqiang Que and Jose G. F. Coutinho and Daichi Fujiki and Masato Motomura and Ce Guo and Wayne Luk},
year = {2026},
date = {2026-01-29},
journal = {IEEE Access},
keywords = {Journal Papers},
pubstate = {published},
tppubtype = {article}
}
The Strong Lottery Ticket Hypothesis for Multi-Head Attention Mechanisms
@conference{nokey,
title = {TTF-GNN: Memory-Efficient GNNs via Tensor Train Decomposition and Network Folding},
author = {Hiroaki Ito and Jiale Yan and Kazushi Kawamura and Masato Motomura and Thiem Van Chu and Daichi Fujiki},
year = {2025},
date = {2025-03-20},
urldate = {2025-03-20},
booktitle = {COOL Chips 28},
address = {Japan},
keywords = {International Conference},
pubstate = {published},
tppubtype = {conference}
}
Accelerating Decision Forest Training via Node-Level Random Data Sampling
@workshop{nokey,
title = {Accelerating Decision Forest Training via Node-Level Random Data Sampling},
author = {Tsukasa Yamakura and Kazushi Kawamura and Daichi Fujiki and Masato Motomura and Thiem Van Chu},
year = {2025},
date = {2025-01-21},
urldate = {2025-01-21},
address = {Asia and South Pacific Design Automation Conference (ASP-DAC), WIP Poster},
keywords = {Awards, Workshop},
pubstate = {published},
tppubtype = {workshop}
}
Amorphica: A Fully Connected Annealer Supporting Metamorphic Annealing and Scalable Multi Chip Integration
@article{nokey_33,
title = {Amorphica: A Fully Connected Annealer Supporting Metamorphic Annealing and Scalable Multi Chip Integration},
author = {Okonogi Daiki and Yu Jaehoon and Jimbo Satoru and Inoue Genta and Hyodo Akira and Ando Kota and Hideki Fukushima-Kimura Bruno and Yasudo Ryota and van Chu Thiem and Motomura Masato and Kawamura Kazushi},
year = {2025},
date = {2025-10-13},
journal = {IEEE Access},
keywords = {Journal Papers},
pubstate = {published},
tppubtype = {article}
}
Binary Quadratic Quantization: Beyond First-Order Quantization for Real-Valued Matrix Compression
@conference{nokey,
title = {BingoGCN: Towards Scalable and Efficient GNN Acceleration with Fine-Grained Partitioning and SLT},
author = {Jiale Yan and Hiroaki Ito and Yuta Nagahara and Kazushi Kawamura and Masato Motomura and Thiem Van Chu and Daichi Fujiki},
year = {2025},
date = {2025-03-21},
urldate = {2025-03-21},
booktitle = {International Symposium on Computer Architecture (ISCA 2025)},
keywords = {International Conference},
pubstate = {published},
tppubtype = {conference}
}
Boltzmann Machine Is Useful for Enhancing Search Performance of Ising Machines
@article{nokey,
title = {DMSA: An Efficient Architecture for Sparse–Sparse Matrix Multiplication Based on Distribute-Merge Product Dataflow},
author = {Yuta Nagahara and Jiale Yan and Kazushi Kawamura and Daichi Fujiki and Masato Motomura and Thiem Van Chu
},
year = {2025},
date = {2025-04-23},
urldate = {2025-04-23},
journal = {IEEE Transactions on Very Large Scale Integration (VLSI) Systems},
keywords = {Journal Papers},
pubstate = {published},
tppubtype = {article}
}
DX100: Programmable Data Access Accelerator for Indirection
Alireza Khadem, Kamalavasan Kamalakkannan, Zhenyan Zhu, Akash Poptani, Yufeng Gu, Jered Benjamin Dominguez-Trujillo, Nishil Talati, Daichi Fujiki, Scott Mahlke, Galen Shipman, Reetuparna Das
International Symposium on Computer Architecture (ISCA 2025),2025
@conference{nokey,
title = {DX100: Programmable Data Access Accelerator for Indirection},
author = {Alireza Khadem and Kamalavasan Kamalakkannan and Zhenyan Zhu and Akash Poptani and Yufeng Gu and Jered Benjamin Dominguez-Trujillo and Nishil Talati and Daichi Fujiki and Scott Mahlke and Galen Shipman and Reetuparna Das
},
year = {2025},
date = {2025-03-21},
urldate = {2025-03-21},
booktitle = {International Symposium on Computer Architecture (ISCA 2025)},
keywords = {International Conference},
pubstate = {published},
tppubtype = {conference}
}
Multi-Dimensional Vector ISA Extension for Mobile In-Cache Computing
Alireza Khadem, Daichi Fujiki, Hilbert Chen, Yufeng Gu, Nishil Talati, Scott Mahlke, Reetuparna Das
IEEE International Symposium on High Performance Computer Architecture (HPCA 2025),2025
@conference{nokey,
title = {Multi-Dimensional Vector ISA Extension for Mobile In-Cache Computing},
author = {Alireza Khadem and Daichi Fujiki and Hilbert Chen and Yufeng Gu and Nishil Talati and Scott Mahlke and Reetuparna Das},
year = {2025},
date = {2025-03-01},
urldate = {2025-03-01},
booktitle = {IEEE International Symposium on High Performance Computer Architecture (HPCA 2025)},
keywords = {International Conference},
pubstate = {published},
tppubtype = {conference}
}
On the Existence of Hidden Subnetworks Within a Randomly Weighted Multi-Head Attention Mechanism
@workshop{nokeyz,
title = {On the Existence of Hidden Subnetworks Within a Randomly Weighted Multi-Head Attention Mechanism},
author = {Hikari Otsuka and Yasuyuki Okoshi and Daichi Fujiki and Susumu Takeuchi and Masato Motomura and Daiki Chijiwa},
year = {2025},
date = {2025-06-10},
urldate = {2025-06-10},
address = {High-dimensional Learning Dynamics Workshop, ICML},
keywords = {Workshop},
pubstate = {published},
tppubtype = {workshop}
}
Partially Frozen Random Networks Contain Compact Strong Lottery Tickets
@article{nokey,
title = {Partially Frozen Random Networks Contain Compact Strong Lottery Tickets},
author = {Hikari Otsuka and Daiki Chijiwa and {'A}ngel L{'o}pez Garc{'i}a-Arias and Yasuyuki Okoshi and Kazushi Kawamura and Thiem Van Chu and Daichi Fujiki and Susumu Takeuchi and Masato Motomura},
url = {https://openreview.net/forum?id=xpnPYfufhz},
year = {2025},
date = {2025-02-11},
journal = {Transactions on Machine Learning Research},
keywords = {Journal Papers},
pubstate = {published},
tppubtype = {article}
}
@conference{nokey_32,
title = {Rethinking Optimal Verification Granularity for Compute-Efficient Test-Time Scaling},
author = {Hao Mark Chen and Guanxi Lu and Yasuyuki Okoshi and Zhiwen Mo and Masato Motomura and Hongxiang Fan},
year = {2025},
date = {2025-12-05},
booktitle = {39th Annual Conference on Neural Information Processing Systems (NeurIPS 2025)},
keywords = {International Conference},
pubstate = {published},
tppubtype = {conference}
}
SharK: Enabling High-Performance Range Queries in Key-Value Store Through Vlog Resharding
@article{nokey,
title = {Uncovering Strong Lottery Tickets in Graph Transformers: A Path to Memory Efficient and Robust Graph Learning},
author = {Hiroaki Ito and Jiale Yan and Hikari Otsuka and Kazushi Kawamura and Masato Motomura and Thiem Van Chu and Daichi Fujiki},
year = {2025},
date = {2025-03-22},
urldate = {2025-03-22},
journal = {Transactions on Machine Learning Research},
keywords = {Journal Papers},
pubstate = {published},
tppubtype = {article}
}
Unlocking the Potential of Extremely Low-Bit Sparse Transformers through Adaptive Multi-bit Supermasks and Random Weights
@workshop{nokey_27,
title = {Unlocking the Potential of Extremely Low-Bit Sparse Transformers through Adaptive Multi-bit Supermasks and Random Weights},
author = {Yasuyuki Okoshi and Hikari Otsuka and Junnosuke Suzuki and Daichi Fujiki and Masato Motomura},
year = {2025},
date = {2025-06-10},
urldate = {2025-06-10},
address = {TTODLer-FM Workshop, ICML},
keywords = {Workshop},
pubstate = {published},
tppubtype = {workshop}
}
WhiteDwarf: A Holistic Co-Design Approach to Ultra-Compact Neural Inference Acceleration
@article{nokey,
title = {WhiteDwarf: A Holistic Co-Design Approach to Ultra-Compact Neural Inference Acceleration},
author = {Ángel López García-Arias and Yasuyuki Okoshi and Jaehoon Yu and Junnnosuke Suzuki and Hikari Otsuka and Kazushi Kawamura and Thiem Van Chu and Daichi Fujiki and Masato Motomura
},
year = {2025},
date = {2025-03-12},
journal = {IEEE Access},
keywords = {Journal Papers},
pubstate = {published},
tppubtype = {article}
}
@techreport{nokey,
title = {グラフトランスフォーマーにおける強い宝くじの発見},
author = {伊藤宏朗 and 嚴佳樂 and 大塚光莉 and 川村一志 and 本村真人 and ティエムヴァンチュ and 藤木大地},
year = {2025},
date = {2025-03-19},
urldate = {2025-03-19},
address = {第56回 IBISML研究会},
keywords = {Domestic Conference},
pubstate = {published},
tppubtype = {techreport}
}
@misc{talk-honkong-20240723,
title = {[Invited] Algorithm-Architecture Centric Approach Towards Energy Efficient AI Hardware},
author = {Masato Motomura},
year = {2024},
date = {2024-07-23},
urldate = {2024-07-23},
address = {Hong Kong University of Science and Technology Seminar},
keywords = {Invited Talks},
pubstate = {published},
tppubtype = {presentation}
}
[Invited] Algorithm-Architecture Centric Approach Towards Energy Efficient AI Hardware
@misc{nokey,
title = {[Invited] Towards Multi-Layer Processing-in-Memory Systems for General Applications},
author = {Daichi Fujiki},
year = {2024},
date = {2024-11-21},
urldate = {2024-11-21},
address = {Rising Star Express (RiSE) Forum at IEEE Asian Solid-State Circuits Conference (A-SSCC) 2024},
keywords = {Invited Talks},
pubstate = {published},
tppubtype = {presentation}
}
[Invited] Will AI Bite the Industry That Feeds It?
@misc{vlsi-20240618,
title = {[Invited] Will AI Bite the Industry That Feeds It?},
author = {Masato Motomura},
year = {2024},
date = {2024-06-18},
urldate = {2024-06-18},
address = {Evening Panel Moderation, Symposium on VLSI Technology and Circuits},
keywords = {Invited Talks},
pubstate = {published},
tppubtype = {presentation}
}
@misc{nagahara-vld-202402,
title = {[記念講演] 分散マージ乗算手法に基づく疎行列疎行列積アクセラレータ},
author = {永原 雄大 and Jiale Yan and 川村 一志 and 本村真人 and Thiem Van Chu},
year = {2024},
date = {2024-09-04},
urldate = {2024-02-29},
address = {電子情報通信学会 VLSI設計技術(VLD)研究会 Excellent Student Author Award for ASP-DAC 2024},
keywords = {Awards, Domestic Conference, Invited Talks},
pubstate = {published},
tppubtype = {presentation}
}
@techreport{nokey,
title = {2スピン同時フリップの並列試行により高効率な解探索を行うアニーリングプロセッサ},
author = {兵藤旭 and 神保聡 and 小此木大輝 and 井上源太 and Thiem Van Chu and 本村真人 and 川村一志},
year = {2024},
date = {2024-11-12},
urldate = {2024-11-12},
address = {デザインガイア},
keywords = {Domestic Conference},
pubstate = {published},
tppubtype = {techreport}
}
A GPU-Based Ising Machine With a Multi-Spin-Flip Capability for Constrained Combinatorial Optimization
@article{ieee-access-jimbo-2024,
title = {A GPU-Based Ising Machine With a Multi-Spin-Flip Capability for Constrained Combinatorial Optimization},
author = {Satoru Jimbo and Tatsuhiko Shirai and Nozomu Togawa and Masato Motomura and Kazushi Kawamura},
year = {2024},
date = {2024-03-21},
journal = {IEEE Access},
keywords = {Journal Papers},
pubstate = {published},
tppubtype = {article}
}
A Parallel-trial Double-update Annealing Algorithm for Enabling Highly-effective State Transition on Annealing Processors
@inproceedings{icce-2024-02,
title = {An Accurate FPGA-Based ORB Feature Extractor for SLAM with Row-Wise Keypoint Selection},
author = {Yuki Ichikawa and Akihiro Shioda and Kazushi Kawamura and Thiem Van Chu and Masato Motomura},
year = {2024},
date = {2024-01-05},
booktitle = {International Conference on Consumer Electronics (ICCE)},
keywords = {International Conference},
pubstate = {published},
tppubtype = {inproceedings}
}
Classical Thermodynamics-based Parallel Annealing Algorithm for High-speed and Robust Combinatorial Optimization
@inproceedings{kuroki-gecco-2024,
title = {Classical Thermodynamics-based Parallel Annealing Algorithm for High-speed and Robust Combinatorial Optimization},
author = {Kyo Kuroki and Satoru Jimbo and Thiem Van Chu and Masato Motomura and Kazushi Kawamura},
year = {2024},
date = {2024-07-14},
booktitle = {The Genetic and Evolutionary Computation Conference (GECCO)},
keywords = {International Conference},
pubstate = {published},
tppubtype = {inproceedings}
}
@inproceedings{yan2024efficientcodesign,
title = {Efficient Co-Design of Hardware and Algorithms for SLT-based Graph Neural Networks},
author = {Jiale Yan and Hiroaki Ito and Kazushi Kawamura and Thiem Van Chu and Daichi Fujiki and Masato Motomura},
booktitle = {6th R-CCS International Symposium},
address = {Kobe, Japan},
month = jan,
year = {2024}
}
Efficient COO to CSR Conversion for Accelerating Sparse Matrix Processing on FPGA
Yuta Nagahara, Jiale Yan, Kazushi Kawamura, Masato Motomura, Thiem Van Chu
International Conference on Consumer Electronics (ICCE),2024
@inproceedings{icce-2024-01,
title = {Efficient COO to CSR Conversion for Accelerating Sparse Matrix Processing on FPGA},
author = {Yuta Nagahara and Jiale Yan and Kazushi Kawamura and Masato Motomura and Thiem Van Chu},
year = {2024},
date = {2024-01-05},
booktitle = {International Conference on Consumer Electronics (ICCE)},
keywords = {International Conference},
pubstate = {published},
tppubtype = {inproceedings}
}
Efficient Stereo Visual Odometry on FPGA Featuring On-Chip Map Management and Pipelined Descriptor-Based Block Matching
Yuki Ichikawa, Kazushi Kawamura, Masato Motomura, Thiem Van Chu
@inproceedings{yamakura-ijcnn-2024,
title = {ETreeNet: Ensemble Model Fusing Decision Trees and Neural Networks for Small Tabular Data},
author = {Tsukasa Yamakura and Kazushi Kawamura and Masato Motomura and Thiem Van Chu},
year = {2024},
date = {2024-06-30},
booktitle = {International Joint Conference on Neural Networks (IJCNN)},
keywords = {International Conference},
pubstate = {published},
tppubtype = {inproceedings}
}
Exploiting N: M Sparsity in Quantized-Folded ResNets: Signed Multicoat Supermasks and Iterative Pruning-Quantization
@conference{nokey,
title = {Exploiting N: M Sparsity in Quantized-Folded ResNets: Signed Multicoat Supermasks and Iterative Pruning-Quantization},
author = {Akihiro Shioda and Ángel López García-Arias and Hikari Otsuka and Yuki Ichikawa and Yasuyuki Okoshi and Kazushi Kawamura and Thiem Van Chu and Daichi Fujiki and Masato Motomura},
url = {https://ieeexplore.ieee.org/abstract/document/10818255},
year = {2024},
date = {2024-12-03},
urldate = {2024-12-03},
booktitle = {2024 Twelfth International Symposium on Computing and Networking (CANDAR)},
keywords = {International Conference},
pubstate = {published},
tppubtype = {conference}
}
Exploration of Hyperdimensional Computing Using Locality-Sensitive Hashing Mechanism on FPGA
@inproceedings{icce-2024-04,
title = {Exploration of Hyperdimensional Computing Using Locality-Sensitive Hashing Mechanism on FPGA},
author = {Masato Watanabe and Shungo Kumazawa and Thiem Van Chu and Kazushi Kawamura and Jaehoon Yu and Masato Motomura},
year = {2024},
date = {2024-01-05},
booktitle = {International Conference on Consumer Electronics (ICCE)},
keywords = {International Conference},
pubstate = {published},
tppubtype = {inproceedings}
}
GPB: An Efficient GBDT Training Method with Tree-Level Parallelism Using Binary Feature Decomposition
@workshop{nokey,
title = {GPB: An Efficient GBDT Training Method with Tree-Level Parallelism Using Binary Feature Decomposition},
author = {Tsukasa Yamakura and Kazushi Kawamura and Daichi Fujiki and Masato Motomura and Thiem Van Chu},
year = {2024},
date = {2024-11-03},
urldate = {2024-11-03},
address = {IEEE/ACM International Symposium on Microarchitecture (MICRO), Student Research Competition},
keywords = {Workshop},
pubstate = {published},
tppubtype = {workshop}
}
High Throughput Datapath Design for Vision Permutator FPGA Accelerator
Mari Yasunaga, Junnosuke Suzuki, Masato Watanabe, Kazushi Kawamura, Thiem Van Chu, Masato Motomura
International Conference on Consumer Electronics (ICCE),2024
@inproceedings{ito2024memoryefficient,
title = {Memory-efficient Methods for Graph Transformer Using Strong Lottery Tickets Hypothesis},
author = {Hiroaki Ito and Jiale Yan and Kazushi Kawamura and Thiem Van Chu and Daichi Fujiki and Masato Motomura},
booktitle = {6th R-CCS International Symposium},
address = {Kobe, Japan},
month = jan,
year = {2024}
}
OSA-HCIM: On-The-Fly Saliency-Aware Hybrid SRAM CIM with Dynamic Precision Configuration
YC Chen, S Ando, D Fujiki, S Takamaeda-Yamazaki, K Yoshioka
@proceedings{asp-dac_2024_dfujiki,
title = {OSA-HCIM: On-The-Fly Saliency-Aware Hybrid SRAM CIM with Dynamic Precision Configuration},
author = {YC Chen, S Ando, D Fujiki, S Takamaeda-Yamazaki, K Yoshioka},
year = {2024},
date = {2024-01-25},
urldate = {2024-01-25},
howpublished = {2024 29th Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 539-544},
keywords = {International Conference},
pubstate = {published},
tppubtype = {proceedings}
}
Partially Frozen Random Networks Contain Compact Strong Lottery Tickets
@workshop{neurips_2024_otuska,
title = {Partially Frozen Random Networks Contain Compact Strong Lottery Tickets},
author = {Hikari Otsuka and Daiki Chijiwa and {'A}ngel L{'o}pez Garc{'i}a-Arias and Yasuyuki Okoshi and Kazushi Kawamura and Thiem Van Chu and Daichi Fujiki and Susumu Takeuchi and Masato Motomura},
url = {https://openreview.net/forum?id=xfE4Dk3X6c},
year = {2024},
date = {2024-12-25},
urldate = {2024-12-25},
address = {Workshop on Machine Learning and Compression, NeurIPS},
keywords = {Workshop},
pubstate = {published},
tppubtype = {workshop}
}
Progressive Variable Precision DNN with Bitwise Ternary Accumulation
Junnosuke Suzuki, Mari Yasunaga, Kazushi Kawamura, Thiem Van Chu, Masato Motomura
International Conference on Artificial Intelligence Circuits and Systems (AICAS),2024
@inproceedings{suzuki-aicas-2024,
title = {Progressive Variable Precision DNN with Bitwise Ternary Accumulation},
author = {Junnosuke Suzuki and Mari Yasunaga and Kazushi Kawamura and Thiem Van Chu and Masato Motomura},
year = {2024},
date = {2024-04-23},
booktitle = {International Conference on Artificial Intelligence Circuits and Systems (AICAS)},
keywords = {International Conference},
pubstate = {published},
tppubtype = {inproceedings}
}
Ramanujan Edge-Popup: Finding Strong Lottery Tickets with Ramanujan Graph Properties for Efficient DNN Inference Execution
@inproceedings{otsuka-sasimi-2024,
title = {Ramanujan Edge-Popup: Finding Strong Lottery Tickets with Ramanujan Graph Properties for Efficient DNN Inference Execution},
author = {Hikari Otsuka and Yasuyuki Okoshi and Ángel López García-Arias and Kazushi Kawamura and Thiem Van Chu and Masato Motomura},
year = {2024},
date = {2024-03-12},
booktitle = {Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI)},
keywords = {International Conference},
pubstate = {published},
tppubtype = {inproceedings}
}
Restricted Random Pruning at Initialization for High Compression Range
@article{otsuka-tmlr-202405,
title = {Restricted Random Pruning at Initialization for High Compression Range},
author = {Hikari Otsuka and Yasuyuki Okoshi and Ángel López García-Arias and Kazushi Kawamura and Thiem Van Chu and Daichi Fujiki and Masato Motomura},
year = {2024},
date = {2024-05-01},
journal = {Transactions on Machine Learning Research (TMLR)},
keywords = {Journal Papers},
pubstate = {published},
tppubtype = {article}
}
Sparse-Sparse Matrix Multiplication Accelerator on FPGA featuring Distribute-Merge Product Dataflow
Yuta Nagahara, Jiale Yan, Kazushi Kawamura, Masato Motomura, Thiem Van Chu
Asia and South Pacific Design Automation Conference (ASP-DAC),2024
@inproceedings{asp-dac-2024,
title = {Sparse-Sparse Matrix Multiplication Accelerator on FPGA featuring Distribute-Merge Product Dataflow},
author = {Yuta Nagahara and Jiale Yan and Kazushi Kawamura and Masato Motomura and Thiem Van Chu},
year = {2024},
date = {2024-01-25},
booktitle = {Asia and South Pacific Design Automation Conference (ASP-DAC)},
keywords = {International Conference},
pubstate = {published},
tppubtype = {inproceedings}
}
The Case for Coherence Directories in Memory Cubes
2024 17th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC-2024),2024
@conference{nokey,
title = {The Case for Coherence Directories in Memory Cubes},
author = {Yuki Kameyama and Naoya Niwa and Daichi Fujiki and Hiroki Matsutani and Michihiro Koibuchi and Hideharu Amano},
year = {2024},
date = {2024-12-12},
urldate = {2024-12-12},
booktitle = {2024 17th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC-2024)},
keywords = {International Conference},
pubstate = {published},
tppubtype = {conference}
}
The Trichromatic Strong Lottery Ticket Hypothesis: Neural Compression With Three Primary Supermasks
@article{ieee-access-kumazawa-2024,
title = {Toward Improving Ensemble-Based Collaborative Inference at the Edge},
author = {Shungo Kumazawa and Jaehoon Yu and Kazushi Kawamura and Thiem Van Chu and Masato Motomura},
year = {2024},
date = {2024-01-08},
urldate = {2024-01-08},
journal = {IEEE Access},
keywords = {Journal Papers},
pubstate = {published},
tppubtype = {article}
}
WhiteDwarf: 12.24 TFLOPS/W 40 nm Versatile Neural Inference Engine for Ultra-Compact Execution of CNNs and MLPs Through Triple Unstructured Sparsity Exploitation and Triple Model Compression
@conference{nokey,
title = {WhiteDwarf: 12.24 TFLOPS/W 40 nm Versatile Neural Inference Engine for Ultra-Compact Execution of CNNs and MLPs Through Triple Unstructured Sparsity Exploitation and Triple Model Compression},
author = {Yasuyuki Okoshi and Ángel López García-Arias and Jaehoon Yu and Junnnosuke Suzuki and Hikari Otsuka and Thiem Van Chu and Kazushi Kawamura and Daichi Fujiki and Masato Motomura
},
url = {https://ieeexplore.ieee.org/document/10849314
},
year = {2024},
date = {2024-11-18},
urldate = {2024-11-18},
booktitle = {2024 IEEE Asian Solid-State Circuits Conference (A-SSCC)},
keywords = {International Conference},
pubstate = {published},
tppubtype = {conference}
}
パイプライン処理と画像特徴の転用によるSLAMアクセラレータの効率化
Yuki Ichikawa, Kazushi Kawamura, Masato Motomura, Thiem Van Chu
@inproceedings{iiswc-2023,
title = {[Best Paper Nomination] Vector-Processing for Mobile Devices: Benchmark and Analysis},
author = {Alireza Khadem and Daichi Fujiki and Nishil Talati and Scott A. Mahlke and Reetuparna Das},
year = {2023},
date = {2023-10-02},
booktitle = {IEEE International Symposium on Workload Characterization},
keywords = {Awards, International Conference},
pubstate = {published},
tppubtype = {inproceedings}
}
[Best Poster Award] Optimized Deep MLP for Tensor Train-based Inference Engine
Jiale Yan, Masato Motomura
IEEE Symposium on Low-Power and High-Speed Chips and Systems (COOL Chips),2023
@inproceedings{jiale-coolchips2023,
title = {[Best Poster Award] Optimized Deep MLP for Tensor Train-based Inference Engine},
author = {Jiale Yan and Masato Motomura},
year = {2023},
date = {2023-04-21},
urldate = {2023-04-21},
booktitle = {IEEE Symposium on Low-Power and High-Speed Chips and Systems (COOL Chips)},
keywords = {Awards, International Conference},
pubstate = {published},
tppubtype = {inproceedings}
}
[Invited – Keynote] The Future of Low-bitwidth Reconfigurable and Parallel AI Computing
@misc{samsung-ai-forum-2023,
title = {[Invited] AI Computing - Tackling the Explosions of Data to Process and Decisions to Make},
author = {Masato Motomura},
year = {2023},
date = {2023-11-07},
address = {Samsung AI Forum},
keywords = {Invited Talks},
pubstate = {published},
tppubtype = {presentation}
}
@misc{suzuki-VLSI2023-invited,
title = {[Invited] Pianissimo: A Sub-mW Class DNN Accelerator with Progressive Bit-by-Bit Datapath Architecture for Adaptive Inference at Edge},
author = {鈴木 淳之介 and 安永 真梨 and Ángel López García-Arias and 大越 康之 and 熊澤 峻悟 and 安藤 洸太 and 川村 一志 and Thiem Van Chu and 本村 真人},
year = {2023},
date = {2023-07-25},
urldate = {2023-07-25},
howpublished = {Symposia on VLSI Technology/Circuits 国内報告会},
keywords = {Invited Talks},
pubstate = {published},
tppubtype = {presentation}
}
@misc{motomura-ISMVL-2023,
title = {[Keynote] Tackling the Explosions of Data and Solutions with Low-Bitwidth Computing Architectures},
author = {Masato Motomura},
year = {2023},
date = {2023-05-22},
urldate = {2023-05-22},
address = {IEEE International Symposium on Multiple-Valued Logic (ISMVL)},
keywords = {Invited Talks},
pubstate = {published},
tppubtype = {presentation}
}
@article{ieice-d-2023-okonogi,
title = {A Fully-Parallel Annealing Algorithm with Autonomous Pinning Effect Control for Various Combinatorial Optimization Problems},
author = {Daiki Okonogi and Satoru Jimbo and Kota Ando and Thiem Van Chu and Jaehoon Yu and Masato Motomura and Kazushi Kawamura},
year = {2023},
date = {2023-12-01},
journal = {IEICE Transactions on Information and Systems},
keywords = {Journal Papers},
pubstate = {published},
tppubtype = {article}
}
A Highly Accurate and Parallel Vision MLP FPGA Accelerator based on FP7/8 SIMD Operations
Mari Yasunaga, Junnosuke Suzuki, Masato Watanabe, Kazushi Kawamura, Thiem Van Chu, Jaehoon Yu, Masato Motomura
International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC),2023
@inproceedings{mcsoc-2023-yasunaga,
title = {A Highly Accurate and Parallel Vision MLP FPGA Accelerator based on FP7/8 SIMD Operations},
author = {Mari Yasunaga and Junnosuke Suzuki and Masato Watanabe and Kazushi Kawamura and Thiem Van Chu and Jaehoon Yu and Masato Motomura},
year = {2023},
date = {2023-12-18},
booktitle = {International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC)},
keywords = {International Conference},
pubstate = {published},
tppubtype = {inproceedings}
}
Amorphica: 4-Replica 512 Fully Connected Spin 336MHz Metamorphic Annealer with Programmable Optimization Strategy and Compressed-Spin-Transfer Multi-Chip Extension
Kazushi Kawamura, Jaehoon Yu, Daiki Okonogi, Satoru Jimbo, Genta Inoue, Akira Hyodo, Ángel López García-Arias, Kota Ando, Bruno Hideki Fukushima-Kimura, Ryota Yasudo, Thiem Van Chu, Masato Motomura
International Solid-State Circuits Conference (ISSCC),2023
@inproceedings{amorphica-isscc2023,
title = {Amorphica: 4-Replica 512 Fully Connected Spin 336MHz Metamorphic Annealer with Programmable Optimization Strategy and Compressed-Spin-Transfer Multi-Chip Extension},
author = {Kazushi Kawamura and Jaehoon Yu and Daiki Okonogi and Satoru Jimbo and Genta Inoue and Akira Hyodo and Ángel López García-Arias and Kota Ando and Bruno Hideki Fukushima-Kimura and Ryota Yasudo and Thiem Van Chu and Masato Motomura
},
year = {2023},
date = {2023-02-19},
urldate = {2023-02-19},
booktitle = {International Solid-State Circuits Conference (ISSCC)},
keywords = {International Conference},
pubstate = {published},
tppubtype = {inproceedings}
}
Decision Forest Training Accelerator Based on Binary Feature Decomposition
Thiem Van Chu, Yu Mizutani, Yuta Nagahara, Shungo Kumazawa, Kazushi Kawamura, Jaehoon Yu, Masato Motomura
International Symposium on Field-Programmable Custom Computing Machines (FCCM),2023
@inproceedings{fccm-2023-thiem,
title = {Decision Forest Training Accelerator Based on Binary Feature Decomposition},
author = {Thiem Van Chu and Yu Mizutani and Yuta Nagahara and Shungo Kumazawa and Kazushi Kawamura and Jaehoon Yu and Masato Motomura},
year = {2023},
date = {2023-05-09},
booktitle = {International Symposium on Field-Programmable Custom Computing Machines (FCCM)},
keywords = {International Conference},
pubstate = {published},
tppubtype = {inproceedings}
}
Flexibly Controllable Dynamic Cooling Methods for Solid-State Annealing Processors to Improve Combinatorial Optimization Performance
@article{bruno-journal-2023-2,
title = {Mixing time and simulated annealing for the stochastic cellular automata},
author = {Bruno Hideki Fukushima-Kimura and Satoshi Handa and Katsuhiro Kamakura and Yoshinori Kamijima and Kazushi Kawamura and Akira Sakai},
doi = {10.1007/s10955-023-03090-x},
year = {2023},
date = {2023-12-01},
journal = {Journal of Statistical Physics},
volume = {190},
number = {79},
pages = {1-20},
keywords = {Journal Papers},
pubstate = {published},
tppubtype = {article}
}
Multicoated and Folded Graph Neural Networks with Strong Lottery Tickets
@misc{yan2023multicoatedfoldedgraphneural,
title={Multicoated and Folded Graph Neural Networks with Strong Lottery Tickets},
author={Jiale Yan and Hiroaki Ito and Ángel López García-Arias and Yasuyuki Okoshi and Hikari Otsuka and Kazushi Kawamura and Thiem Van Chu and Masato Motomura},
year={2023},
eprint={2312.03236},
archivePrefix={arXiv},
primaryClass={cs.LG},
url={https://arxiv.org/abs/2312.03236},
}
MVC: Enabling Fully Coherent Multi-Data-Views through the Memory Hierarchy with Processing in Memory
Daichi Fujiki
Proceedings of the 56th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO 2023),2023
@conference{nokey,
title = {MVC: Enabling Fully Coherent Multi-Data-Views through the Memory Hierarchy with Processing in Memory},
author = {Daichi Fujiki},
year = {2023},
date = {2023-12-08},
urldate = {2023-12-08},
booktitle = {Proceedings of the 56th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO 2023)
},
keywords = {International Conference},
pubstate = {published},
tppubtype = {conference}
}
Pianissimo: A Sub-mW Class DNN Accelerator with Progressive Bit-by-Bit Datapath Architecture for Adaptive Inference at Edge
Junnosuke Suzuki, Jaehoon Yu, Mari Yasunaga, Ángel López García-Arias, Yasuyuki Okoshi, Shungo Kumazawa, Kota Ando, Kazushi Kawamura, Thiem Van Chu, Masato Motomura
Symposium on VLSI Technology and Circuits, 2023,2023
@conference{suzuki-vssympo-2023,
title = {Pianissimo: A Sub-mW Class DNN Accelerator with Progressive Bit-by-Bit Datapath Architecture for Adaptive Inference at Edge},
author = {Junnosuke Suzuki and Jaehoon Yu and Mari Yasunaga and Ángel López García-Arias and Yasuyuki Okoshi and Shungo Kumazawa and Kota Ando and Kazushi Kawamura and Thiem Van Chu and Masato Motomura},
year = {2023},
date = {2023-06-14},
booktitle = {Symposium on VLSI Technology and Circuits, 2023},
keywords = {International Conference},
pubstate = {published},
tppubtype = {conference}
}
Pianissimo: A Sub-mW Class DNN Accelerator With Progressively Adjustable Bit-Precision
Junnosuke Suzuki, Jaehoon Yu, Mari Yasunaga, Ángel López García-Arias, Yasuyuki Okoshi, Shungo Kumazawa, Kota Ando, Kazushi Kawamura, Thiem Van Chu, Masato Motomura
@article{ieee-access-pianissimo,
title = {Pianissimo: A Sub-mW Class DNN Accelerator With Progressively Adjustable Bit-Precision},
author = {Junnosuke Suzuki and Jaehoon Yu and Mari Yasunaga and Ángel López García-Arias and Yasuyuki Okoshi and Shungo Kumazawa and Kota Ando and Kazushi Kawamura and Thiem Van Chu and Masato Motomura},
year = {2023},
date = {2023-12-26},
journal = {IEEE Access},
keywords = {Journal Papers},
pubstate = {published},
tppubtype = {article}
}
@article{bruno-journal-2023-1,
title = {Stochastic optimization: Glauber dynamics versus stochastic cellular automata},
author = {Bruno Hideki Fukushima-Kimura and Yoshinori Kamijima and Kazushi Kawamura and Akira Sakai},
doi = {10.5687/iscie.36.9},
year = {2023},
date = {2023-12-01},
journal = {Transactions of the Institute of Systems, Control and Information Engineers},
volume = {36},
number = {1},
pages = {9-16},
keywords = {Journal Papers},
pubstate = {published},
tppubtype = {article}
}
@article{ieice-d-2022-jimbo,
title = {A Hybrid Integer Encoding Method for Obtaining High-quality Solutions of Quadratic Knapsack Problems on Solid-state Annealers},
author = {Satoru Jimbo and Daiki Okonogi and Kota Ando and Thiem Van Chu and Jaehoon Yu and Masato Motomura and Kazushi Kawamura},
year = {2022},
date = {2022-12-01},
journal = {IEICE Transactions on Information and Systems},
keywords = {Journal Papers},
pubstate = {published},
tppubtype = {article}
}
A Unhealthy Plant Identification System Using a Generative Adversarial Network
@inproceedings{ecticon2022,
title = {A Unhealthy Plant Identification System Using a Generative Adversarial Network},
author = {Satida Sookpong and Teerasit Kasetkasem and Teera Phatrapornnant and Jaehoon Yu},
year = {2022},
date = {2022-05-25},
booktitle = {International Conference on Electrical Engineering/Electronics, Computer, Telecommunications and Information Technology (ECTI-CON)},
keywords = {International Conference},
pubstate = {published},
tppubtype = {inproceedings}
}
Hiddenite: 4K-PE Hidden Network Inference 4D-Tensor Engine Exploiting On-Chip Model Construction Achieving 34.8-to-16.0TOPS/W for CIFAR-100 and ImageNet
Kazutoshi Hirose, Jaehoon Yu, Kota Ando, Yasuyuki Okoshi, Ángel López García-Arias, Junnosuke Suzuki, Thiem Van Chu, Kazushi Kawamura, Masato Motomura
International Solid-State Circuits Conference (ISSCC),2022
@inproceedings{hiddenite-isscc2022,
title = {Hiddenite: 4K-PE Hidden Network Inference 4D-Tensor Engine Exploiting On-Chip Model Construction Achieving 34.8-to-16.0TOPS/W for CIFAR-100 and ImageNet},
author = {Kazutoshi Hirose and Jaehoon Yu and Kota Ando and Yasuyuki Okoshi and Ángel López García-Arias and Junnosuke Suzuki and Thiem Van Chu and Kazushi Kawamura and Masato Motomura},
year = {2022},
date = {2022-02-20},
booktitle = {International Solid-State Circuits Conference (ISSCC)},
keywords = {International Conference},
pubstate = {published},
tppubtype = {inproceedings}
}
IEEE Fellow “for contributions to memory-logic integration of reconfigurable chip architecture.”
@inproceedings{mwscas2022,
title = {Investigating Small Device Implementation of FRET-based Optical Reservoir Computing},
author = {Masafumi Tanaka and Jaehoon Yu and Masaki Nakagawa and Naoya Tate and Masanori Hashimoto},
year = {2022},
date = {2022-08-07},
booktitle = {The IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)},
keywords = {International Conference},
pubstate = {published},
tppubtype = {inproceedings}
}
Multicoated Supermasks Enhance Hidden Networks
Yasuyuki Okoshi, Ángel López García-Arias, Kazutoshi Hirose, Kota Ando, Kazushi Kawamura, Thiem Van Chu, Masato Motomura, Jaehoon Yu
International Conference on Machine Learning (ICML),2022
@inproceedings{icml2022-okoshi,
title = {Multicoated Supermasks Enhance Hidden Networks},
author = {Yasuyuki Okoshi and Ángel López García-Arias and Kazutoshi Hirose and Kota Ando and Kazushi Kawamura and Thiem Van Chu and Masato Motomura and Jaehoon Yu},
year = {2022},
date = {2022-07-23},
booktitle = {International Conference on Machine Learning (ICML)},
keywords = {International Conference},
pubstate = {published},
tppubtype = {inproceedings}
}
QKP-QUBO変換におけるHybridエンコーディング方式
Satoru Jimbo, Daiki Okonogi, Kota Ando, Thiem Van Chu, Jaehoon Yu, Masato Motomura, Kazushi Kawamura
@techreport{jimbo-qs-2022,
title = {QKP-QUBO変換におけるHybridエンコーディング方式},
author = {神保 聡 and 小此木 大輝 and 安藤 洸太 and Thiem Van Chu and 劉 載勲 and 本村 真人 and 川村 一志},
year = {2022},
date = {2022-03-24},
urldate = {2022-03-24},
address = {第5回量子ソフトウェア研究発表会},
keywords = {Domestic Conference},
pubstate = {published},
tppubtype = {techreport}
}
Via-switch FPGA with transistor-free programmability enabling energy-efficient near-memory parallel computation
Masanori Hashimoto, X Bai, Naoki Banno, Munehiro Tada, Toshitsugu Sakamoto, Jaehoon Yu, Ryutaro Doi, Hidetoshi Onodera, Takashi Imagawa, Hiroyuki Ochi
@article{viaswitch-fpga-physics,
title = {Via-switch FPGA with transistor-free programmability enabling energy-efficient near-memory parallel computation},
author = {Masanori Hashimoto and X Bai and Naoki Banno and Munehiro Tada and Toshitsugu Sakamoto and Jaehoon Yu and Ryutaro Doi and Hidetoshi Onodera and Takashi Imagawa and Hiroyuki Ochi},
doi = {10.35848/1347-4065/ac6b81},
year = {2022},
date = {2022-04-28},
journal = {Japanese Journal of Applied Physics},
keywords = {Journal Papers},
pubstate = {published},
tppubtype = {article}
}
@techreport{okonogi-qs-2022,
title = {全並列アニーリングのための自律的パラメータ制御},
author = {小此木 大輝 and 神保 聡 and 安藤 洸太 and Thiem Van Chu and 劉 載勲 and 本村 真人 and 川村 一志},
year = {2022},
date = {2022-03-24},
urldate = {2022-03-24},
address = {第5回量子ソフトウェア研究発表会},
keywords = {Domestic Conference},
pubstate = {published},
tppubtype = {techreport}
}
外部メモリアクセス抑制による高効率疎行列積アクセラレータの研究
Yuta Nagahara, Kota Ando, Kazushi Kawamura, Jaehoon Yu, Masato Motomura, Thiem Van Chu
@techreport{inoue-SLDM2022,
title = {巡回セールスマン問題を対象とした並列アニーリング手法の評価},
author = {井上 源太 and 小此木 大輝 and Thiem Van Chu and 劉 載勲 and 本村 真人 and 川村 一志},
year = {2022},
date = {2022-11-04},
urldate = {2022-11-04},
address = {第199回SLDM研究発表会(SLDM WIP Forum 2022)},
keywords = {Domestic Conference},
pubstate = {published},
tppubtype = {techreport}
}
2021
[Best Paper Award] A High-Performance and Flexible FPGA Inference Accelerator for Decision Forests Based on Prior Feature Space Partitioning
@inproceedings{thiem-fpt2021,
title = {[Best Paper Award] A High-Performance and Flexible FPGA Inference Accelerator for Decision Forests Based on Prior Feature Space Partitioning},
author = {Thiem Van Chu and Ryuichi Kitajima and Kazushi Kawamura and Jaehoon Yu and Masato Motomura},
year = {2021},
date = {2021-12-06},
urldate = {2021-12-06},
booktitle = {International Conference on Field-Programmable Technology (FPT)},
keywords = {Awards, International Conference},
pubstate = {published},
tppubtype = {inproceedings}
}
@misc{motomura-asap2021,
title = {[Invited] CGRAs for Broad Embedded Market & for Neural Networks},
author = {Masato Motomura},
year = {2021},
date = {2021-07-08},
address = {Position Talk in the "Panel: Coarse-Grained Reconfigurable Arrays and their Opportunities as Application Accelerators," IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP)},
keywords = {Invited Talks},
pubstate = {published},
tppubtype = {presentation}
}
@article{shiba-ieeetcs2020,
title = {A 96-MB 3D-Stacked SRAM Using Inductive Coupling with 0.4-V Transmitter, Termination Scheme and 12:1 SerDes in 40-nm CMOS},
author = {Kota Shiba and Tatsuo Omori and Kodai Ueyoshi and Kota Ando and Kazutoshi Hirose and Shinya Takamaeda-Yamazaki and Masato Motomura and Mototsugu Hamada and Tadahiro Kuroda},
year = {2021},
date = {2021-02-01},
journal = {IEEE Transactions on Circuits and Systems I},
volume = {68},
number = {2},
pages = {692-703},
keywords = {Journal Papers},
pubstate = {published},
tppubtype = {article}
}
Edge Inference Engine for Deep & Random Sparse Neural Networks with 4-bit Cartesian-Product MAC Array and Pipelined Activation Aligner
Kota Ando, Jaehoon Yu, Kazutoshi Hirose, Hiroki Nakahara, Kazushi Kawamura, Thiem Van Chu, Masato Motomura
@inproceedings{ando-hotchips-2021,
title = {Edge Inference Engine for Deep & Random Sparse Neural Networks with 4-bit Cartesian-Product MAC Array and Pipelined Activation Aligner},
author = {Kota Ando and Jaehoon Yu and Kazutoshi Hirose and Hiroki Nakahara and Kazushi Kawamura and Thiem Van Chu and Masato Motomura},
year = {2021},
date = {2021-08-24},
booktitle = {Hot Chips 33 (Poster)},
keywords = {International Conference},
pubstate = {published},
tppubtype = {inproceedings}
}
ExtraFerns: Fully Parallel Ensemble Learning Technique with Random Projection and Non-Greedy yet Minimal Memory Access Training
@article{kumazawa-ijnc-2021,
title = {ExtraFerns: Fully Parallel Ensemble Learning Technique with Random Projection and Non-Greedy yet Minimal Memory Access Training},
author = {Shungo Kumazawa and Kazushi Kawamura and Thiem Van Chu and Masato Motomura and Jaehoon Yu},
year = {2021},
date = {2021-07-08},
journal = {International Journal of Networking and Computing},
volume = {11},
number = {2},
pages = {215-230},
keywords = {Journal Papers},
pubstate = {published},
tppubtype = {article}
}
Hidden-Fold Networks: Random Recurrent Residuals Using Sparse Supermasks
@inproceedings{yu-date-2021,
title = {MUX Granularity-Oriented Iterative Technology Mapping for Implementing Compute-Intensive Applications on Via-Switch FPGA},
author = {Takashi Imagawa and Jaehoon Yu and Masanori Hashimoto and Hiroyuki Ochi},
year = {2021},
date = {2021-02-01},
booktitle = {Design, Automation and Test in Europe Conference (DATE)},
keywords = {International Conference},
pubstate = {published},
tppubtype = {inproceedings}
}
ProgressiveNN: Achieving Computational Scalability with Dynamic Bit-Precision Adjustment by MSB-first Accumulative Computation
Junnosuke Suzuki, Tomohiro Kaneko, Kota Ando, Kazutoshi Hirose, Kazushi Kawamura, Thiem Van Chu, Masato Motomura, Jaehoon Yu
International Journal of Networking and Computing,2021
@article{suzuki-ijnc-2021,
title = {ProgressiveNN: Achieving Computational Scalability with Dynamic Bit-Precision Adjustment by MSB-first Accumulative Computation},
author = {Junnosuke Suzuki and Tomohiro Kaneko and Kota Ando and Kazutoshi Hirose and Kazushi Kawamura and Thiem Van Chu and Masato Motomura and Jaehoon Yu},
year = {2021},
date = {2021-07-08},
journal = {International Journal of Networking and Computing},
volume = {11},
number = {2},
pages = {338-353},
keywords = {Journal Papers},
pubstate = {published},
tppubtype = {article}
}
@techreport{suzuki-lsi-2021,
title = {ビットスケーラブルCNNにおける計算量・精度トレードオフ制御手法の検討},
author = {鈴木 淳之介 and 安藤 洸太 and 廣瀬 一俊 and 川村 一志 and Thiem Van Chu and 本村 真人 and 劉載勲},
year = {2021},
date = {2021-05-10},
urldate = {2021-05-10},
address = {LSIとシステムとワークショップ},
keywords = {Domestic Conference},
pubstate = {published},
tppubtype = {techreport}
}
@techreport{kumazawa-lsi-2021,
title = {入力空間のランダム射影と分割に基づくFernアンサンブル学習},
author = {熊澤 峻悟 and 川村 一志 and Thiem Van Chu and 本村 真人 and 劉載勲},
year = {2021},
date = {2021-05-10},
address = {LSIとシステムとワークショップ},
keywords = {Domestic Conference},
pubstate = {published},
tppubtype = {techreport}
}
@techreport{suzuki-reconf-2021,
title = {対称二進表現に基づくビットスケーラブルCNN推論手法},
author = {鈴木 淳之介 and 安藤 洸太 and 廣瀬 一俊 and 川村 一志 and Thiem Van Chu and 本村 真人 and 劉載勲},
year = {2021},
date = {2021-06-08},
address = {電子情報通信学会リコンフィギャラブルシステム研究会 (RECONF)},
keywords = {Domestic Conference},
pubstate = {published},
tppubtype = {techreport}
}
@inproceedings{ieee-cs-award-2022,
title = {[IEEE CS Tokyo/Japan Joint Local Chapters Young Author Award 2022] SeedEx: A Genome Sequencing Accelerator for Optimal Alignments in Subminimal Space},
author = {Daichi Fujiki and Shunhao Wu and Nathan Ozog and Kush Goliya and David T. Blaauw and Satish Narayanasamy and Reetuparna Das},
year = {2020},
date = {2020-10-22},
urldate = {2020-10-22},
booktitle = {International Symposium on Microarchitecture (MICRO)},
keywords = {Awards, International Conference},
pubstate = {published},
tppubtype = {inproceedings}
}
[Invited] Designing AI Accelerator Chips for the Smarter Future
@misc{motomura-icta2020,
title = {[Invited] Designing AI Accelerator Chips for the Smarter Future},
author = {Masato Motomura},
year = {2020},
date = {2020-11-23},
address = {IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)},
keywords = {Invited Talks},
pubstate = {published},
tppubtype = {presentation}
}
[Invited] Domain-Specific Architectures for Boosting “Compute for Intelligence”
@misc{motomura-nus2020,
title = {[Invited] Stochastic Cellular Automata Annealing (SCA) and its Non-Quantum Silicon Chip Implementation},
author = {Masato Motomura},
year = {2020},
date = {2020-11-10},
address = {Seminar at National University of Singapore},
keywords = {Invited Talks},
pubstate = {published},
tppubtype = {presentation}
}
[Invited] Stochastic Cellular Automata Annealing (SCA) and its Non-Quantum Silicon Chip Implementation: Realizing Fully-Parallel Spin-Updates for Fully-Connected Spin Systems
@inproceedings{shiba-iscas2020,
title = {A 3D-Stacked SRAM Using Inductive Coupling with Low-Voltage Transmitter and 12:1 SerDes},
author = {Kota Shiba and Tatsuo Omori and Kodai Ueyoshi and Kota Ando and Kazutoshi Hirose and Shinya Takamaeda-Yamazaki and Masato Motomura and Mototsugu Hamada and Tadahiro Kuroda},
year = {2020},
date = {2020-10-10},
booktitle = {IEEE International Symposium on Circuits and Systems (ISCAS)},
pages = {1-5},
keywords = {International Conference},
pubstate = {published},
tppubtype = {inproceedings}
}
A Hardware-Efficient Weight Sampling Circuit for Bayesian Neural Networks
@inproceedings{reca-lopez-iscas2020,
title = {Low-Cost Reservoir Computing using Cellular Automata and Random Forests},
author = {Ángel López García-Arias and Jaehoon Yu and Masanori Hashimoto},
year = {2020},
date = {2020-10-10},
booktitle = {IEEE International Symposium on Circuits and Systems (ISCAS)},
pages = {1-5},
keywords = {International Conference},
pubstate = {published},
tppubtype = {inproceedings}
}
Memory Efficient Training using Lookup-Table-based Quantization for Neural Network
Kazuki Onishi, Jaehoon Yu, Masanori Hashimoto
IEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS),2020
@inproceedings{onishi2020memory,
title = {Memory Efficient Training using Lookup-Table-based Quantization for Neural Network},
author = {Kazuki Onishi and Jaehoon Yu and Masanori Hashimoto},
year = {2020},
date = {2020-09-04},
booktitle = {IEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS)},
pages = {251--255},
organization = {IEEE},
keywords = {International Conference},
pubstate = {published},
tppubtype = {inproceedings}
}
Novel Annealing Processor Is the Best Ever at Solving Combinatorial Optimization Problems
@inproceedings{suzuki-candar2020,
title = {ProgressiveNN: Achieving Computational Scalability without Network Alteration by MSB-first Accumulative Computation},
author = {Junnosuke Suzuki and Kota Ando and Kazutoshi Hirose and Kazushi Kawamura and Thiem Van Chu and Masato Motomura and Jaehoon Yu},
year = {2020},
date = {2020-11-24},
booktitle = {International Symposium on Computing and Networking (CANDAR)},
keywords = {International Conference},
pubstate = {published},
tppubtype = {inproceedings}
}
@article{Motomura-TCSVT-2020,
title = {Real-time Tone Mapping: A State of the Art Report},
author = {Yafei Ou and Prasoon Ambalathankandy and Masayuki Ikebe and Shinya Takamaeda and Masato Motomura and Tetsuya Asai},
year = {2020},
date = {2020-01-01},
journal = {IEEE Transactions on Circuits and Systems for Video Technology},
keywords = {Journal Papers},
pubstate = {published},
tppubtype = {article}
}
Selective Fine-Tuning on a Classifier Ensemble: Realizing Adaptive Neural Networks With a Diversified Multi-Exit Architecture
@article{hirose-ieee-access-2020,
title = {Selective Fine-Tuning on a Classifier Ensemble: Realizing Adaptive Neural Networks With a Diversified Multi-Exit Architecture},
author = {Kazutoshi Hirose and Shinya Takamaeda-Yamazaki and Jaehoon Yu and Masato Motomura},
year = {2020},
date = {2020-12-28},
journal = {IEEE Access},
volume = {9},
pages = {6179-6187},
keywords = {Journal Papers},
pubstate = {published},
tppubtype = {article}
}
STATICA: A 512-Spin 0.25M-Weight Annealing Processor With an All-Spin-Updates-at-Once Architecture for Combinatorial Optimization With Complete Spin-Spin Interactions
@article{statica-jssc,
title = {STATICA: A 512-Spin 0.25M-Weight Annealing Processor With an All-Spin-Updates-at-Once Architecture for Combinatorial Optimization With Complete Spin-Spin Interactions},
author = {Kasho Yamamoto and Kazushi Kawamura and Kota Ando and Normann Mertig and Takashi Takemoto and Masanao Yamaoka and Hiroshi Teramoto and Akira Sakai and Shinya Takamaeda-Yamazaki and Masato Motomura},
year = {2020},
date = {2020-10-13},
journal = {IEEE Journal of Solid-State Circuits (JSSC)},
keywords = {Journal Papers},
pubstate = {published},
tppubtype = {article}
}
STATICA: A 512-Spin 0.25M-Weight Full-Digital Annealing Processor with a Near-Memory All-Spin-Updates-at-Once Architecture for Combinatorial Optimization with Complete Spin-Spin Interactions
@inproceedings{statica,
title = {STATICA: A 512-Spin 0.25M-Weight Full-Digital Annealing Processor with a Near-Memory All-Spin-Updates-at-Once Architecture for Combinatorial Optimization with Complete Spin-Spin Interactions},
author = {Kasho Yamamoto and Kota Ando and Normann Mertig and Takashi Takemoto and Masanao Yamaoka and Hiroshi Teramoto and Akira Sakai and Shinya Takamaeda-Yamazaki and Masato Motomura},
year = {2020},
date = {2020-02-17},
booktitle = {International Solid-State Circuits Conference (ISSCC)},
pages = {138--139},
keywords = {International Conference},
pubstate = {published},
tppubtype = {inproceedings}
}
Via-Switch FPGA: 65nm CMOS Implementation and Architecture Extension for AI Applications
@inproceedings{id529,
title = {Via-Switch FPGA: 65nm CMOS Implementation and Architecture Extension for AI Applications},
author = {Masanori Hashimoto and Xu Bai and Naoki Banno and Munehiro Tada and Toshitsugu Sakamoto and Jaehoon Yu and Ryutaro Doi and Yusuke Araki and Hidetoshi Onodera and Takashi Imagawa and Hiroyuki Ochi and Kazutoshi Wakabayashi and Yukio Mitsuyama and Tadahiko Sugibayashi},
year = {2020},
date = {2020-02-17},
booktitle = {International Solid-State Circuits Conference (ISSCC)},
pages = {502--503},
keywords = {International Conference},
pubstate = {published},
tppubtype = {inproceedings}
}
深層ニューラルネットワーク向けプロセッサ技術の実例と展望
Masato Motomura, 高前田 伸也, 植吉 晃大, Kota Ando, Kazutoshi Hirose
@misc{motomura_00041,
title = {[Invited] AI Computing: The Promised Land for Hardware?},
author = {Masato Motomura},
year = {2019},
date = {2019-03-01},
address = {Multimedia Workshop, Tokyo, Japan},
keywords = {Invited Talks},
pubstate = {published},
tppubtype = {presentation}
}
@misc{Motomura-A-SSCC-2019,
title = {[Tutorial] AI Computing: What it is about & How hardware can help it out},
author = {Masato Motomura},
year = {2019},
date = {2019-11-14},
address = {Asian Solid-State Circuit Conference (A-SSCC), Macau, SAR, China},
keywords = {Invited Talks},
pubstate = {published},
tppubtype = {presentation}
}
@article{motomura_00004,
title = {A Study on a Low Power Optimization Algorithm for An Edge-AI Device},
author = {Tatsuya Kaneko and Kentaro Orimo and Itaru Hida and Shinya Takamaeda-Yamazaki and Masayuki Ikebe and Masato Motomura and Tetsuya Asai},
year = {2019},
date = {2019-10-01},
journal = {Nonlinear Theory and Its Applications},
volume = {E10-N},
number = {4},
keywords = {Journal Papers},
pubstate = {published},
tppubtype = {article}
}
@article{motomura_00001,
title = {An Adaptive Global and Local Tone Mapping Algorithm Implemented on FPGA},
author = {Prasoon Ambalathankandy and Masayuki Ikebe and Takashi Yoshida and Takeshi Shimada and Shinya Takamaeda-Yamazaki and Masato Motomura and Tetsuya Asai},
year = {2019},
date = {2019-12-01},
journal = {IEEE Transactions on Circuits and Systems for Video Technology},
volume = {29},
keywords = {Journal Papers},
pubstate = {published},
tppubtype = {article}
}
Approach to Reservoir Computing with Schmitt Trigger Oscillator-Based Analog Neural Circuits
@inproceedings{motomura_00049,
title = {Approach to Reservoir Computing with Schmitt Trigger Oscillator-Based Analog Neural Circuits},
author = {Seunggoo Rim and Shunya Suzuki and Shinya Takamaeda-Yamazaki and Masayuki Ikebe and Masato Motomura and Tetsuya Asai},
year = {2019},
date = {2019-01-01},
booktitle = {Japan-Korea Joint Workshop on Complex Communication Sciences},
address = {Pyengonchang, Korea},
keywords = {International Conference},
pubstate = {published},
tppubtype = {inproceedings}
}
DeltaNet: Differential Binary Neural Network
Yuka Oba, Kota Ando, Tetsuya Asai, Masato Motomura, Shinya Takamaeda-Yamazaki
IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP),2019
@inproceedings{motomura_00039b,
title = {DeltaNet: Differential Binary Neural Network},
author = {Yuka Oba and Kota Ando and Tetsuya Asai and Masato Motomura and Shinya Takamaeda-Yamazaki},
year = {2019},
date = {2019-07-01},
booktitle = {IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP)},
address = {New York, USA},
keywords = {International Conference},
pubstate = {published},
tppubtype = {inproceedings}
}
Distilling Knowledge for Non-Neural Networks
Shota Fukui, Jaehoon Yu, Masanori Hashimoto
Asia-Pacific Signal and Information Processing Association (APSIPA),2019
@inproceedings{2019-11-Fukui-APSIPA,
title = {Distilling Knowledge for Non-Neural Networks},
author = {Shota Fukui and Jaehoon Yu and Masanori Hashimoto},
year = {2019},
date = {2019-11-01},
booktitle = {Asia-Pacific Signal and Information Processing Association (APSIPA)},
keywords = {International Conference},
pubstate = {published},
tppubtype = {inproceedings}
}
Dither NN: Hardware/Algorithm Co-Design for Accurate Quantized Neural Networks
@article{motomura_00003,
title = {Dither NN: Hardware/Algorithm Co-Design for Accurate Quantized Neural Networks},
author = {Kota Ando and Kodai Ueyoshi and Yuka Oba and Kazutoshi Hirose and Ryota Uematsu and Takumi Kudo and Masayuki Ikebe and Tetsuya Asai and Shinya Takamaeda-Yamazaki and Masato Motomura},
year = {2019},
date = {2019-12-01},
journal = {IEICE Transactions on Information and Systems},
volume = {E102},
keywords = {Journal Papers},
pubstate = {published},
tppubtype = {article}
}
Experimental Demonstration of Physical Reservoir Computing with Nonlinear Electronic Devices
@inproceedings{motomura_00045b,
title = {Experimental Demonstration of Physical Reservoir Computing with Nonlinear Electronic Devices},
author = {Shunya Suzuki and Seunggoo Rim and Shinya Takamaeda-Yamazaki and Masayuki Ikebe and Masato Motomura and Tetsuya Asai},
year = {2019},
date = {2019-03-01},
booktitle = {RISP International Workshop on Nonlinear Circuits, Communications and Signal Processing},
address = {Honolulu, USA},
keywords = {International Conference},
pubstate = {published},
tppubtype = {inproceedings}
}
FPGA-Based Annealing Processor with Time-Division Multiplexing
@article{motomura_00002,
title = {FPGA-Based Annealing Processor with Time-Division Multiplexing},
author = {Kasho Yamamoto and Masayuki Ikebe and Tetsuya Asai and Masato Motomura and Shinya Takamaeda-Yamazaki},
year = {2019},
date = {2019-12-01},
journal = {IEICE Transactions on Information and Systems},
volume = {E102},
keywords = {Journal Papers},
pubstate = {published},
tppubtype = {article}
}
FPGA-Based FORCE Learning Accelerator towards Real-Time Online Reservoir Computing
@inproceedings{motomura_00046b,
title = {FPGA-Based FORCE Learning Accelerator towards Real-Time Online Reservoir Computing},
author = {Koyo Minamikawa and Shinya Takamaeda-Yamazaki and Masayuki Ikebe and Masato Motomura and Tetsuya Asai},
year = {2019},
date = {2019-03-01},
booktitle = {RISP International Workshop on Nonlinear Circuits, Communications and Signal Processing},
address = {Honolulu, USA},
keywords = {International Conference},
pubstate = {published},
tppubtype = {inproceedings}
}
Hardware-Oriented Algorithm and Architecture for Generative Adversarial Networks
@article{motomura_00005,
title = {Hardware-Oriented Algorithm and Architecture for Generative Adversarial Networks},
author = {Tatsuya Kaneko and Masayuki Ikebe and Shinya Takamaeda-Yamazaki and Masato Motomura and Tetsuya Asai},
year = {2019},
date = {2019-07-01},
journal = {Journal of Signal Processing},
volume = {23},
number = {4},
pages = {151-154},
keywords = {Journal Papers},
pubstate = {published},
tppubtype = {article}
}
Hardware-Oriented Algorithm and Architecture for Generative Adversarial Networks
@inproceedings{motomura_00044b,
title = {Hardware-Oriented Algorithm and Architecture for Generative Adversarial Networks},
author = {Tatsuya Kaneko and Masayuki Ikebe and Shinya Takamaeda-Yamazaki and Masato Motomura and Tetsuya Asai},
year = {2019},
date = {2019-03-01},
booktitle = {RISP International Workshop on Nonlinear Circuits, Communications and Signal Processing},
address = {Honolulu, USA},
keywords = {International Conference},
pubstate = {published},
tppubtype = {inproceedings}
}
LEF: An Effective Routing Algorithm for Two-Dimensional Meshes
Thiem Van Chu, Kenji Kise
IEICE Transactions on Information and Systems,2019
@article{thiem-ieice2019,
title = {LEF: An Effective Routing Algorithm for Two-Dimensional Meshes},
author = {Thiem Van Chu and Kenji Kise},
year = {2019},
date = {2019-01-01},
journal = {IEICE Transactions on Information and Systems},
volume = {E102-D},
number = {10},
pages = {1925--1941},
keywords = {Journal Papers},
pubstate = {published},
tppubtype = {article}
}
Minimizing Energy for Neural Network Training with Logarithm-Approximate Floating-Point Multiplier
Tai-Yu Cheng, Jaehoon Yu, Masanori Hashimoto
International Symposium on Power and Timing Modeling, Optimization and Simulation,2019
@inproceedings{cheng-patmos-2019,
title = {Minimizing Energy for Neural Network Training with Logarithm-Approximate Floating-Point Multiplier},
author = {Tai-Yu Cheng and Jaehoon Yu and Masanori Hashimoto},
year = {2019},
date = {2019-01-01},
booktitle = {International Symposium on Power and Timing Modeling, Optimization and Simulation},
pages = {91--96},
keywords = {},
pubstate = {published},
tppubtype = {inproceedings}
}
Parallelism-Flexible Convolution Core for Sparse Convolutional Neural Networks on FPGA
@inproceedings{Motomura-DICTA-2019,
title = {Radiography Contrast Enhancement: Smoothed LHE Filter, a Practical Solution for Digital X-rays with Mach Band},
author = {Prasoon Ambalathankandy and Yafei Ou and Jyotsna Kochiyil and Shinya Takamaeda-Yamazaki and Masato Motomura and Tetsuya Asai and Masayuki Ikebe},
year = {2019},
date = {2019-12-02},
booktitle = {International Conference on Digital Image Computing: Techniques and Applications},
address = {University of Western Australia, Perth, Australia},
keywords = {International Conference},
pubstate = {published},
tppubtype = {inproceedings}
}
Sneak Path Free Reconfiguration with Minimized Programming Steps for Via-switch Crossbar Based FPGA
Ryutaro Doi, Jaehoon Yu, Masanori Hashimoto
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems,2019
@inproceedings{motomura_00047,
title = {Ternarized Backpropagation: A Hardware-Oriented Optimization Algorithm for Edge-Oriented AI Devices},
author = {Tatsuya Kaneko and Masayuki Ikebe and Shinya Takamaeda-Yamazaki and Masato Motomura and Tetsuya Asai},
year = {2019},
date = {2019-02-01},
booktitle = {RIEC International Symposium on Brain Functions and Brain Computer},
address = {Sendai, Japan},
keywords = {International Conference},
pubstate = {published},
tppubtype = {inproceedings}
}
Training Data Reduction using Support Vectors for Neural Networks
@inproceedings{2019-11-Tanio-APSIPA,
title = {Training Data Reduction using Support Vectors for Neural Networks},
author = {Toranosuke Tanio and Kouya Takeda and Jaehoon Yu and Masanori Hashimoto},
year = {2019},
date = {2019-11-01},
booktitle = {Asia-Pacific Signal and Information Processing Association (APSIPA)},
keywords = {International Conference},
pubstate = {published},
tppubtype = {inproceedings}
}
@inproceedings{nocs-2018,
title = {[Best Paper Nomination] AxNoC: Low-power Approximate Network-on-Chips using Critical-Path Isolation},
author = {Akram Ben Ahmed and Daichi Fujiki and Hiroki Matsutani and Michihiro Koibuchi and Hideharu Amano},
year = {2018},
date = {2018-10-04},
booktitle = {International Symposium on Networks-on-Chip (NOCS)},
keywords = {Awards, International Conference},
pubstate = {published},
tppubtype = {inproceedings}
}
[Invited] Hardware-Oriented Approaches for Accelerating “AI” Workloads
@inproceedings{motomura_00057,
title = {A Study on Ternary Back Propagation Algorithm for Embedded Egde-AI Processing},
author = {Tatsuya Kaneko and Masayuki Ikebe and Shinya Takamaeda-Yamazaki and Masato Motomura and Tetsuya Asai},
year = {2018},
date = {2018-10-01},
booktitle = {Joint Workshop of UCL-ICN, NTT, UCL-Gatsby and AIBS: Analysis and Synthesis for Human/Artificial Cognition and Behaviour},
address = {Okinawa, Japan},
keywords = {International Conference},
pubstate = {published},
tppubtype = {inproceedings}
}
Adapting Soft Cascade to MAC Operations of Convolutional Neural Networks
Kenshi Ito, Jaehoon Yu, Masanori Hashimoto
International Symposium on Multimedia and Communication Technology,2018
@inproceedings{ito2018adapting,
title = {Adapting Soft Cascade to MAC Operations of Convolutional Neural Networks},
author = {Kenshi Ito and Jaehoon Yu and Masanori Hashimoto},
year = {2018},
date = {2018-01-01},
booktitle = {International Symposium on Multimedia and Communication Technology},
pages = {101--104},
keywords = {International Conference},
pubstate = {published},
tppubtype = {inproceedings}
}
Analysis of Smoothed LHE Methods for Processing Images with Optical Illusions
@inproceedings{motomura_00052,
title = {Analysis of Smoothed LHE Methods for Processing Images with Optical Illusions},
author = {Prasoon Ambalathankandy and Takeshi Shimada and Shinya Takamaeda-Yamazaki and Masato Motomura and Tetsuya Asai and Masayuki Ikebe},
year = {2018},
date = {2018-12-01},
booktitle = {IEEE International Conference on Visual Communications and Image Processing},
address = {Taichung, Taiwan},
keywords = {International Conference},
pubstate = {published},
tppubtype = {inproceedings}
}
Area and Energy Optimization for Bit-Serial Log-Quantized DNN Accelerator with Shared Accumulators
@inproceedings{motomura_00061,
title = {Area and Energy Optimization for Bit-Serial Log-Quantized DNN Accelerator with Shared Accumulators},
author = {Takumi Kudo and Kodai Ueyoshi and Kota Ando and Kazutoshi Hirose and Ryota Uematsu and Yuka Oba and Masayuki Ikebe and Tetsuya Asai and Masato Motomura and Shinya Takamaeda-Yamazaki},
year = {2018},
date = {2018-09-01},
booktitle = {IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip},
address = {Hanoi, Vietnam},
keywords = {International Conference},
pubstate = {published},
tppubtype = {inproceedings}
}
BRein Memory: A Single-Chip Binary/Ternary Reconfigurable In-Memory Deep Neural Network Accelerator Achieving 1.4TOPS at 0.6W
@article{motomura_00009,
title = {BRein Memory: A Single-Chip Binary/Ternary Reconfigurable In-Memory Deep Neural Network Accelerator Achieving 1.4TOPS at 0.6W},
author = {Kota Ando and Kodai Ueyoshi and Kentaro Orimo and Haruyoshi Yonekawa and Shimpei Sato and Hiroki Nakahara and Shinya Takamaeda-Yamazaki and Masayuki Ikebe and Tetsuya Asai and Tadahiro Kuroda and Masato Motomura},
year = {2018},
date = {2018-04-01},
journal = {IEEE Journal of Solid-State Circuits},
volume = {53},
number = {4},
pages = {983-994},
keywords = {Journal Papers},
pubstate = {published},
tppubtype = {article}
}
Decomposed Vector Histograms of Oriented Gradients for Efficient Hardware Implementation
@inproceedings{motomura_00050,
title = {Dither NN: An Accurate Neural Network with Dithering for Low Bit-Precision Hardware},
author = {Kota Ando and Kodai Ueyoshi and Yuka Oba and Kazutoshi Hirose and Ryota Uematsu and Takumi Kudo and Masayuki Ikebe and Tetsuya Asai and Shinya Takamaeda-Yamazaki and Masato Motomura},
year = {2018},
date = {2018-12-01},
booktitle = {International Conference on Field-Programmable Technology (FPT)},
address = {Naha, Japan},
keywords = {International Conference},
pubstate = {published},
tppubtype = {inproceedings}
}
Exploring CNN Accelerator Design Space on a Dynamically Reconfigurable Hardware Platform
@inproceedings{motomura_00072,
title = {Exploring CNN Accelerator Design Space on a Dynamically Reconfigurable Hardware Platform},
author = {Ryota Uematsu and Kota Ando and Kodai Ueyoshi and Kazutoshi Hirose and Masayuki Ikebe and Tetsuya Asai and Shinya Takamaeda-Yamazaki and Masato Motomura},
year = {2018},
date = {2018-03-01},
booktitle = {Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI)},
address = {Matsue, Japan},
keywords = {International Conference},
pubstate = {published},
tppubtype = {inproceedings}
}
Hardware Architecture for Fast General Object Detection Using Aggregated Channel Features
@inproceedings{mitsunari2018hardware-asscc,
title = {Hardware Architecture for Fast General Object Detection Using Aggregated Channel Features},
author = {Koichi Mitsunari and Jaehoon Yu and Masanori Hashimoto},
year = {2018},
date = {2018-01-01},
pages = {55-58},
keywords = {International Conference},
pubstate = {published},
tppubtype = {inproceedings}
}
Hardware Architecture for High-Speed Object Detection Using Decision Tree Ensemble
@inproceedings{hashimoto2018interconnect,
title = {Interconnect Delay Analysis for RRAM Crossbar Based FPGA},
author = {Masanori Hashimoto and Yuki Nakazawa and Ryutaro Doi and Jaehoon Yu},
year = {2018},
date = {2018-01-01},
pages = {522--527},
keywords = {International Conference},
pubstate = {published},
tppubtype = {inproceedings}
}
New Generation Dynamically Reconfigurable Processor Technology for Accelerating Embedded AI Applications
@inproceedings{motomura_00062,
title = {New Generation Dynamically Reconfigurable Processor Technology for Accelerating Embedded AI Applications},
author = {Taro Fujii and Takao Toi and Teruhito Tanaka and Katsumi Togawa and Toshiro Kitaoka and Kengo Nishino and Noritsugu Nakamura and Hiroki Nakahara and Masato Motomura},
year = {2018},
date = {2018-06-01},
booktitle = {Symposia on VLSI Technology and Circuits},
address = {Hawaii, USA},
keywords = {International Conference},
pubstate = {published},
tppubtype = {inproceedings}
}
Phase Locking Value Calculator based on Hardware-oriented Mathematical Expression
@article{motomura_00010,
title = {Proto-Computing Architecture over A Digital Medium Aiming at Real-Time Video Processing},
author = {Aoi Tanibata and Alexandre Schmid and Shinya Takamaeda-Yamazaki and Masayuki Ikebe and Masato Motomura and Tetsuya Asai},
year = {2018},
date = {2018-02-01},
journal = {Complexity},
volume = {2018},
pages = {3618621-1-11},
keywords = {Journal Papers},
pubstate = {published},
tppubtype = {article}
}
Quantization Error-Based Regularization for Hardware-Aware Neural Network Training
@article{motomura_00008,
title = {Quantization Error-Based Regularization for Hardware-Aware Neural Network Training},
author = {Kazutoshi Hirose and Ryota Uematsu and Kota Ando and Kodai Ueyoshi and Masayuki Ikebe and Tetsuya Asai and Masato Motomura and Shinya Takamaeda-Yamazaki},
year = {2018},
date = {2018-10-01},
journal = {Nonlinear Theory and Its Applications},
volume = {E9-N},
number = {4},
pages = {453-465},
keywords = {Journal Papers},
pubstate = {published},
tppubtype = {article}
}
QUEST: A 7.49-TOPS Multi-Purpose Log-Quantized DNN Inference Engine Stacked on 96MB 3D SRAM using Inductive-Coupling Technology in 40nm CMOS
@inproceedings{motomura_00076,
title = {QUEST: A 7.49-TOPS Multi-Purpose Log-Quantized DNN Inference Engine Stacked on 96MB 3D SRAM using Inductive-Coupling Technology in 40nm CMOS},
author = {Kodai Ueyoshi and Kota Ando and Kazutoshi Hirose and Shinya Takamaeda-Yamazaki and Junichiro Kadomoto and Tomoki Miyata and Mototsugu Hamada and Tadahiro Kuroda and Masato Motomura},
year = {2018},
date = {2018-02-01},
booktitle = {International Solid-State Circuits Conference (ISSCC 2018)},
address = {San Francisco, US},
keywords = {International Conference},
pubstate = {published},
tppubtype = {inproceedings}
}
Real-time HDTV to 4K and 8K-UHD Conversions Using Anti-Aliasing Based Super Resolution Algorithm on FPGA
@article{motomura_00007,
title = {Real-time HDTV to 4K and 8K-UHD Conversions Using Anti-Aliasing Based Super Resolution Algorithm on FPGA},
author = {Prasoon Ambalathankandy and Shinya Takamaeda-Yamazaki and Masato Motomura and Tetsuya Asai and Masayuki Ikebe and Hotaka Kusano},
year = {2018},
date = {2018-12-01},
journal = {Microprocessors and Microsystems},
volume = {60},
keywords = {Journal Papers},
pubstate = {published},
tppubtype = {article}
}
Sneak Path Free Reconfiguration of Via-switch Crossbars Based FPGA
@inproceedings{motomura_00071,
title = {Sparse Disparity Estimation Using Global Phase Only Correlation for Stereo Matching Acceleration},
author = {Takeshi Shimada and Masayuki Ikebe and Prasoon Ambalathankandy and Shinya Takamaeda-Yamazaki and Masato Motomura and Tetsuya Asai},
year = {2018},
date = {2018-04-01},
booktitle = {IEEE International Conference on Acoustics, Speech and Signal Processing},
address = {Alberta, Canada},
keywords = {International Conference},
pubstate = {published},
tppubtype = {inproceedings}
}
@article{ochi2018via,
title = {Via-Switch FPGA: Highly Dense Mixed-Grained Reconfigurable Architecture with Overlay Via-Switch Crossbars},
author = {Hiroyuki Ochi and Kosei Yamaguchi and Tetsuaki Fujimoto and Junshi Hotate and Takashi Kishimoto and Toshiki Higashi and Takashi Imagawa and Ryutaro Doi and Munehiro Tada and Tadahiko Sugibayashi and Wataru Takahashi and Kazutoshi Wakabayashi and Hidetoshi Onodera and Yukio Mitsuyama and Jaehoon Yu and Masanori Hashimoto},
year = {2018},
date = {2018-01-01},
number = {99},
pages = {1--14},
note = {(IF: 1.744, 被引用件数: 3)},
keywords = {Journal Papers},
pubstate = {published},
tppubtype = {article}
}
@article{motomura_00011,
title = {6-DoF Camera Position and Posture Estimation Based on Local Patches of Image Sequence},
author = {Takuto Tsuji and Masayuki Ikebe and Shinya Takamaeda-Yamazaki and Masato Motomura and Tetsuya Asai},
year = {2017},
date = {2017-07-01},
journal = {Journal of Signal Processing},
volume = {21},
number = {4},
pages = {191-194},
keywords = {Journal Papers},
pubstate = {published},
tppubtype = {article}
}
6-DoF Camera-Position and Posture Estimation Based on Local Patches of Image Sequence
@inproceedings{motomura_00130,
title = {6-DoF Camera-Position and Posture Estimation Based on Local Patches of Image Sequence},
author = {Takuto Tsuji and Masayuki Ikebe and Shinya Takamaeda-Yamazaki and Masato Motomura and Tetsuya Asai},
year = {2017},
date = {2017-02-01},
booktitle = {RISP International Workshop on Nonlinear Circuits, Communications and Signal Processing},
address = {Guam, USA},
keywords = {International Conference},
pubstate = {published},
tppubtype = {inproceedings}
}
A Batch Normalization Free Binarized Convolutional Deep Neural Network on an FPGA
@article{motomura_00014,
title = {A High Performance and Energy Efficient Microprocessor with a Novel Restricted Dynamically Reconfigurable Accelerator},
author = {Itaru Hida and Shinya Takamaeda-Yamazaki and Masayuki Ikebe and Masato Motomura and Tetsuya Asai},
year = {2017},
date = {2017-05-01},
journal = {Circuits and Systems},
volume = {8},
number = {5},
pages = {134-147},
keywords = {Journal Papers},
pubstate = {published},
tppubtype = {article}
}
A Low-Energy Application Specific Instruction-Set Processor towards a Low-Computational Lossless Compression Method for Stimuli Position Data of Artificial Vision Systems
@article{sugiura2017low,
title = {A Low-Energy Application Specific Instruction-Set Processor towards a Low-Computational Lossless Compression Method for Stimuli Position Data of Artificial Vision Systems},
author = {Tomoki Sugiura and Masaharu Imai and Jaehoon Yu and Yoshinori Takeuchi},
year = {2017},
date = {2017-01-01},
volume = {25},
pages = {210--219},
note = {(IF: 0.77, 被引用件数: 2)},
keywords = {Journal Papers},
pubstate = {published},
tppubtype = {article}
}
A Multithreaded CGRA for Convolutional Neural Network Processing
Kota Ando, Shinya Takamaeda-Yamazaki, Masayuki Ikebe, Tetsuya Asai, Masato Motomura
@inproceedings{ando_00015,
title = {Accelerating Deep Learning by Binarized Hardware},
author = {Shinya Takamaeda-Yamazaki and Kodai Ueyoshi and Kota Ando and Ryota Uematsu and Kazutoshi Hirose and Masayuki Ikebe and Tetsuya Asai and Masato Motomura},
year = {2017},
date = {2017-12-01},
booktitle = {Asia-Pacific Signal and Information Processing Association Annual Summit and Conference (APSIPA ASC)},
address = {Kuala Lumpur, Malaysia},
keywords = {International Conference},
pubstate = {published},
tppubtype = {inproceedings}
}
An Energy-Efficient Dynamic Branch Predictor with a Two-Clock-Cycle Naive Bayes Classifier for Pipelined RISC Microprocessors
@article{motomura_00013,
title = {An Energy-Efficient Dynamic Branch Predictor with a Two-Clock-Cycle Naive Bayes Classifier for Pipelined RISC Microprocessors},
author = {Itaru Hida and Shinya Takamaeda-Yamazaki and Masayuki Ikebe and Masato Motomura and Tetsuya Asai},
year = {2017},
date = {2017-05-01},
journal = {Nonlinear Theory and Its Applications},
volume = {E8-N},
number = {3},
pages = {235-245},
keywords = {Journal Papers},
pubstate = {published},
tppubtype = {article}
}
An FPGA Realization of a Deep Convolutional Neural Network Using A Threshold Neuron Pruning
@inproceedings{motomura_00124,
title = {An FPGA Realization of a Deep Convolutional Neural Network Using A Threshold Neuron Pruning},
author = {Tomoya Fujii and Shimpei Sato and Hiroki Nakahara and Masato Motomura},
year = {2017},
date = {2017-04-01},
booktitle = {International Symposium on Applied Reconfigurable Computing (ARC)},
address = {Delft, Netherlands},
keywords = {International Conference},
pubstate = {published},
tppubtype = {inproceedings}
}
BRein Memory: A 13-Layer 4.2 K Neuron/0.8 M Synapse Binary/Ternary Reconfigurable In-Memory Deep Neural Network Accelerator in 65 nm CMOS
@inproceedings{ando_00022,
title = {BRein Memory: A 13-Layer 4.2 K Neuron/0.8 M Synapse Binary/Ternary Reconfigurable In-Memory Deep Neural Network Accelerator in 65 nm CMOS},
author = {Kota Ando and Kodai Ueyoshi and Kentaro Orimo and Haruyoshi Yonekawa and Shimpei Sato and Hiroki Nakahara and Masayuki Ikebe and Tetsuya Asai and Shinya Takamaeda-Yamazaki and Tadahiro Kuroda and Masato Motomura},
year = {2017},
date = {2017-06-01},
booktitle = {Symposia on VLSI Technology and Circuits},
address = {Kyoto, Japan},
keywords = {International Conference},
pubstate = {published},
tppubtype = {inproceedings}
}
Deformable Part Model Based Arrhythmia Detection Using Time Domain Features
@article{hirao2017deformable,
title = {Deformable Part Model Based Arrhythmia Detection Using Time Domain Features},
author = {Yuuka Hirao and Yoshinori Takeuchi and Masaharu Imai and Jaehoon Yu},
year = {2017},
date = {2017-01-01},
journal = {IEICE_J_FECACS},
volume = {100},
number = {11},
pages = {2221--2229},
keywords = {Journal Papers},
pubstate = {published},
tppubtype = {article}
}
Error Tolerance Analysis of Deep Learning Hardware Using Restricted Boltzmann Machine towards Low-Power Memory Implementation
@article{motomura_00015,
title = {Error Tolerance Analysis of Deep Learning Hardware Using Restricted Boltzmann Machine towards Low-Power Memory Implementation},
author = {Takao Marukame and Kodai Ueyoshi and Tetsuya Asai and Masato Motomura and Alexandre Schmid and Masamichi Suzuki and Yusuke Higashi and Yuichiro Mitani},
year = {2017},
date = {2017-04-01},
journal = {IEEE Transactions on Circuits and Systems II},
volume = {64},
number = {4},
pages = {462-466},
keywords = {Journal Papers},
pubstate = {published},
tppubtype = {article}
}
Exploring Optimized Accelerator Design for Binarized Convolutional Neural Networks
@article{thiem-acmtrets2017,
title = {Fast and Cycle-Accurate Emulation of Large-Scale Networks-on-Chip Using a Single FPGA},
author = {Thiem Van Chu and Shimpei Sato and Kenji Kise},
year = {2017},
date = {2017-01-01},
journal = {ACM Transactions on Reconfigurable Technology and Systems (TRETS)},
volume = {10},
number = {4},
pages = {27:1--27:27},
keywords = {Journal Papers},
pubstate = {published},
tppubtype = {article}
}
Feature Extraction System Using Restricted Boltzmann Machines on FPGA
@inproceedings{motomura_00110,
title = {Feature Extraction System Using Restricted Boltzmann Machines on FPGA},
author = {Kodai Ueyoshi and Takao Marukame and Tetsuya Asai and Masato Motomura and Alexandre Schmid},
year = {2017},
date = {2017-05-01},
booktitle = {IEEE International Symposium on Circuits & Systems},
address = {Baltimore, USA},
keywords = {International Conference},
pubstate = {published},
tppubtype = {inproceedings}
}
FPGA Implementation of Edge-Guided Pattern Generation for Motion-Vector Estimation of Textureless Objects (Demo Night)
@inproceedings{ando_00020,
title = {In-Memory Area-Efficient Signal Streaming Processor Design for Binary Neural Networks},
author = {Kota Ando and Kodai Ueyoshi and Kazutoshi Hirose and Kentaro Orimo and Haruyoshi Yonekawa and Shimpei Sato and Hiroki Nakahara and Masayuki Ikebe and Shinya Takamaeda-Yamazaki and Tetsuya Asai and Tadahiro Kuroda and Masato Motomura},
year = {2017},
date = {2017-08-01},
booktitle = {IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)},
address = {Boston, USA},
keywords = {International Conference},
pubstate = {published},
tppubtype = {inproceedings}
}
Logarithmic Compression for Memory Footprint Reduction in Neural Network Training
@inproceedings{ando_00017,
title = {Logarithmic Compression for Memory Footprint Reduction in Neural Network Training},
author = {Kazutoshi Hirose and Ryota Uematsu and Kota Ando and Kentaro Orimo and Kodai Ueyoshi and Masayuki Ikebe and Tetsuya Asai and Shinya Takamaeda-Yamazaki and Masato Motomura},
year = {2017},
date = {2017-11-01},
booktitle = {International Workshop on Computer Systems and Architectures (CSA)},
address = {Aomori, Japan},
keywords = {International Conference},
pubstate = {published},
tppubtype = {inproceedings}
}
Low latency divider using ensemble of moving average curves
@inproceedings{motomura_00127,
title = {Low latency divider using ensemble of moving average curves},
author = {Yuhan Fu and Masayuki Ikebe and Takeshi Shimada and Masato Motomura and Tetsuya Asai},
year = {2017},
date = {2017-03-01},
booktitle = {International Symposium on Quality Electronic Design (ISQED)},
address = {Santa Clara, USA},
keywords = {International Conference},
pubstate = {published},
tppubtype = {inproceedings}
}
Quantization Error-based Regularization in Neural Networks
@inproceedings{ando_00016,
title = {Quantization Error-based Regularization in Neural Networks},
author = {Kazutoshi Hirose and Kota Ando and Kodai Ueyoshi and Masayuki Ikebe and Tetsuya Asai and Masato Motomura and Shinya Takamaeda-Yamazaki},
year = {2017},
date = {2017-12-01},
booktitle = {SGAI International Conference on Artificial Intelligence (SGAI)},
address = {Cambridge, England},
keywords = {International Conference},
pubstate = {published},
tppubtype = {inproceedings}
}
Sign-Invariant Unsupervised Learning Facilitates Weighted-Sum Computation in Analog Neural-Network Devices
@inproceedings{motomura_00082,
title = {Sign-Invariant Unsupervised Learning Facilitates Weighted-Sum Computation in Analog Neural-Network Devices},
author = {Itaru Hida and Kodai Ueyoshi and Shinya Takamaeda-Yamazaki and Masayuki Ikebe and Masato Motomura and Tetsuya Asai},
year = {2017},
date = {2017-12-01},
booktitle = {International Symposium on Nonlinear Theory and Its Applications},
address = {Cancun, Mexico},
keywords = {International Conference},
pubstate = {published},
tppubtype = {inproceedings}
}
Throughput Analysis of A Data-Flow Reconfigurable Array Architecture for Convolutional Neural Networks
@inproceedings{ando_00028,
title = {Throughput Analysis of A Data-Flow Reconfigurable Array Architecture for Convolutional Neural Networks},
author = {Kota Ando and Kodai Ueyoshi and Kentaro Orimo and Masayuki Ikebe and Shinya Takamaeda-Yamazaki and Tetsuya Asai and Masato Motomura},
year = {2017},
date = {2017-02-01},
booktitle = {RIEC International Symposium on Brain Functions and Brain Computer},
address = {Sendai, Japan},
keywords = {International Conference},
pubstate = {published},
tppubtype = {inproceedings}
}
@article{motomura_00021,
title = {3D Stacked Imager Featuring Inductive Coupling Channels for High Speed/Low-Noise Image Transfer},
author = {Masayuki Ikebe and Daisuke Uchida and Yasuhiro Take and Makito Someya and Satoshi Chikuda and Kento Matsuyama and Tetsuya Asai and Tadahiro Kuroda and Masato Motomura},
year = {2016},
date = {2016-04-01},
journal = {ITE Transactions on Media Technology and Applications},
volume = {4},
number = {2},
pages = {142-148},
keywords = {Journal Papers},
pubstate = {published},
tppubtype = {article}
}
A Hardware Cellular-Automaton Architecture for Spatial Pattern Generation towards Motion-Vector Estimation of Textureless Objects
@inproceedings{motomura_00145,
title = {A Hardware Cellular-Automaton Architecture for Spatial Pattern Generation towards Motion-Vector Estimation of Textureless Objects},
author = {Aoi Tanibata and Miho Ushida and Alexandre Schmid and Masayuki Ikebe and Tetsuya Asai and Masato Motomura},
year = {2016},
date = {2016-11-01},
booktitle = {International Symposium on Nonlinear Theory and its Applications},
address = {Shizuoka, Japan},
keywords = {International Conference},
pubstate = {published},
tppubtype = {inproceedings}
}
A Memory-Based Realization of A Binarized Deep Convolutional Neural Network
@inproceedings{sugiura2016programmable,
title = {A Programmable Controller for Spatio-Temporal Pattern Stimulation of Cortical Visual Prosthesis},
author = {Tomoki Sugiura and Arif Ullah Khan and Jaehoon Yu and Yoshinori Takeuchi and Seiji Kameda and Takatsugu Kamata and Yuki Hayashida and Tetsuya Yagi and Masaharu Imai},
year = {2016},
date = {2016-01-01},
booktitle = {IEEE_C_BCAS},
pages = {432--435},
note = {(被引用件数: 2)},
keywords = {International Conference},
pubstate = {published},
tppubtype = {inproceedings}
}
A Two-Clock-Cycle Naive Bayes Classifier for Dynamic Branch Prediction in Pipelined RISC Microprocessors
@inproceedings{motomura_00143,
title = {An FPGA-Optimized Architecture of Anti-Aliasing Based Super Resolution for Real-time HDTV to 4K- and 8K-UHD Conversions},
author = {Hotaka Kusano and Masayuki Ikebe and Tetsuya Asai and Masato Motomura},
year = {2016},
date = {2016-11-01},
booktitle = {International Conference on Reconfigurable Computing and FPGAs},
address = {Cancun, Mexico},
keywords = {International Conference},
pubstate = {published},
tppubtype = {inproceedings}
}
Arrhythmia Detection Using a Deformable Part Model and Time Domain Features
@inproceedings{hirao2016arrhythmia,
title = {Arrhythmia Detection Using a Deformable Part Model and Time Domain Features},
author = {Yuuka Hirao and Jaehoon Yu and Yoshinori Takeuchi and Masaharu Imai},
year = {2016},
date = {2016-01-01},
pages = {94--99},
note = {(Student Best Paper Award)},
keywords = {International Conference},
pubstate = {published},
tppubtype = {inproceedings}
}
Cognitive Motion Processing in Imager/Neural Processor 3D Stacked Systems
@article{motomura_00017,
title = {FPGA Implementation of A Scalable and Highly Parallel Architecture for Restricted Boltzmann Machines},
author = {Kodai Ueyoshi and Takao Marukame and Tetsuya Asai and Masato Motomura and Alexandre Schmid},
year = {2016},
date = {2016-07-01},
journal = {Circuits and Systems},
volume = {7},
number = {9},
pages = {2132-2141},
keywords = {Journal Papers},
pubstate = {published},
tppubtype = {article}
}
FPGA-Based Stream Processing for Frequent Itemset Mining with Incremental Multiple Hashes
@inproceedings{motomura_00161,
title = {Memory-Error Tolerance of Scalable and Highly Parallel Architecture for Restricted Boltzmann Machines in Deep Belief Network},
author = {Kodai Ueyoshi and Takao Marukame and Tetsuya Asai and Masato Motomura and Alexandre Schmid},
year = {2016},
date = {2016-05-01},
booktitle = {IEEE International Symposium on Circuits and Systems},
address = {Montreal, Canada},
keywords = {International Conference},
pubstate = {published},
tppubtype = {inproceedings}
}
Motion Vector Estimation of Textureless Objects Exploiting Reaction-Diffusion Cellular Automata
@inproceedings{motomura_00158,
title = {Motion-Vector Estimation and Cognitive Classification on An Image Sensor/Processor 3D Stacked System Featuring ThruChip Interfaces},
author = {Tetsuya Asai and Masafumi Mori and Toshiyuki Itou and Yasuhiro Take and Masayuki Ikebe and Tadahiro Kuroda and Masato Motomura},
year = {2016},
date = {2016-09-01},
booktitle = {European Solid-State Circuits Conference},
address = {Lausanne, Switzerland},
keywords = {International Conference},
pubstate = {published},
tppubtype = {inproceedings}
}
Object Tracking based on Path Similarity of Boosted Decision Trees
@inproceedings{kawabe2016proposal,
title = {Proposal of An Efficient Clock-Gating Mechanism for Multi-Core Processors to Reduce Power Supply Noise},
author = {Jun Kawabe and Yoshinori Takeuchi and Jaehoon Yu and Masaharu Imai},
year = {2016},
date = {2016-01-01},
booktitle = {Workshop on Synthesis And System Integration of Mixed Information technologies},
pages = {178--183},
keywords = {International Conference},
pubstate = {published},
tppubtype = {inproceedings}
}
Reconfigurable Processor Array Architecture for Deep Convolutional Neural Networks
@inproceedings{ando_00030,
title = {Reconfigurable Processor Array Architecture for Deep Convolutional Neural Networks},
author = {Kota Ando and Kentaro Orimo and Kodai Ueyoshi and Masayuki Ikebe and Tetsuya Asai and Masato Motomura},
year = {2016},
date = {2016-10-01},
booktitle = {Workshop on Synthesis And System Integration of Mixed Information Technologies},
address = {Kyoto, Japan},
keywords = {International Conference},
pubstate = {published},
tppubtype = {inproceedings}
}
Reconfigurable Processor Array Architecture for Deep Convolutional Neural Networks
@inproceedings{motomura_00150,
title = {Reconfigurable Processor Array Architecture for Deep Convolutional Neural Networks},
author = {Kota Ando and Kentaro Orimo and Kodai Ueyoshi and Masayuki Ikebe and Tetsuya Asai and Masato Motomura},
year = {2016},
date = {2016-10-01},
booktitle = {Workshop on Synthesis And System Integration of Mixed Information Technologies},
address = {Kyoto, Japan},
keywords = {International Conference},
pubstate = {published},
tppubtype = {inproceedings}
}
Robustness of Hardware-Oriented Restricted Boltzmann Machines in Deep Belief Networks for Reliable Processing
@article{motomura_00018,
title = {Robustness of Hardware-Oriented Restricted Boltzmann Machines in Deep Belief Networks for Reliable Processing},
author = {Kodai Ueyoshi and Takao Marukame and Tetsuya Asai and Masato Motomura and Alexandre Schmid},
year = {2016},
date = {2016-07-01},
journal = {Nonlinear Theory and Its Applications},
volume = {E7-N},
number = {3},
pages = {395-406},
keywords = {Journal Papers},
pubstate = {published},
tppubtype = {article}
}
Stochastic Resonance Induced by Internal Noise in A Unidirectional Network of Excitable FitzHugh-Nagumo Neurons
@article{motomura_00020,
title = {Stochastic Resonance Induced by Internal Noise in A Unidirectional Network of Excitable FitzHugh-Nagumo Neurons},
author = {Kazuyoshi Ishimura and Alexandre Schmid and Tetsuya Asai and Masato Motomura},
year = {2016},
date = {2016-04-01},
journal = {Nonlinear Theory and Its Applications},
volume = {7},
number = {2},
pages = {164-175},
keywords = {Journal Papers},
pubstate = {published},
tppubtype = {article}
}
System Design of Vision-based Framework for Senior Driver Assistance
Eric Aliwarga, Koichi Mitsunari, Jaehoon Yu, Takao Onoye, Toshitaka Azuma, Mitsuhiko Koga
Workshop on Synthesis And System Integration of Mixed Information technologies,2016
@inproceedings{aliwarga2016system,
title = {System Design of Vision-based Framework for Senior Driver Assistance},
author = {Eric Aliwarga and Koichi Mitsunari and Jaehoon Yu and Takao Onoye and Toshitaka Azuma and Mitsuhiko Koga},
year = {2016},
date = {2016-01-01},
booktitle = {Workshop on Synthesis And System Integration of Mixed Information technologies},
pages = {77--80},
keywords = {International Conference},
pubstate = {published},
tppubtype = {inproceedings}
}
The Synchronous vs. Asynchronous NoC Routers: An Apple-to-Apple Comparison between Synchronous and Transition Signaling Asynchronous Designs
Masashi Imai, Thiem Van Chu, Kenji Kise, Tomohiro Yoneda
IEEE/ACM International Symposium on Networks-on-Chip (NOCS),2016
@inproceedings{thiem-nocs2016,
title = {The Synchronous vs. Asynchronous NoC Routers: An Apple-to-Apple Comparison between Synchronous and Transition Signaling Asynchronous Designs},
author = {Masashi Imai and Thiem Van Chu and Kenji Kise and Tomohiro Yoneda},
year = {2016},
date = {2016-01-01},
booktitle = {IEEE/ACM International Symposium on Networks-on-Chip (NOCS)},
pages = {1--8},
keywords = {International Conference},
pubstate = {published},
tppubtype = {inproceedings}
}
Vision-based Comprehensive Framework for Senior Driver Assistance
Mitsuhiko Koga, Takao Onoye, Jaehoon Yu, Toshitaka Azuma, Eric Aliwarga
@inproceedings{koga2016vision,
title = {Vision-based Comprehensive Framework for Senior Driver Assistance},
author = {Mitsuhiko Koga and Takao Onoye and Jaehoon Yu and Toshitaka Azuma and Eric Aliwarga},
year = {2016},
date = {2016-01-01},
booktitle = {ERTICO},
keywords = {International Conference},
pubstate = {published},
tppubtype = {inproceedings}
}
@inproceedings{motomura_00181,
title = {A New Architecture for Feature Extraction to Perform Machine Learning by Using Motion Vectors and Its Implementation in An FPGA},
author = {Toshiyuki Itou and Masafumi Mori and Masayuki Ikebe and Tetsuya Asai and Tadahiro Kuroda and Masato Motomura},
year = {2015},
date = {2015-02-01},
booktitle = {RISP International Workshop on Nonlinear Circuits, Communications and Signal Processing},
address = {Kuala Lumpur, Malaysia},
keywords = {International Conference},
pubstate = {published},
tppubtype = {inproceedings}
}
A Reaction-Diffusion Algorithm for Texture Generation towards Motion-Vector Estimation of Textureless-Objects
@inproceedings{motomura_00183,
title = {A Reaction-Diffusion Algorithm for Texture Generation towards Motion-Vector Estimation of Textureless-Objects},
author = {Miho Ushida and Kazuyoshi Ishimura and Tetsuya Asai and Masato Motomura},
year = {2015},
date = {2015-02-01},
booktitle = {RISP International Workshop on Nonlinear Circuits, Communications and Signal Processing},
address = {Kuala Lumpur, Malaysia},
keywords = {International Conference},
pubstate = {published},
tppubtype = {inproceedings}
}
An Accelerator for Frequent Itemset Mining from Data Stream with Parallel Item Tree
Kasho Yamamoto, Eric S Fukuda, Tetsuya Asai, Masato Motomura
Workshop on Synthesis And System Integration of Mixed Information Technologies,2015
@inproceedings{motomura_00179,
title = {An Accelerator for Frequent Itemset Mining from Data Stream with Parallel Item Tree},
author = {Kasho Yamamoto and Eric S Fukuda and Tetsuya Asai and Masato Motomura},
year = {2015},
date = {2015-03-01},
booktitle = {Workshop on Synthesis And System Integration of Mixed Information Technologies},
address = {Yilan, Taiwan},
keywords = {International Conference},
pubstate = {published},
tppubtype = {inproceedings}
}
Crosstalk Rejection in 3D-Stacked Inter-Chip Communication with Blind Source Separation
Kamal El-Sankary, Tetsuya Asai, Tadahiro Kuroda, Masato Motomura
@article{motomura_00022,
title = {Crosstalk Rejection in 3D-Stacked Inter-Chip Communication with Blind Source Separation},
author = {Kamal El-Sankary and Tetsuya Asai and Tadahiro Kuroda and Masato Motomura},
year = {2015},
date = {2015-08-01},
journal = {IEEE Transactions on Circuits and Systems II},
volume = {62},
number = {8},
pages = {726-730},
keywords = {Journal Papers},
pubstate = {published},
tppubtype = {article}
}
Design of Generic Hardware for Soft Cascade-Based Linear SVM Classification
Eric Aliwarga, Jaehoon Yu, Masahide Hatanaka, Takao Onoye
@article{motomura_00025,
title = {Enhancing Memcached by Caching its Data and Functionalities at Network Interface},
author = {Eric S Fukuda and Hiroaki Inoue and Takashi Takenaka and Dahoo Kim and Tsunaki Sadahisa and Tetsuya Asai and Masato Motomura},
year = {2015},
date = {2015-03-01},
journal = {IPSJ Journal},
volume = {56},
number = {3},
pages = {143-152},
keywords = {Journal Papers},
pubstate = {published},
tppubtype = {article}
}
FPGA Implementation of Hardware-Oriented Reaction-Diffusion Cellular Automata Models
@article{motomura_00023,
title = {FPGA Implementation of Hardware-Oriented Reaction-Diffusion Cellular Automata Models},
author = {Kazuyoshi Ishimura and Katsuro Komuro and Alexandre Schmid and Tetsuya Asai and Masato Motomura},
year = {2015},
date = {2015-04-01},
journal = {Nonlinear Theory and Its Applications},
volume = {6},
number = {2},
pages = {252-262},
keywords = {Journal Papers},
pubstate = {published},
tppubtype = {article}
}
Image Sensor/Digital Logic 3D Stacked Module Featuring Inductive Coupling Channels for High Speed/Low-Noise Image Transfer
@inproceedings{motomura_00174,
title = {Image Sensor/Digital Logic 3D Stacked Module Featuring Inductive Coupling Channels for High Speed/Low-Noise Image Transfer},
author = {Masayuki Ikebe and Daisuke Uchida and Yasuhiro Take and Makito Someya and Satoshi Chikuda and Kento Matsuyama and Tetsuya Asai and Tadahiro Kuroda and Masato Motomura},
year = {2015},
date = {2015-06-01},
booktitle = {Symposia on VLSI Technology and Circuits},
address = {Kyoto, Japan},
keywords = {International Conference},
pubstate = {published},
tppubtype = {inproceedings}
}
Motion Vector Estimation of Textureless Objects Exploiting Reaction-Diffusion Cellular Automata
@inproceedings{motomura_00182,
title = {Scalable and Highly-Parallel Architecture for Restricted Boltzmann Machines},
author = {Kodai Ueyoshi and Tetsuya Asai and Masato Motomura},
year = {2015},
date = {2015-02-01},
booktitle = {RISP International Workshop on Nonlinear Circuits, Communications and Signal Processing},
address = {Kuala Lumpur, Malaysia},
keywords = {International Conference},
pubstate = {published},
tppubtype = {inproceedings}
}
Through Chip Interface Based Three-Dimensional FPGA Architecture Exploration
@inproceedings{motomura_00189,
title = {A Study of Transparent On-Chip Instruction Cache for NV Microcontrollers},
author = {Dahoo Kim and Itaru Hida and Eric S Fukuda and Tetsuya Asai and Masato Motomura},
year = {2014},
date = {2014-11-01},
booktitle = {International Conference on Advances in Circuits, Electronics and Micro-electronics},
address = {Lisbon, Portugal},
keywords = {International Conference},
pubstate = {published},
tppubtype = {inproceedings}
}
Achieving Higher Performance of Memcached by Caching at Network Interface
Eric S Fukuda, Hiroaki Inoue, Takashi Takenaka, Dahoo Kim, Tsunaki Sadahisa, Tetsuya Asai, Masato Motomura
International Conference on Field Programmable Technology (FPT),2014
@inproceedings{motomura_00185,
title = {Achieving Higher Performance of Memcached by Caching at Network Interface},
author = {Eric S Fukuda and Hiroaki Inoue and Takashi Takenaka and Dahoo Kim and Tsunaki Sadahisa and Tetsuya Asai and Masato Motomura},
year = {2014},
date = {2014-12-01},
booktitle = {International Conference on Field Programmable Technology (FPT)},
address = {Shanghai, China},
keywords = {International Conference},
pubstate = {published},
tppubtype = {inproceedings}
}
An Efficient Data Compression Method for Artificial Vision Systems and Its Low Energy Implementation Using ASIP Technology
@inproceedings{sugiura2014efficient,
title = {An Efficient Data Compression Method for Artificial Vision Systems and Its Low Energy Implementation Using ASIP Technology},
author = {Tomoki Sugiura and Shoko Nakatsuka and Jaehoon Yu and Yoshinori Takeuchi and Masaharu Imai},
year = {2014},
date = {2014-01-01},
booktitle = {IEEE_C_BCAS},
pages = {81--84},
keywords = {International Conference},
pubstate = {published},
tppubtype = {inproceedings}
}
Application of Nonlinear Systems for Designing Low-Power Logic Gates Based on Stochastic Resonance
@article{motomura_00027,
title = {Application of Nonlinear Systems for Designing Low-Power Logic Gates Based on Stochastic Resonance},
author = {Gonzalez-Carabarin Lizeth and Tetsuya Asai and Masato Motomura},
year = {2014},
date = {2014-10-01},
journal = {Nonlinear Theory and Its Applications},
volume = {5},
number = {4},
pages = {445-455},
keywords = {Journal Papers},
pubstate = {published},
tppubtype = {article}
}
Caching Memcached at Reconfigurable Network Interface
Eric S Fukuda, Hiroaki Inoue, Takashi Takenaka, Dahoo Kim, Tsunaki Sadahisa, Tetsuya Asai, Masato Motomura
International Conference on Field Programmable Logic and Applications (FPL),2014
@inproceedings{motomura_00195,
title = {Caching Memcached at Reconfigurable Network Interface},
author = {Eric S Fukuda and Hiroaki Inoue and Takashi Takenaka and Dahoo Kim and Tsunaki Sadahisa and Tetsuya Asai and Masato Motomura},
year = {2014},
date = {2014-09-01},
booktitle = {International Conference on Field Programmable Logic and Applications (FPL)},
address = {Munich, Germany},
keywords = {International Conference},
pubstate = {published},
tppubtype = {inproceedings}
}
Dual-Rail Asynchronous Pipeline Based on Stochastic Resonance Logic Gates
@inproceedings{motomura_00193,
title = {Dual-Rail Asynchronous Pipeline Based on Stochastic Resonance Logic Gates},
author = {Gonzalez-Carabarin Lizeth and Tetsuya Asai and Masato Motomura},
year = {2014},
date = {2014-09-01},
booktitle = {International Symposium on Nonlinear Theory and its Applications},
address = {Luzern, Switzerland},
keywords = {International Conference},
pubstate = {published},
tppubtype = {inproceedings}
}
FPGA Implementation of A Memory-Efficient Stereo Vision Algorithm Based on 1-D Guided Filtering
@inproceedings{motomura_00208,
title = {FPGA Implementation of A Memory-Efficient Stereo Vision Algorithm Based on 1-D Guided Filtering},
author = {Yuki Sanada and Katsuki Ohata and Tetsuro Ogaki and Kento Matsuyama and Takanori Ohira and Satoshi Chikuda and Masaki Igarashi and Tadahiro Kuroda and Masayuki Ikebe and Tetsuya Asai and Masato Motomura},
year = {2014},
date = {2014-02-01},
booktitle = {International Conference on Circuits, Systems, and Control},
address = {Interlaken, Switzerland},
keywords = {International Conference},
pubstate = {published},
tppubtype = {inproceedings}
}
FPGA-Based Design for Motion-Vector Estimation Exploiting High-Speed Imaging and Its Application to Machine Learning
@inproceedings{motomura_00207,
title = {FPGA-Based Design for Motion-Vector Estimation Exploiting High-Speed Imaging and Its Application to Machine Learning},
author = {Masafumi Mori and Toshiyuki Itou and Masayuki Ikebe and Tetsuya Asai and Tadahiro Kuroda and Masato Motomura},
year = {2014},
date = {2014-02-01},
booktitle = {RISP International Workshop on Nonlinear Circuits, Communications and Signal Processing},
address = {Honolulu, U.S.A.},
keywords = {International Conference},
pubstate = {published},
tppubtype = {inproceedings}
}
FPGA-Based Design for Motion-Vector Estimation Exploiting High-Speed Imaging and Its Application to Motion Classification with Neural Networks
@article{motomura_00029,
title = {FPGA-Based Design for Motion-Vector Estimation Exploiting High-Speed Imaging and Its Application to Motion Classification with Neural Networks},
author = {Masafumi Mori and Toshiyuki Itou and Masayuki Ikebe and Tetsuya Asai and Tadahiro Kuroda and Masato Motomura},
year = {2014},
date = {2014-07-01},
journal = {Journal of Signal Processing},
volume = {18},
number = {4},
pages = {165-168},
keywords = {Journal Papers},
pubstate = {published},
tppubtype = {article}
}
Hardware Architecture for Accelerating Key-Value Retrieval Implemented on FPGA
Dahoo Kim, Eric S Fukuda, Tsunaki Sadahisa, Tetsuya Asai, Masato Motomura
Japan-Korea Joint Workshop on Complex Communication Sciences,2014
@inproceedings{motomura_00192,
title = {Hardware Architecture for Accelerating Key-Value Retrieval Implemented on FPGA},
author = {Dahoo Kim and Eric S Fukuda and Tsunaki Sadahisa and Tetsuya Asai and Masato Motomura},
year = {2014},
date = {2014-10-01},
booktitle = {Japan-Korea Joint Workshop on Complex Communication Sciences},
address = {Busan, Korea},
keywords = {International Conference},
pubstate = {published},
tppubtype = {inproceedings}
}
Image Steganography Based on Reaction Diffusion Models toward Hardware Implementation
@article{motomura_00028,
title = {Image Steganography Based on Reaction Diffusion Models toward Hardware Implementation},
author = {Kazuyoshi Ishimura and Katsuro Komuro and Alexandre Schmid and Tetsuya Asai and Masato Motomura},
year = {2014},
date = {2014-10-01},
journal = {Nonlinear Theory and Its Applications},
volume = {5},
number = {4},
pages = {456-465},
keywords = {Journal Papers},
pubstate = {published},
tppubtype = {article}
}
Low-Power Asynchronous Digital Pipeline Based on Mismatch-Tolerant Logic Gates
@inproceedings{miyamoto2014normalized,
title = {Normalized Channel Features for Accurate Pedestrian Detection},
author = {Ryusuke Miyamoto and Jaehoon Yu and Takao Onoye},
year = {2014},
date = {2014-01-01},
booktitle = {International Symposium on Communications, Control and Signal Processing},
pages = {582--585},
note = {(被引用件数: 4)},
keywords = {International Conference},
pubstate = {published},
tppubtype = {inproceedings}
}
Reducing Power and Energy Consumption of Nonvolatile Microcontrollers with Transparent On-Chip Instruction Cache
Dahoo Kim, Itaru Hida, Eric S Fukuda, Tetsuya Asai, Masato Motomura
@article{motomura_00026,
title = {Reducing Power and Energy Consumption of Nonvolatile Microcontrollers with Transparent On-Chip Instruction Cache},
author = {Dahoo Kim and Itaru Hida and Eric S Fukuda and Tetsuya Asai and Masato Motomura},
year = {2014},
date = {2014-10-01},
journal = {Circuits and Systems},
volume = {5},
number = {11},
pages = {253-264},
keywords = {Journal Papers},
pubstate = {published},
tppubtype = {article}
}
Stochastic Resonance in A Unidirectional Network of Nonlinear Oscillators Driven by Internal Noise
@inproceedings{motomura_00194,
title = {Stochastic Resonance in A Unidirectional Network of Nonlinear Oscillators Driven by Internal Noise},
author = {Kazuyoshi Ishimura and Katsuro Komuro and Alexandre Schmid and Tetsuya Asai and Masato Motomura},
year = {2014},
date = {2014-09-01},
booktitle = {International Symposium on Nonlinear Theory and its Applications},
address = {Luzern, Switzerland},
keywords = {International Conference},
pubstate = {published},
tppubtype = {inproceedings}
}
@inproceedings{motomura_00213,
title = {A Restricted Dynamically Reconfigurable Architecture for Low Power Processors},
author = {Takeshi Hirao and Dahoo Kim and Itaru Hida and Tetsuya Asai and Masato Motomura},
year = {2013},
date = {2013-12-01},
booktitle = {International Conference on ReConFigurable Computing and FPGAs},
address = {Cancun, Mexico},
keywords = {International Conference},
pubstate = {published},
tppubtype = {inproceedings}
}
A Restricted Dynamically Reconfigurable Architecture for Low Power Processors
Takeshi Hirao, Dahoo Kim, Itaru Hida, Tetsuya Asai, Masato Motomura
Workshop on Synthesis And System Integration of Mixed Information Technologies,2013
@inproceedings{motomura_00218,
title = {A Restricted Dynamically Reconfigurable Architecture for Low Power Processors},
author = {Takeshi Hirao and Dahoo Kim and Itaru Hida and Tetsuya Asai and Masato Motomura},
year = {2013},
date = {2013-10-01},
booktitle = {Workshop on Synthesis And System Integration of Mixed Information Technologies},
address = {Sapporo, Japan},
keywords = {International Conference},
pubstate = {published},
tppubtype = {inproceedings}
}
A Speed-Up Scheme Based on Multiple-Instance Pruning for Pedestrian Detection Using A Support Vector Machine
@article{yu2013speed,
title = {A Speed-Up Scheme Based on Multiple-Instance Pruning for Pedestrian Detection Using A Support Vector Machine},
author = {Jaehoon Yu and Ryusuke Miyamoto and Takao Onoye},
year = {2013},
date = {2013-01-01},
volume = {22},
number = {12},
pages = {4752--4761},
note = {(IF: 5.071, 被引用件数: 9)},
keywords = {Journal Papers},
pubstate = {published},
tppubtype = {article}
}
Asynchronous Digital Circuit Design Using Noise-Driven Stochastic Gates
@inproceedings{motomura_00222,
title = {Asynchronous Digital Circuit Design Using Noise-Driven Stochastic Gates},
author = {Gonzalez-Carabarin Lizeth and Tetsuya Asai and Masato Motomura},
year = {2013},
date = {2013-09-01},
booktitle = {International Symposium on Nonlinear Theory and its Applications},
address = {Santa Fe, U.S.A.},
keywords = {International Conference},
pubstate = {published},
tppubtype = {inproceedings}
}
C-Based Adaptive Stream Processing on Dynamically Reconfigurable Hardware: Window Join Case Study
Eric S Fukuda, Hideyuki Kawashima, Hiroaki Inoue, Taro Fujii, Koichiro Furuta, Tetsuya Asai, Masato Motomura
International Symposium on Applied Reconfigurable Computing (ARC),2013
@article{motomura_00032b,
title = {C-Based Design of Window Join for Dynamically Reconfigurable Hardware},
author = {Eric S Fukuda and Hideyuki Kawashima and Hiroaki Inoue and Tetsuya Asai and Masato Motomura},
year = {2013},
date = {2013-11-01},
journal = {Journal of Computer Science and Engineering},
volume = {20},
number = {2},
pages = {1-9},
keywords = {Journal Papers},
pubstate = {published},
tppubtype = {article}
}
@inproceedings{motomura_00219,
title = {FPGA Implementation of 60-FPS QVGA-to-VGA Single-Image Super Resolution},
author = {Satoshi Chikuda and Takanori Ohira and Yuki Sanada and Masaki Igarashi and Masayuki Ikebe and Tetsuya Asai and Masato Motomura},
year = {2013},
date = {2013-09-01},
booktitle = {International Conference on Solid State Devices and Materials},
address = {Fukuoka, Japan},
keywords = {International Conference},
pubstate = {published},
tppubtype = {inproceedings}
}
FPGA Implementation of Single-Image Super Resolution Based on Frame-Bufferless Box Filtering
@article{motomura_00033b,
title = {FPGA Implementation of Single-Image Super Resolution Based on Frame-Bufferless Box Filtering},
author = {Yuki Sanada and Takanori Ohira and Satoshi Chikuda and Masaki Igarashi and Masayuki Ikebe and Tetsuya Asai and Masato Motomura},
year = {2013},
date = {2013-07-01},
journal = {Journal of Signal Processing},
volume = {17},
number = {4},
pages = {111-114},
keywords = {Journal Papers},
pubstate = {published},
tppubtype = {article}
}
FPGA Implementation of Single-Image Super Resolution Based on Frame-Bufferless Box Filtering
@inproceedings{motomura_00237,
title = {FPGA Implementation of Single-Image Super Resolution Based on Frame-Bufferless Box Filtering},
author = {Yuki Sanada and Takanori Ohira and Satoshi Chikuda and Masaki Igarashi and Masayuki Ikebe and Tetsuya Asai and Masato Motomura},
year = {2013},
date = {2013-03-01},
booktitle = {RISP International Workshop on Nonlinear Circuits, Communications and Signal Processing},
address = {The Island of Hawaii, U.S.A.},
keywords = {International Conference},
pubstate = {published},
tppubtype = {inproceedings}
}
Hardware-Oriented Stereo Vision Algorithm Based on 1-D Guided Filtering and Its FPGA Implementation
@inproceedings{motomura_00214,
title = {Hardware-Oriented Stereo Vision Algorithm Based on 1-D Guided Filtering and Its FPGA Implementation},
author = {Katsuki Ohata and Yuki Sanada and Tetsuro Ogaki and Kento Matsuyama and Takanori Ohira and Satoshi Chikuda and Masaki Igarashi and Masayuki Ikebe and Tetsuya Asai and Masato Motomura and Tadahiro Kuroda},
year = {2013},
date = {2013-12-01},
booktitle = {IEEE International Conference on Electronics, Circuits, and Systems},
address = {Abu Dhabi, UAE},
keywords = {International Conference},
pubstate = {published},
tppubtype = {inproceedings}
}
High Level Synthesis with Stream Query to C Parser: Eliminating Hardware Development Difficulties for Software Developers
Eric S Fukuda, Takashi Takenaka, Hiroaki Inoue, Hideyuki Kawashima, Tetsuya Asai, Masato Motomura
Workshop on Synthesis And System Integration of Mixed Information Technologies,2013
@inproceedings{motomura_00217,
title = {High Level Synthesis with Stream Query to C Parser: Eliminating Hardware Development Difficulties for Software Developers},
author = {Eric S Fukuda and Takashi Takenaka and Hiroaki Inoue and Hideyuki Kawashima and Tetsuya Asai and Masato Motomura},
year = {2013},
date = {2013-10-01},
booktitle = {Workshop on Synthesis And System Integration of Mixed Information Technologies},
address = {Sapporo, Japan},
keywords = {International Conference},
pubstate = {published},
tppubtype = {inproceedings}
}
Image steganography based on hardware-oriented reaction-diffusion models
@inproceedings{motomura_00223,
title = {Image steganography based on hardware-oriented reaction-diffusion models},
author = {Kazuyoshi Ishimura and Alexandre Schmid and Tetsuya Asai and Masato Motomura},
year = {2013},
date = {2013-09-01},
booktitle = {International Symposium on Nonlinear Theory and its Applications},
address = {Santa Fe, U.S.A.},
keywords = {International Conference},
pubstate = {published},
tppubtype = {inproceedings}
}
Image Steganography on Digital Reaction-Diffusion Processor
@inproceedings{motomura_00249,
title = {A Memristor-Based Synaptic Device Having an Asymmetric STDP Time Window},
author = {Taku Adachi and Tetsuya Asai and Masato Motomura},
year = {2012},
date = {2012-03-01},
booktitle = {RISP International Workshop on Nonlinear Circuits, Communications and Signal Processing},
address = {Honolulu, U.S.A.},
keywords = {International Conference},
pubstate = {published},
tppubtype = {inproceedings}
}
Chaotic Resonance in Forced Chua’s Oscillator
Kazuyoshi Ishimura, Tetsuya Asai, Masato Motomura
RISP International Workshop on Nonlinear Circuits, Communications and Signal Processing,2012
@article{motomura_00035b,
title = {Excitable Reaction-Diffusion Media with Memristors},
author = {Xiyuan Gong and Tetsuya Asai and Masato Motomura},
year = {2012},
date = {2012-07-01},
journal = {Journal of Signal Processing},
volume = {16},
number = {4},
pages = {283-286},
keywords = {Journal Papers},
pubstate = {published},
tppubtype = {article}
}
Excitable Reaction-Diffusion Media with Memristors
Xiyuan Gong, Tetsuya Asai, Masato Motomura
RISP International Workshop on Nonlinear Circuits, Communications and Signal Processing,2012
@inproceedings{motomura_00251,
title = {Excitable Reaction-Diffusion Media with Memristors},
author = {Xiyuan Gong and Tetsuya Asai and Masato Motomura},
year = {2012},
date = {2012-03-01},
booktitle = {RISP International Workshop on Nonlinear Circuits, Communications and Signal Processing},
address = {Honolulu, U.S.A.},
keywords = {International Conference},
pubstate = {published},
tppubtype = {inproceedings}
}
Impact of Noise on Spike Transmission through Serially-Connected Electrical FitzHugh-Nagumo Circuits with Subthreshold and Suprathreshold Interconductances
@article{motomura_00037b,
title = {Impact of Noise on Spike Transmission through Serially-Connected Electrical FitzHugh-Nagumo Circuits with Subthreshold and Suprathreshold Interconductances},
author = {Gonzalez-Carabarin Lizeth and Tetsuya Asai and Masato Motomura},
year = {2012},
date = {2012-03-01},
journal = {Journal of Signal Processing},
volume = {16},
number = {6},
pages = {503-509},
keywords = {Journal Papers},
pubstate = {published},
tppubtype = {article}
}
Noise Impact on Spike Transmission through Serially-Connected Electrical FitzHugh-Nagumo Model with Subthreshold and Suprathreshold Interconductances
@inproceedings{motomura_00246,
title = {Noise Impact on Spike Transmission through Serially-Connected Electrical FitzHugh-Nagumo Model with Subthreshold and Suprathreshold Interconductances},
author = {Gonzalez-Carabarin Lizeth and Tetsuya Asai and Masato Motomura},
year = {2012},
date = {2012-05-01},
booktitle = {International Conference On Cognitive and Neural Systems},
address = {Boston, U.S.A.},
keywords = {International Conference},
pubstate = {published},
tppubtype = {inproceedings}
}
Noise-Assisted Spike Transmission on An Array of Electrical FitzHugh-Nagumo Models
@inproceedings{motomura_00253,
title = {Noise-Assisted Spike Transmission on An Array of Electrical FitzHugh-Nagumo Models},
author = {Gonzalez-Carabarin Lizeth and Tetsuya Asai and Masato Motomura},
year = {2012},
date = {2012-03-01},
booktitle = {RISP International Workshop on Nonlinear Circuits, Communications and Signal Processing},
address = {Honolulu, U.S.A.},
keywords = {International Conference},
pubstate = {published},
tppubtype = {inproceedings}
}
Noise-Induced Phase Synchronization among Simple Digital Counters
@inproceedings{motomura_00252,
title = {Noise-Induced Phase Synchronization in Digital Counters},
author = {Masakazu Matsuura and Tetsuya Asai and Masato Motomura},
year = {2012},
date = {2012-03-01},
booktitle = {RISP International Workshop on Nonlinear Circuits, Communications and Signal Processing},
address = {Honolulu, U.S.A.},
keywords = {International Conference},
pubstate = {published},
tppubtype = {inproceedings}
}
Pedestrian Localization Using CoHOG-based Detection and HSV-based Tracking
@inproceedings{motomura_00245,
title = {Reaction-Diffusion Media with Excitable Oregonators Coupled by Memristors},
author = {Xiyuan Gong and Tetsuya Asai and Masato Motomura},
year = {2012},
date = {2012-08-01},
booktitle = {International Workshop on Cellular Nanoscale Networks and their Applications (Memristor and Memristive Symposium)},
address = {Turin, Italy},
keywords = {International Conference},
pubstate = {published},
tppubtype = {inproceedings}
}
Spatio-Temporal Pattern Formation on Memristive Reaction-Diffusion Systems
Xiyuan Gong, Tetsuya Asai, Masato Motomura
Asia Conference on Nanoscience and Nanotechnology,2012
@inproceedings{motomura_00242,
title = {Spike Propagation in Excitable Systems Enhanced by Membrane-Potential-Dependent Noise},
author = {Gonzalez-Carabarin Lizeth and Tetsuya Asai and Masato Motomura},
year = {2012},
date = {2012-10-01},
booktitle = {International Symposium on Nonlinear Theory and its Applications},
address = {Majorca, Spain},
keywords = {International Conference},
pubstate = {published},
tppubtype = {inproceedings}
}
Spike Transmission in Locally Coupled Excitable Circuits Enhanced by Membrane-Potential-Dependent Noise
@article{motomura_00038b,
title = {Test Compression for Dynamically Reconfigurable Processors},
author = {Hiroaki Inoue and Junya Yamada and Hideyuki Yoneda and Katsumi Togawa and Masato Motomura and Koichiro Furuta},
year = {2011},
date = {2011-12-01},
journal = {ACM Transactions on Reconfigurable Technology and Systems (TRETS)},
volume = {4},
number = {4},
pages = {40:1-15},
keywords = {Journal Papers},
pubstate = {published},
tppubtype = {article}
}
Time and Space-Multiplexed Compilation Challenge for Dynamically Reconfigurable Processors
@inproceedings{motomura_00268,
title = {Time and Space-Multiplexed Compilation Challenge for Dynamically Reconfigurable Processors},
author = {Takao Toi and Toru Awashima and Masato Motomura and Hideharu Amano},
year = {2011},
date = {2011-08-01},
booktitle = {IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)},
address = {Seoul, Korea},
keywords = {International Conference},
pubstate = {published},
tppubtype = {inproceedings}
}
@inproceedings{渡邊賢治20102,
title = {AS-2-4 階層探索による Full HD 対応 H. 264 小面積動き検出回路の開発 (AS-2. ディジタル信号処理システムの実装技術, シンポジウムセッション)},
author = {渡邊賢治 and 平井直行 and 今川隆司 and 劉載勲 and 橋本亮司 and 藤田玄},
year = {2010},
date = {2010-01-01},
journal = {電子情報通信学会総合大会講演論文集},
volume = {2010},
keywords = {International Conference},
pubstate = {published},
tppubtype = {inproceedings}
}
Computationally Efficient Pedestrian Detection Based on Markov Chain Monte Carlo
@inproceedings{yu2010gpu,
title = {GPU Implementation of Efficient Pedestrian Detection Based on MCMC},
author = {Jaehoon Yu and Hiroki Sugano and Ryusuke Miyamoto and Takao Onoye},
year = {2010},
date = {2010-01-01},
booktitle = {Joint International Conference on Soft Computing and Intelligent Systems and International Symposium on Advanced Intelligent Systems},
pages = {1624--1629},
keywords = {International Conference},
pubstate = {published},
tppubtype = {inproceedings}
}
@inproceedings{ishikawa2007implementation,
title = {Implementation of AV Streaming System Using Peer-to-Peer Communication},
author = {Norihiro Ishikawa and Hiroshi Tsutsui and Jaehoon Yu and Tomonori Izumi and Hiroyuki Ochi and Yukihiro Nakamura and Takaaki Komura and Yoshitaka Uchida},
year = {2007},
date = {2007-01-01},
booktitle = {IEEE Consumer Communications and Networking Conference},
pages = {778--782},
note = {(被引用件数: 7)},
keywords = {International Conference},
pubstate = {published},
tppubtype = {inproceedings}
}
@inproceedings{izumi2005implementation,
title = {Implementation of AV Control System Over Universal P2P Network},
author = {Tomonori Izumi and Jaehoon Yu and Tetsuya Kimata and Hiroyuki Ochi and Yukihiro Nakamura},
year = {2005},
date = {2005-01-01},
booktitle = {International Conference on Computing, Communications and Control Technologies},
pages = {9--14},
note = {(被引用件数: 4)},
keywords = {International Conference},
pubstate = {published},
tppubtype = {inproceedings}
}
@inproceedings{劉載勲2005情報家電ネットワークと携帯端末ネットワークをつなぐ,
title = {情報家電ネットワークと携帯端末ネットワークをつなぐ P2P 動画配信システムの構築},
author = {劉載勲 and 木全哲也 and 越智直紀 and 泉知論 and 越智裕之 and 中村行宏 and 小俣栄治 and 石川憲洋 and others},
year = {2005},
date = {2005-01-01},
booktitle = {情報処理学会研究報告モバイルコンピューティングとユビキタス通信 (MBL)},
volume = {2005},
number = {28 (2004-MBL-032)},
pages = {195--202},
keywords = {International Conference},
pubstate = {published},
tppubtype = {inproceedings}
}
2002
A Dynamically Reconfigurable Processor Architecture