研究業績 (β)

2026

AQPIM: Breaking the PIM Capacity Wall for LLMs with In-Memory Activation Quantization
Kosuke Matsushima, Yasuyuki Okoshi, Masato Motomura, Daichi Fujiki — 2026 IEEE International Symposium on High-Performance Computer Architecture (HPCA) — International Conference — 2026
Memory-Efficient and Trustworthy Neural Networks via Random Seed-Based Design
Hiroaki Ito, Hikari Otsuka, Ryota Yasudo, Zhiqiang Que, Jose G. F. Coutinho, Daichi Fujiki, Masato Motomura, Ce Guo, Wayne Luk — IEEE Access — Journal Papers — 2026
DOILink
The Strong Lottery Ticket Hypothesis for Multi-Head Attention Mechanisms
Hikari Otsuka, Daiki Chijiwa, Yasuyuki Okoshi, Daichi Fujiki, Susumu Takeuchi, Masato Motomura — The Fortieth AAAI Conference on Artificial Intelligence (AAAI 2026) — International Conference — 2026

2025

TTF-GNN: Memory-Efficient GNNs via Tensor Train Decomposition and Network Folding
Hiroaki Ito, Jiale Yan, Kazushi Kawamura, Masato Motomura, Thiem Van Chu, Daichi Fujiki — COOL Chips 28 — International Conference — 2025
DOILink
Accelerating Decision Forest Training via Node-Level Random Data Sampling
Tsukasa Yamakura, Kazushi Kawamura, Daichi Fujiki, Masato Motomura, Thiem Van Chu — Workshop — 2025
Amorphica: A Fully Connected Annealer Supporting Metamorphic Annealing and Scalable Multi Chip Integration
Daiki Okonogi, Jaehoon Yu, Satoru Jimbo, Genta Inoue, Akira Hyodo, Kota Ando, Hideki Fukushima-Kimura Bruno, Yasudo Ryota, Thiem Van Chu, Masato Motomura, Kazushi Kawamura — IEEE Access — Journal Papers — 2025
Binary Quadratic Quantization: Beyond First-Order Quantization for Real-Valued Matrix Compression
Kyo Kuroki, Yasuyuki Okoshi, Thiem Van Chu, Kazushi Kawamura, Masato Motomura — 39th Annual Conference on Neural Information Processing Systems (NeurIPS 2025) — International Conference — 2025
BingoGCN: Towards Scalable and Efficient GNN Acceleration with Fine-Grained Partitioning and SLT
Jiale Yan, Hiroaki Ito, Yuta Nagahara, Kazushi Kawamura, Masato Motomura, Thiem Van Chu, Daichi Fujiki — International Symposium on Computer Architecture (ISCA 2025) — International Conference — 2025
DOILink
Boltzmann Machine Is Useful for Enhancing Search Performance of Ising Machines
Satoru Jimbo, Kazushi Kawamura — International Conference — 2025
DMSA: An Efficient Architecture for Sparse–Sparse Matrix Multiplication Based on Distribute-Merge Product Dataflow
Yuta Nagahara, Jiale Yan, Kazushi Kawamura, Daichi Fujiki, Masato Motomura, Thiem Van Chu — IEEE Transactions on Very Large Scale Integration (VLSI) Systems — Journal Papers — 2025
DX100: Programmable Data Access Accelerator for Indirection
Alireza Khadem, Kamalavasan Kamalakkannan, Zhenyan Zhu, Akash Poptani, Yufeng Gu, Jered Benjamin Dominguez-Trujillo, Nishil Talati, Daichi Fujiki, Scott Mahlke, Galen Shipman, Reetuparna Das — International Symposium on Computer Architecture (ISCA 2025) — International Conference — 2025
Multi-Dimensional Vector ISA Extension for Mobile In-Cache Computing
Alireza Khadem, Daichi Fujiki, Hilbert Chen, Yufeng Gu, Nishil Talati, Scott Mahlke, Reetuparna Das — IEEE International Symposium on High Performance Computer Architecture (HPCA 2025) — International Conference — 2025
On the Existence of Hidden Subnetworks Within a Randomly Weighted Multi-Head Attention Mechanism
Hikari Otsuka, Yasuyuki Okoshi, Daichi Fujiki, Susumu Takeuchi, Masato Motomura, Daiki Chijiwa — Workshop — 2025
Partially Frozen Random Networks Contain Compact Strong Lottery Tickets
Transactions on Machine Learning Research — Journal Papers — 2025
Link
PIM による動的量子化を用いた大規模言語モデル推論の効率化
松島 康祐, 大越 康之, 本村 真人, 藤木 大地 — Workshop — 2025
Rethinking Optimal Verification Granularity for Compute-Efficient Test-Time Scaling
Hao Mark Chen, Guanxi Lu, Yasuyuki Okoshi, Zhiwen Mo, Masato Motomura, Hongxiang Fan — 39th Annual Conference on Neural Information Processing Systems (NeurIPS 2025) — International Conference — 2025
SharK: Enabling High-Performance Range Queries in Key-Value Store Through Vlog Resharding
Naoto Sugiura, Daichi Fujiki — IEEE Access — Journal Papers — 2025
DOI
TicketLLM: Next-Generation Sparse and Low-bit Transformers with Supermask-based Method
Yasuyuki Okoshi, Hikari Otsuka, Daichi Fujiki, Masato Motomura — Transactions on Machine Learning Research — Journal Papers — 2025
Uncovering Strong Lottery Tickets in Graph Transformers: A Path to Memory Efficient and Robust Graph Learning
Hiroaki Ito, Jiale Yan, Hikari Otsuka, Kazushi Kawamura, Masato Motomura, Thiem Van Chu, Daichi Fujiki — Transactions on Machine Learning Research — Journal Papers — 2025
Link
Unlocking the Potential of Extremely Low-Bit Sparse Transformers through Adaptive Multi-bit Supermasks and Random Weights
Yasuyuki Okoshi, Hikari Otsuka, Junnosuke Suzuki, Daichi Fujiki, Masato Motomura — Workshop — 2025
WhiteDwarf: A Holistic Co-Design Approach to Ultra-Compact Neural Inference Acceleration
Ángel López García-Arias, Yasuyuki Okoshi, Jaehoon Yu, Junnosuke Suzuki, Hikari Otsuka, Kazushi Kawamura, Thiem Van Chu, Daichi Fujiki, Masato Motomura — IEEE Access — Journal Papers — 2025
キオクシア奨励研究優秀研究賞
藤木大地 — Workshop — 2025
グラフトランスフォーマーにおける強い宝くじの発見
Hiroaki Ito, Jiale Yan, Hikari Otsuka, Kazushi Kawamura, Masato Motomura, Thiem Van Chu, Daichi Fujiki — Workshop — 2025
令和7年度 文部科学大臣表彰 科学技術賞 (開発部門) 「動的再構成プロセッサ技術とAI処理プロセッサの開発」
Masato Motomura — Workshop — 2025

2024

[Invited] AIチップ開発の最先端
本村 真人 — Workshop — 2024
[Invited] Algorithm-Architecture Centric Approach Towards Energy Efficient AI Hardware
Masato Motomura — Workshop — 2024
[Invited] Algorithm-Architecture Centric Approach Towards Energy Efficient AI Hardware
Masato Motomura — Workshop — 2024
[Invited] Algorithm-Architecture Centric Approach Towards Low Power AI Hardware
Masato Motomura — Workshop — 2024
[Invited] Reconfigurable AI Processing for Embedded Systems
Masato Motomura — Workshop — 2024
[Invited] Towards Multi-Layer Processing-in-Memory Systems for General Applications
Daichi Fujiki — Workshop — 2024
[Invited] Will AI Bite the Industry That Feeds It?
Masato Motomura — Workshop — 2024
[Invited] エッジ知能の実現に向けたAIコンピューティングの展望
本村 真人 — Workshop — 2024
[PMRU研究奨励賞] 強い宝くじ仮説に基づく超軽量物体検出ニューラルネットワーク
大塚 光莉 — Workshop — 2024
[優秀学生賞] 負荷均等配分を目指した高並列疎行列積アーキテクチャの研究
永原 雄大 — Workshop — 2024
[基調講演] 組み込み市場を変革するエッジAIの今後の展開
本村 真人 — Workshop — 2024
[記念講演] MVC: Enabling Fully Coherent Multi-Data-Views through the Memory Hierarchy with Processing in Memory
Daichi Fujiki — Workshop — 2024
[記念講演] 分散マージ乗算手法に基づく疎行列疎行列積アクセラレータ
永原 雄大, Jiale Yan, 川村 一志, 本村真人, Thiem Van Chu — Workshop — 2024
2スピン同時フリップの並列試行により高効率な解探索を行うアニーリングプロセッサ
兵藤旭, 神保聡, 小此木大輝, 井上源太, Thiem Van Chu, 本村真人, 川村一志 — Workshop — 2024
A GPU-Based Ising Machine With a Multi-Spin-Flip Capability for Constrained Combinatorial Optimization
Satoru Jimbo, Tatsuhiko Shirai, Nozomu Togawa, Masato Motomura, Kazushi Kawamura — IEEE Access — Journal Papers — 2024
A Parallel-trial Double-update Annealing Algorithm for Enabling Highly-effective State Transition on Annealing Processors
Akira Hyodo, Satoru Jimbo, Daiki Okonogi, Genta Inoue, Thiem Chua, Masato Motomura, Kazushi Kawamura — Workshop — 2024
Link
An Accurate FPGA-Based ORB Feature Extractor for SLAM with Row-Wise Keypoint Selection
Yuki Ichikawa, Akihiro Shioda, Kazushi Kawamura, Thiem Van Chu, Masato Motomura — International Conference on Consumer Electronics (ICCE) — International Conference — 2024
Classical Thermodynamics-based Parallel Annealing Algorithm for High-speed and Robust Combinatorial Optimization
Kyo Kuroki, Satoru Jimbo, Thiem Van Chu, Masato Motomura, Kazushi Kawamura — The Genetic and Evolutionary Computation Conference (GECCO) — International Conference — 2024
Data centric computing and machine learning
Daichi Fujiki — Workshop — 2024
Efficient Co-Design of Hardware and Algorithms for SLT-based Graph Neural Networks
Jiale Yan, Hiroaki Ito, Kazushi Kawamura, Thiem Van Chu, Daichi Fujiki, Masato Motomura — 6th R-CCS International Symposium — International Conference — 2024
Efficient COO to CSR Conversion for Accelerating Sparse Matrix Processing on FPGA
Yuta Nagahara, Jiale Yan, Kazushi Kawamura, Masato Motomura, Thiem Van Chu — International Conference on Consumer Electronics (ICCE) — International Conference — 2024
Efficient Stereo Visual Odometry on FPGA Featuring On-Chip Map Management and Pipelined Descriptor-Based Block Matching
Yuki Ichikawa, Kazushi Kawamura, Masato Motomura, Thiem Van Chu — IEEE Access — Journal Papers — 2024
ETreeNet: Ensemble Model Fusing Decision Trees and Neural Networks for Small Tabular Data
Tsukasa Yamakura, Kazushi Kawamura, Masato Motomura, Thiem Van Chu — International Joint Conference on Neural Networks (IJCNN) — International Conference — 2024
Exploiting N: M Sparsity in Quantized-Folded ResNets: Signed Multicoat Supermasks and Iterative Pruning-Quantization
Akihiro Shioda, Ángel López García-Arias, Hikari Otsuka, Yuki Ichikawa, Yasuyuki Okoshi, Kazushi Kawamura, Thiem Van Chu, Daichi Fujiki, Masato Motomura — 2024 Twelfth International Symposium on Computing and Networking (CANDAR) — International Conference — 2024
Link
Exploration of Hyperdimensional Computing Using Locality-Sensitive Hashing Mechanism on FPGA
Masato Watanabe, Shungo Kumazawa, Thiem Van Chu, Kazushi Kawamura, Jaehoon Yu, Masato Motomura — International Conference on Consumer Electronics (ICCE) — International Conference — 2024
GPB: An Efficient GBDT Training Method with Tree-Level　Parallelism Using Binary Feature Decomposition
Tsukasa Yamakura, Kazushi Kawamura, Daichi Fujiki, Masato Motomura, Thiem Van Chu — Workshop — 2024
High Throughput Datapath Design for Vision Permutator FPGA Accelerator
Mari Yasunaga, Junnosuke Suzuki, Masato Watanabe, Kazushi Kawamura, Thiem Van Chu, Masato Motomura — International Conference on Consumer Electronics (ICCE) — International Conference — 2024
Memory-efficient Methods for Graph Transformer Using Strong Lottery Tickets Hypothesis
Hiroaki Ito, Jiale Yan, Kazushi Kawamura, Thiem Van Chu, Daichi Fujiki, Masato Motomura — 6th R-CCS International Symposium — International Conference — 2024
OSA-HCIM: On-The-Fly Saliency-Aware Hybrid SRAM CIM with Dynamic Precision Configuration
YC Chen, S Ando, D Fujiki, S Takamaeda-Yamazaki, K Yoshioka — Workshop — 2024
Partially Frozen Random Networks Contain Compact Strong Lottery Tickets
Workshop — 2024
Link
Progressive Variable Precision DNN with Bitwise Ternary Accumulation
Junnosuke Suzuki, Mari Yasunaga, Kazushi Kawamura, Thiem Van Chu, Masato Motomura — International Conference on Artificial Intelligence Circuits and Systems (AICAS) — International Conference — 2024
Ramanujan Edge-Popup: Finding Strong Lottery Tickets with Ramanujan Graph Properties for Efficient DNN Inference Execution
Hikari Otsuka, Yasuyuki Okoshi, Ángel López García-Arias, Kazushi Kawamura, Thiem Van Chu, Masato Motomura — Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI) — International Conference — 2024
Restricted Random Pruning at Initialization for High Compression Range
Hikari Otsuka, Yasuyuki Okoshi, Ángel López García-Arias, Kazushi Kawamura, Thiem Van Chu, Daichi Fujiki, Masato Motomura — Transactions on Machine Learning Research (TMLR) — Journal Papers — 2024
Sparse-Sparse Matrix Multiplication Accelerator on FPGA featuring Distribute-Merge Product Dataflow
Yuta Nagahara, Jiale Yan, Kazushi Kawamura, Masato Motomura, Thiem Van Chu — Asia and South Pacific Design Automation Conference (ASP-DAC) — International Conference — 2024
The Case for Coherence Directories in Memory Cubes
2024 17th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC-2024) — International Conference — 2024
The Trichromatic Strong Lottery Ticket Hypothesis: Neural Compression With Three Primary Supermasks
Ángel López García-Arias, Yasuyuki Okoshi, Hikari Otsuka, Daiki Chijiwa, Yasuhiro Fujiwara, Susumu Takeuchi, Masato Motomura — Workshop — 2024
Link
Toward Improving Ensemble-Based Collaborative Inference at the Edge
Shungo Kumazawa, Jaehoon Yu, Kazushi Kawamura, Thiem Van Chu, Masato Motomura — IEEE Access — Journal Papers — 2024
WhiteDwarf: 12.24 TFLOPS/W 40 nm Versatile Neural Inference Engine for Ultra-Compact Execution of CNNs and MLPs Through Triple Unstructured Sparsity Exploitation and Triple Model Compression
Yasuyuki Okoshi, Ángel López García-Arias, Jaehoon Yu, Junnnosuke Suzuki, Hikari Otsuka, Thiem Van Chu, Kazushi Kawamura, Daichi Fujiki, Masato Motomura — 2024 IEEE Asian Solid-State Circuits Conference (A-SSCC) — International Conference — 2024
Link
パイプライン処理と画像特徴の転用によるSLAMアクセラレータの効率化
Yuki Ichikawa, Kazushi Kawamura, Masato Motomura, Thiem Van Chu — Workshop — 2024
平均場アニーリングに基づく高性能全並列型アニーリングアルゴリズム
Kyo Kuroki, Satoru Jimbo, Thiem Van Chu, Masato Motomura, Kazushi Kawamura — Workshop — 2024
農機シェアリング問題を対象としたスケーラブルなイジングモデル定式化手法
Daiki Okonogi, Satoru Jimbo, Thiem Van Chu, Masato Motomura, Kazushi Kawamura — Workshop — 2024

2023

[Best Paper Nomination] Vector-Processing for Mobile Devices: Benchmark and Analysis
Alireza Khadem, Daichi Fujiki, Nishil Talati, Scott A. Mahlke, Reetuparna Das — IEEE International Symposium on Workload Characterization — International Conference — 2023
[Best Poster Award] Optimized Deep MLP for Tensor Train-based Inference Engine
Jiale Yan, Masato Motomura — IEEE Symposium on Low-Power and High-Speed Chips and Systems (COOL Chips) — International Conference — 2023
[Invited – Keynote] The Future of Low-bitwidth Reconfigurable and Parallel AI Computing
Masato Motomura — Workshop — 2023
[Invited] AI Computing – Tackling the Explosions of Data to Process and Decisions to Make
Masato Motomura — Workshop — 2023
[Invited] AIエッジの今後を展望する
Masato Motomura — Workshop — 2023
[Invited] Pianissimo: A Sub-mW Class DNN Accelerator with Progressive Bit-by-Bit Datapath Architecture for Adaptive Inference at Edge
鈴木 淳之介, 安永 真梨, Ángel López García-Arias, 大越 康之, 熊澤 峻悟, 安藤 洸太, 川村 一志, Thiem Van Chu, 本村 真人 — Workshop — 2023
[Invited] エッジ知能の実現に向けた低ビット幅表現・並列処理AIエンジン群の研究
Masato Motomura — Workshop — 2023
[Invited] 動的再構成プロセッサの研究開発と事業化 及びAI分野への展開
Masato Motomura — Workshop — 2023
[Invited] 問題に応じて計算手法を選択・最適化するアニーリングプロセッサLSI「Amorphica」
Kazushi Kawamura — Workshop — 2023
[Invited] 学習/数理モデルに基づく時空間展開型アーキテクチャの創出と応用プロジェクトの社会実装
Kazushi Kawamura — Workshop — 2023
[Invited] 超高次元分散ベクトル表現を基軸とする 融合型AIコンピューティング基盤の開拓
Masato Motomura — Workshop — 2023
[Invited] 非フォンノイマン・デジタル コンピューティングの研究動向
Masato Motomura — Workshop — 2023
[Keynote] Tackling the Explosions of Data and Solutions with Low-Bitwidth Computing Architectures
Masato Motomura — Workshop — 2023
[優秀ポスター賞-学生部門] アニーリングプロセッサにおける解探索効率化のための動的温度制御法の検討
Genta Inoue, Daiki Okonogi, Thiem Van Chu, Jaehoon Yu, Masato Motomura, Kazushi Kawamura — Workshop — 2023
[優秀構想発表賞] ニューラルネットワークの学習コスト削減に向けた学習前刈込・強い宝くじ仮説の研究
Hikari Otsuka — Workshop — 2023
[研究会優秀講演賞-若手部門] Pianissimo: エッジでの適応的な推論を実現するサブmWクラスDNNアクセラレータ
鈴木 淳之介, 安永 真梨, Ángel López García-Arias, 大越 康之, 熊澤 峻悟, 安藤 洸太, 川村 一志, Thiem Van Chu, 本村 真人 — Workshop — 2023
A Fully-Parallel Annealing Algorithm with Autonomous Pinning Effect Control for Various Combinatorial Optimization Problems
Daiki Okonogi, Satoru Jimbo, Kota Ando, Thiem Van Chu, Jaehoon Yu, Masato Motomura, Kazushi Kawamura — IEICE Transactions on Information and Systems — Journal Papers — 2023
A Highly Accurate and Parallel Vision MLP FPGA Accelerator based on FP7/8 SIMD Operations
Mari Yasunaga, Junnosuke Suzuki, Masato Watanabe, Kazushi Kawamura, Thiem Van Chu, Jaehoon Yu, Masato Motomura — International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC) — International Conference — 2023
Amorphica: 4-Replica 512 Fully Connected Spin 336MHz Metamorphic Annealer with Programmable Optimization Strategy and Compressed-Spin-Transfer Multi-Chip Extension
Kazushi Kawamura, Jaehoon Yu, Daiki Okonogi, Satoru Jimbo, Genta Inoue, Akira Hyodo, Ángel López García-Arias, Kota Ando, Bruno Hideki Fukushima-Kimura, Ryota Yasudo, Thiem Van Chu, Masato Motomura — International Solid-State Circuits Conference (ISSCC) — International Conference — 2023
Decision Forest Training Accelerator Based on Binary Feature Decomposition
Thiem Van Chu, Yu Mizutani, Yuta Nagahara, Shungo Kumazawa, Kazushi Kawamura, Jaehoon Yu, Masato Motomura — International Symposium on Field-Programmable Custom Computing Machines (FCCM) — International Conference — 2023
Flexibly Controllable Dynamic Cooling Methods for Solid-State Annealing Processors to Improve Combinatorial Optimization Performance
Genta Inoue, Daiki Okonogi, Thiem Van Chu, Jaehoon Yu, Masato Motomura, Kazushi Kawamura — IEEE Symposium on Low-Power and High-Speed Chips and Systems, COOL Chips 26 — International Conference — 2023
FP8 SIMD演算に基づく高精度・高並列なFPGA向けNNアクセラレータ
安永 真梨, 鈴木 淳之介, 川村 一志, Thiem Van Chu, 本村 真人, 劉 載勲 — Workshop — 2023
Mixing time and simulated annealing for the stochastic cellular automata
Bruno Hideki Fukushima-Kimura, Satoshi Handa, Katsuhiro Kamakura, Yoshinori Kamijima, Kazushi Kawamura, Akira Sakai — Journal of Statistical Physics — Journal Papers — 2023
DOI
Multicoated and Folded Graph Neural Networks with Strong Lottery Tickets
Jiale Yan, Hiroaki Ito, Ángel López García-Arias, Yasuyuki Okoshi, Hikari Otsuka, Kazushi Kawamura, Thiem Van Chu, Masato Motomura — Learning on Graph Conference 2023 — International Conference — 2023
DOILink
MVC: Enabling Fully Coherent Multi-Data-Views through the Memory Hierarchy with Processing in Memory
Daichi Fujiki — Proceedings of the 56th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO 2023) — International Conference — 2023
Pianissimo: A Sub-mW Class DNN Accelerator with Progressive Bit-by-Bit Datapath Architecture for Adaptive Inference at Edge
Junnosuke Suzuki, Jaehoon Yu, Mari Yasunaga, Ángel López García-Arias, Yasuyuki Okoshi, Shungo Kumazawa, Kota Ando, Kazushi Kawamura, Thiem Van Chu, Masato Motomura — Symposium on VLSI Technology and Circuits, 2023 — International Conference — 2023
Pianissimo: A Sub-mW Class DNN Accelerator With Progressively Adjustable Bit-Precision
Junnosuke Suzuki, Jaehoon Yu, Mari Yasunaga, Ángel López García-Arias, Yasuyuki Okoshi, Shungo Kumazawa, Kota Ando, Kazushi Kawamura, Thiem Van Chu, Masato Motomura — IEEE Access — Journal Papers — 2023
Recurrent Residual Networks Contain Stronger Lottery Tickets
Ángel López García-Arias, Yasuyuki Okoshi, Masanori Hashimoto, Masato Motomura, Jaehoon Yu — IEEE Access — Journal Papers — 2023
DOI
Stochastic optimization: Glauber dynamics versus stochastic cellular automata
Bruno Hideki Fukushima-Kimura, Yoshinori Kamijima, Kazushi Kawamura, Akira Sakai — Transactions of the Institute of Systems, Control and Information Engineers — Journal Papers — 2023
DOI
TT-MLP: Tensor Train Decomposition on Deep MLPs
Jiale Yan, Kota Ando, Jaehoon Yu, Masato Motomura — IEEE Access — Journal Papers — 2023
DOI
同変性ネットワークに基づく自律走行向け強化学習手法
塩田 晃弘, 市川 雄樹, 川村 一志, Thiem Van Chu, 本村 真人, 劉 載勲 — Workshop — 2023
強い宝くじ仮説に基づく超軽量物体検出ニューラルネットワーク
大塚 光莉, 大越 康之, Ángel López García-Arias, 川村 一志, Thiem Van Chu, 劉載勲, 本村 真人 — Workshop — 2023
表形式データを対象とした決定木とニューラルネットワークの融合型機械学習手法の研究
山倉 司, 川村 一志, 本村 真人, Thiem Van Chu — Workshop — 2023

2022

[Invited] AI Algorithm Innovation Calls for Innovative AI Accelerator Designs
Masato Motomura — Workshop — 2022
[Invited] AI－コンピューティング－集積回路:技術変革のうねりとその未来
本村 真人 — Workshop — 2022
[Invited] Exploring AI Computing Architectures Toward Future SoC
Masato Motomura — Workshop — 2022
[Invited] Hiddenite: CNN Inference Accelerator for Randomly Weighted Neural Networks
Jaehoon Yu — Workshop — 2022
[Invited] Hiddenite: オンチップモデル構築を用いる隠れニューラルネットワーク理論の推論テンソルエンジン
廣瀨 一俊 — Workshop — 2022
[Invited] HotChips2021にみる機械学習アクセラレータの動向：東工大DNN推論アクセラレータの発表内容紹介，及びその他の同分野発表サマリ
本村 真人 — Workshop — 2022
[Invited] エッジAIの現状と展望: アルゴリズムと ハードウェアの協創の観点から
本村 真人 — Workshop — 2022
[Invited] データ再利用性を考慮した高効率CNN推論アーキテクチャ
劉 載勲 — Workshop — 2022
[Invited] 動的再構成プロセッサの研究開発と事業化 及びAI分野への展開
本村 真人 — Workshop — 2022
[Invited] 学習/数理モデルに基づく時空間展開型アーキテクチャ
本村 真人 — Workshop — 2022
[Invited] 学習/数理モデルに基づく時空間展開型アーキテクチャの創出と応用
本村 真人 — Workshop — 2022
[Invited] 構造型情報処理に関する先駆的研究とそのAI情報処理への展開
本村 真人 — Workshop — 2022
[Invited] 構造型情報処理基盤の確立を目指して
劉 載勲 — Workshop — 2022
[Invited] 特徴空間事前分割型決定森推論アクセラレータ
Thiem Van Chu — Workshop — 2022
[Invited] 知能コンピューティングを加速するアーキテクチャ基盤技術
本村 真人 — Workshop — 2022
[Invited] 隠れネットワーク理論に基づく新たなDNN推論エンジンチップ(Hiddenite)の紹介
本村 真人 — Workshop — 2022
[Keynote] Exploring AI Computing Architectures Toward Future SoC
Masato Motomura — Workshop — 2022
[WIP最優秀賞] 2スピン同時フリップを並列試行可能なシミュレーテッドアニーリング手法の検討
兵藤 旭, 神保 聡, Thiem Van Chu, 劉 載勲, 本村 真人, 川村 一志 — Workshop — 2022
[第22回山﨑貞一賞-半導体及びシステム・情報・エレクトロニクス分野] 動的再構成プロセッサの研究開発と事業化及びAI分野への展開
本村 真人 — Workshop — 2022
[第54回市村学術賞 功績賞] 構造型情報処理に関する先駆的研究とそのAI処理分野への展開
本村 真人 — Workshop — 2022
A Hybrid Integer Encoding Method for Obtaining High-quality Solutions of Quadratic Knapsack Problems on Solid-state Annealers
Satoru Jimbo, Daiki Okonogi, Kota Ando, Thiem Van Chu, Jaehoon Yu, Masato Motomura, Kazushi Kawamura — IEICE Transactions on Information and Systems — Journal Papers — 2022
A Unhealthy Plant Identification System Using a Generative Adversarial Network
Satida Sookpong, Teerasit Kasetkasem, Teera Phatrapornnant, Jaehoon Yu — International Conference on Electrical Engineering/Electronics, Computer, Telecommunications and Information Technology (ECTI-CON) — International Conference — 2022
Hiddenite: 4K-PE Hidden Network Inference 4D-Tensor Engine Exploiting On-Chip Model Construction Achieving 34.8-to-16.0TOPS/W for CIFAR-100 and ImageNet
Kazutoshi Hirose, Jaehoon Yu, Kota Ando, Yasuyuki Okoshi, Ángel López García-Arias, Junnosuke Suzuki, Thiem Van Chu, Kazushi Kawamura, Masato Motomura — International Solid-State Circuits Conference (ISSCC) — International Conference — 2022
IEEE Fellow “for contributions to memory-logic integration of reconfigurable chip architecture.”
Masato Motomura — Workshop — 2022
Investigating Small Device Implementation of FRET-based Optical Reservoir Computing
Masafumi Tanaka, Jaehoon Yu, Masaki Nakagawa, Naoya Tate, Masanori Hashimoto — The IEEE International Midwest Symposium on Circuits and Systems (MWSCAS) — International Conference — 2022
Multicoated Supermasks Enhance Hidden Networks
Yasuyuki Okoshi, Ángel López García-Arias, Kazutoshi Hirose, Kota Ando, Kazushi Kawamura, Thiem Van Chu, Masato Motomura, Jaehoon Yu — International Conference on Machine Learning (ICML) — International Conference — 2022
QKP-QUBO変換におけるHybridエンコーディング方式
神保 聡, 小此木 大輝, 安藤 洸太, Thiem Van Chu, 劉 載勲, 本村 真人, 川村 一志 — Workshop — 2022
Via-switch FPGA with transistor-free programmability enabling energy-efficient near-memory parallel computation
Masanori Hashimoto, X Bai, Naoki Banno, Munehiro Tada, Toshitsugu Sakamoto, Jaehoon Yu, Ryutaro Doi, Hidetoshi Onodera, Takashi Imagawa, Hiroyuki Ochi — Japanese Journal of Applied Physics — Journal Papers — 2022
DOI
イジング計算機の解探索を効率化させる整数エンコーディング手法の提案と評価
神保 聡, 小此木 大輝, Thiem Van Chu, 劉 載勲, 本村 真人, 川村 一志 — Workshop — 2022
ピンニングパラメータの自律制御機構を搭載した全スピン並列更新アニーリング マシン
小此木 大輝, 神保 聡, Thiem Van Chu, 劉 載勲, 本村 真人, 川村 一志 — Workshop — 2022
全並列アニーリングのための自律的パラメータ制御
小此木 大輝, 神保 聡, 安藤 洸太, Thiem Van Chu, 劉 載勲, 本村 真人, 川村 一志 — Workshop — 2022
外部メモリアクセス抑制による高効率疎行列積アクセラレータの研究
永原 雄大, 安藤 洸太, 川村 一志, 劉 載勲, 本村 真人, Thiem Van Chu — Workshop — 2022
巡回セールスマン問題を対象とした並列アニーリング手法の評価
井上 源太, 小此木 大輝, Thiem Van Chu, 劉 載勲, 本村 真人, 川村 一志 — Workshop — 2022

2021

[Best Paper Award] A High-Performance and Flexible FPGA Inference Accelerator for Decision Forests Based on Prior Feature Space Partitioning
Thiem Van Chu, Ryuichi Kitajima, Kazushi Kawamura, Jaehoon Yu, Masato Motomura — International Conference on Field-Programmable Technology (FPT) — International Conference — 2021
[Invited] AIチップの現状と今後について
本村 真人 — Workshop — 2021
[Invited] CGRAs for Broad Embedded Market & for Neural Networks
Masato Motomura — Workshop — 2021
[Invited] LSI技術が開く構造型情報処理の新展開
本村 真人 — Workshop — 2021
[Invited] ポストノイマン・ポストムーア時代の情報処理アーキテクチャ
本村 真人 — Workshop — 2021
[Invited] ⼆値・三値・量⼦化ニューラルネットワークの推論LSIと学習アルゴリズム
安藤 洸太 — Workshop — 2021
[Invited] 全結合・全並列型アニーリングHWの紹介 ～ その数理モデルからLSI実装まで ～
本村 真人 — Workshop — 2021
[Moderator] “Hot” Techs for “Cool” AI Computing: Do We have Enough Tricks?
Masato Motomura — Workshop — 2021
[セッション特別賞] GPUを活用した全結合・全並列アニーリング手法の高速化検討
大川 開生, 川村 一志, Gregory Gutmann, Thiem Van Chu, 劉 載勲, 本村 真人 — Workshop — 2021
[優秀構想発表賞] 多ビットマスクを用いた高精度・軽量HNNの研究
大越 康之 — Workshop — 2021
A 96-MB 3D-Stacked SRAM Using Inductive Coupling with 0.4-V Transmitter, Termination Scheme and 12:1 SerDes in 40-nm CMOS
Kota Shiba, Tatsuo Omori, Kodai Ueyoshi, Kota Ando, Kazutoshi Hirose, Shinya Takamaeda-Yamazaki, Masato Motomura, Mototsugu Hamada, Tadahiro Kuroda — IEEE Transactions on Circuits and Systems I — Journal Papers — 2021
Edge Inference Engine for Deep & Random Sparse Neural Networks with 4-bit Cartesian-Product MAC Array and Pipelined Activation Aligner
Kota Ando, Jaehoon Yu, Kazutoshi Hirose, Hiroki Nakahara, Kazushi Kawamura, Thiem Van Chu, Masato Motomura — Hot Chips 33 (Poster) — International Conference — 2021
ExtraFerns: Fully Parallel Ensemble Learning Technique with Random Projection and Non-Greedy yet Minimal Memory Access Training
Shungo Kumazawa, Kazushi Kawamura, Thiem Van Chu, Masato Motomura, Jaehoon Yu — International Journal of Networking and Computing — Journal Papers — 2021
Hidden-Fold Networks: Random Recurrent Residuals Using Sparse Supermasks
Ángel López García-Arias, Masanori Hashimoto, Masato Motomura, Jaehoon Yu — The British Machine Vision Conference (BMVC) — International Conference — 2021
MUX Granularity-Oriented Iterative Technology Mapping for Implementing Compute-Intensive Applications on Via-Switch FPGA
Takashi Imagawa, Jaehoon Yu, Masanori Hashimoto, Hiroyuki Ochi — Design, Automation and Test in Europe Conference (DATE) — International Conference — 2021
ProgressiveNN: Achieving Computational Scalability with Dynamic Bit-Precision Adjustment by MSB-first Accumulative Computation
Junnosuke Suzuki, Tomohiro Kaneko, Kota Ando, Kazutoshi Hirose, Kazushi Kawamura, Thiem Van Chu, Masato Motomura, Jaehoon Yu — International Journal of Networking and Computing — Journal Papers — 2021
こんなとこにもイジングマシン
雑誌記事 — Books — 2021
スマホやロボットなどで高効率なAI処理を行うプロセッサーアーキテクチャーを開発
東工大プレスリリース — Books — 2021
Link
ビットスケーラブルCNNにおける計算量・精度トレードオフ制御手法の検討
鈴木 淳之介, 安藤 洸太, 廣瀬 一俊, 川村 一志, Thiem Van Chu, 本村 真人, 劉載勲 — Workshop — 2021
乱数生成ノードの並列閾値最適化に基づくエッジ指向決定木アンサンブル学習
熊澤 峻悟, 川村 一志, Thiem Van Chu, 本村 真人, 劉載勲 — Workshop — 2021
入力空間のランダム射影と分割に基づくFernアンサンブル学習
熊澤 峻悟, 川村 一志, Thiem Van Chu, 本村 真人, 劉載勲 — Workshop — 2021
学習/数理モデルに基づく時空間展開型アーキテクチャの創出と応用
本村 真人 — Workshop — 2021
対称二進表現に基づくビットスケーラブルCNN推論手法
鈴木 淳之介, 安藤 洸太, 廣瀬 一俊, 川村 一志, Thiem Van Chu, 本村 真人, 劉載勲 — Workshop — 2021
特徴空間事前分割に基づく決定木アンサンブルのFPGA推論アクセラレータ
北島 龍一, 川村 一志, 劉 載勲, 本村 真人, Thiem Van Chu — Workshop — 2021

2020

[IEEE CS Tokyo/Japan Joint Local Chapters Young Author Award 2022] SeedEx: A Genome Sequencing Accelerator for Optimal Alignments in Subminimal Space
Daichi Fujiki, Shunhao Wu, Nathan Ozog, Kush Goliya, David T. Blaauw, Satish Narayanasamy, Reetuparna Das — International Symposium on Microarchitecture (MICRO) — International Conference — 2020
[Invited] Designing AI Accelerator Chips for the Smarter Future
Masato Motomura — Workshop — 2020
[Invited] Domain-Specific Architectures for Boosting “Compute for Intelligence”
Masato Motomura — Workshop — 2020
[Invited] Reconfigurable and Domain-Specific Hardware for AI Computing
Masato Motomura — Workshop — 2020
[Invited] Stochastic Cellular Automata Annealing (SCA) and its Non-Quantum Silicon Chip Implementation
Masato Motomura — Workshop — 2020
[Invited] Stochastic Cellular Automata Annealing (SCA) and its Non-Quantum Silicon Chip Implementation: Realizing Fully-Parallel Spin-Updates for Fully-Connected Spin Systems
Masato Motomura — Workshop — 2020
[Invited] 学習/数理モデルに基づく時空間展開型アーキテクチャ
本村 真人 — Workshop — 2020
[優秀構想発表賞] エッジAIのための推論精度と計算量のトレードオフ向上に関する研究
鈴木 淳之介 — Workshop — 2020
[優秀若手発表賞] 二値化ニューラルネットワークのハードウェア指向精度向上手法の検討
大羽 由華, 村上 大輔, 中江 達哉, 安藤 洸太, 浅井 哲也, 本村 真人, 高前田 伸也 — Workshop — 2020
[優秀講演賞] 無効ニューロン予測によるDNN計算効率化手法
植吉 晃大, 池田 泰我, 安藤 洸太, 廣瀨 一俊, 浅井 哲也, 高前田 伸也, 本村 真人 — Workshop — 2020
[若手奨励賞] 効率的なDNN計算のための無効ニューロン予測手法の評価
池田 泰我, 植吉 晃大, 安藤 洸太, 廣瀨 一俊, 浅井 哲也, 本村 真人, 高前田 伸也 — Workshop — 2020
A 3D-Stacked SRAM Using Inductive Coupling with Low-Voltage Transmitter and 12:1 SerDes
Kota Shiba, Tatsuo Omori, Kodai Ueyoshi, Kota Ando, Kazutoshi Hirose, Shinya Takamaeda-Yamazaki, Masato Motomura, Mototsugu Hamada, Tadahiro Kuroda — IEEE International Symposium on Circuits and Systems (ISCAS) — International Conference — 2020
A Hardware-Efficient Weight Sampling Circuit for Bayesian Neural Networks
Yuki Hirayama, Tetsuya Asai, Masato Motomura, Shinya Takamaeda-Yamazaki — International Journal of Networking and Computing — Journal Papers — 2020
Dependency-Driven Trace-Based Network-on-Chip Emulation on FPGAs
Thiem Van Chu, Kenji Kise, Kiyofumi Tanaka — ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA) — International Conference — 2020
ExtraFerns: Fully Parallel Ensemble Learning Technique with Non-Greedy yet Minimal Memory Access Training
Shungo Kumazawa, Kazushi Kawamura, Thiem Van Chu, Masato Motomura, Jaehoon Yu — International Symposium on Computing and Networking (CANDAR) — International Conference — 2020
Hardware/Algorithm Co-optimization for Fully-Parallelized Compact Decision Tree Ensembles on FPGAs
Taiga Ikeda, Kento Sakurada, Atsuyoshi Nakamura, Masato Motomura, Shinya Takamaeda-Yamazaki — International Symposium on Applied Reconfigurable Computing (ARC) — International Conference — 2020
Logarithm-Approximate Floating-Point Multiplier is Applicable to Power-Efficient Neural Network Training
Tai-Yu Cheng, Yukata Masuda, Jun Chen, Jaehoon Yu, Masanori Hashimoto — Integration — Journal Papers — 2020
Low-Cost Reservoir Computing using Cellular Automata and Random Forests
Ángel López García-Arias, Jaehoon Yu, Masanori Hashimoto — IEEE International Symposium on Circuits and Systems (ISCAS) — International Conference — 2020
Memory Efficient Training using Lookup-Table-based Quantization for Neural Network
Kazuki Onishi, Jaehoon Yu, Masanori Hashimoto — IEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS) — International Conference — 2020
Novel Annealing Processor Is the Best Ever at Solving Combinatorial Optimization Problems
IEEE Spectrum — Books — 2020
Link
ProgressiveNN: Achieving Computational Scalability without Network Alteration by MSB-first Accumulative Computation
Junnosuke Suzuki, Kota Ando, Kazutoshi Hirose, Kazushi Kawamura, Thiem Van Chu, Masato Motomura, Jaehoon Yu — International Symposium on Computing and Networking (CANDAR) — International Conference — 2020
Q&Aで分かるAIチップ
本村 真人(監修) — Books — 2020
Real-time Tone Mapping: A State of the Art Report
Yafei Ou, Prasoon Ambalathankandy, Masayuki Ikebe, Shinya Takamaeda, Masato Motomura, Tetsuya Asai — IEEE Transactions on Circuits and Systems for Video Technology — Journal Papers — 2020
Selective Fine-Tuning on a Classifier Ensemble: Realizing Adaptive Neural Networks With a Diversified Multi-Exit Architecture
Kazutoshi Hirose, Shinya Takamaeda-Yamazaki, Jaehoon Yu, Masato Motomura — IEEE Access — Journal Papers — 2020
STATICA: A 512-Spin 0.25M-Weight Annealing Processor With an All-Spin-Updates-at-Once Architecture for Combinatorial Optimization With Complete Spin-Spin Interactions
Kasho Yamamoto, Kazushi Kawamura, Kota Ando, Normann Mertig, Takashi Takemoto, Masanao Yamaoka, Hiroshi Teramoto, Akira Sakai, Shinya Takamaeda-Yamazaki, Masato Motomura — IEEE Journal of Solid-State Circuits (JSSC) — Journal Papers — 2020
STATICA: A 512-Spin 0.25M-Weight Full-Digital Annealing Processor with a Near-Memory All-Spin-Updates-at-Once Architecture for Combinatorial Optimization with Complete Spin-Spin Interactions
Kasho Yamamoto, Kota Ando, Normann Mertig, Takashi Takemoto, Masanao Yamaoka, Hiroshi Teramoto, Akira Sakai, Shinya Takamaeda-Yamazaki, Masato Motomura — International Solid-State Circuits Conference (ISSCC) — International Conference — 2020
Via-Switch FPGA: 65nm CMOS Implementation and Architecture Extension for AI Applications
Masanori Hashimoto, Xu Bai, Naoki Banno, Munehiro Tada, Toshitsugu Sakamoto, Jaehoon Yu, Ryutaro Doi, Yusuke Araki, Hidetoshi Onodera, Takashi Imagawa, Hiroyuki Ochi, Kazutoshi Wakabayashi, Yukio Mitsuyama, Tadahiko Sugibayashi — International Solid-State Circuits Conference (ISSCC) — International Conference — 2020
深層ニューラルネットワーク向けプロセッサ技術の実例と展望
本村 真人, 高前田 伸也, 植吉 晃大, 安藤 洸太, 廣瀨 一俊 — 電子情報通信学会和文論文誌C — Journal Papers — 2020
組合せ最適化問題を高速に解く新しいアニーリングマシンを開発
東工大プレスリリース — Books — 2020
Link

2019

[2019年度研究会優秀賞] 決定論的変分推論に基づくベイジアンCNNの検討
平山 侑樹, 浅井 哲也, 本村 真人, 高前田 伸也 — Workshop — 2019
[Invited] AI Computing: The Promised Land for Computer Architecture Innovation?
Masato Motomura — Workshop — 2019
[Invited] AI Computing: The Promised Land for Hardware?
Masato Motomura — Workshop — 2019
[Invited] AIチップ: 世界の研究動向と東工大の研究戦略
本村 真人 — Workshop — 2019
[Invited] AIチップの世界動向と日本がとるべき戦略
本村 真人 — Workshop — 2019
[Invited] AI関連半導体技術の動向
本村 真人 — Workshop — 2019
[Invited] Intelligence at the Edge: Frontiers for Energy-Efficient Hardware Architectures
Masato Motomura — Workshop — 2019
[Tutorial] AI Computing: What it is about & How hardware can help it out
Masato Motomura — Workshop — 2019
[若手優秀講演賞] 効率的なDNN計算のための無効ニューロン予測手法の評価
池田 泰我, 植吉 晃大, 安藤 洸太, 廣瀨 一俊, 浅井 哲也, 本村 真人, 高前田 伸也 — Workshop — 2019
A Resource-Efficient Weight Sampling Method for Bayesian Neural Networks Accelerators
Yuki Hirayama, Tetsuya Asai, Masato Motomura, Shinya Takamaeda-Yamazaki — International Symposium on Computing and Networking (CANDAR) — International Conference — 2019
A Study on a Low Power Optimization Algorithm for An Edge-AI Device
Tatsuya Kaneko, Kentaro Orimo, Itaru Hida, Shinya Takamaeda-Yamazaki, Masayuki Ikebe, Masato Motomura, Tetsuya Asai — Nonlinear Theory and Its Applications — Journal Papers — 2019
AIエッジコンピューティングへの希望と展望
本村 真人 — Books — 2019
AIエッジコンピューティングへの希望と展望
本村 真人 — Books — 2019
An Adaptive Global and Local Tone Mapping Algorithm Implemented on FPGA
Prasoon Ambalathankandy, Masayuki Ikebe, Takashi Yoshida, Takeshi Shimada, Shinya Takamaeda-Yamazaki, Masato Motomura, Tetsuya Asai — IEEE Transactions on Circuits and Systems for Video Technology — Journal Papers — 2019
Approach to Reservoir Computing with Schmitt Trigger Oscillator-Based Analog Neural Circuits
Seunggoo Rim, Shunya Suzuki, Shinya Takamaeda-Yamazaki, Masayuki Ikebe, Masato Motomura, Tetsuya Asai — Japan-Korea Joint Workshop on Complex Communication Sciences — International Conference — 2019
DeltaNet: Differential Binary Neural Network
Yuka Oba, Kota Ando, Tetsuya Asai, Masato Motomura, Shinya Takamaeda-Yamazaki — IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP) — International Conference — 2019
Distilling Knowledge for Non-Neural Networks
Shota Fukui, Jaehoon Yu, Masanori Hashimoto — Asia-Pacific Signal and Information Processing Association (APSIPA) — International Conference — 2019
Dither NN: Hardware/Algorithm Co-Design for Accurate Quantized Neural Networks
Kota Ando, Kodai Ueyoshi, Yuka Oba, Kazutoshi Hirose, Ryota Uematsu, Takumi Kudo, Masayuki Ikebe, Tetsuya Asai, Shinya Takamaeda-Yamazaki, Masato Motomura — IEICE Transactions on Information and Systems — Journal Papers — 2019
Experimental Demonstration of Physical Reservoir Computing with Nonlinear Electronic Devices
Shunya Suzuki, Seunggoo Rim, Shinya Takamaeda-Yamazaki, Masayuki Ikebe, Masato Motomura, Tetsuya Asai — RISP International Workshop on Nonlinear Circuits, Communications and Signal Processing — International Conference — 2019
FPGA-Based Annealing Processor with Time-Division Multiplexing
Kasho Yamamoto, Masayuki Ikebe, Tetsuya Asai, Masato Motomura, Shinya Takamaeda-Yamazaki — IEICE Transactions on Information and Systems — Journal Papers — 2019
FPGA-Based FORCE Learning Accelerator towards Real-Time Online Reservoir Computing
Koyo Minamikawa, Shinya Takamaeda-Yamazaki, Masayuki Ikebe, Masato Motomura, Tetsuya Asai — RISP International Workshop on Nonlinear Circuits, Communications and Signal Processing — International Conference — 2019
Hardware-Oriented Algorithm and Architecture for Generative Adversarial Networks
Tatsuya Kaneko, Masayuki Ikebe, Shinya Takamaeda-Yamazaki, Masato Motomura, Tetsuya Asai — Journal of Signal Processing — Journal Papers — 2019
Hardware-Oriented Algorithm and Architecture for Generative Adversarial Networks
Tatsuya Kaneko, Masayuki Ikebe, Shinya Takamaeda-Yamazaki, Masato Motomura, Tetsuya Asai — RISP International Workshop on Nonlinear Circuits, Communications and Signal Processing — International Conference — 2019
LEF: An Effective Routing Algorithm for Two-Dimensional Meshes
Thiem Van Chu, Kenji Kise — IEICE Transactions on Information and Systems — Journal Papers — 2019
Minimizing Energy for Neural Network Training with Logarithm-Approximate Floating-Point Multiplier
Tai-Yu Cheng, Jaehoon Yu, Masanori Hashimoto — International Symposium on Power and Timing Modeling, Optimization and Simulation — International Conference — 2019
Parallelism-Flexible Convolution Core for Sparse Convolutional Neural Networks on FPGA
Salita Sombatsiri, Seiya Shibata, Yuki Kobayashi, Hiroaki Inoue, Takashi Takenaka, Takeo Hosomi, Jaehoon Yu, Yoshinori Takeuchi — Journal Papers — 2019
QUEST: Multi-Purpose Log-Quantized DNN Inference Engine Stacked on 96-MB 3-D SRAM Using Inductive Coupling Technology in 40-nm CMOS
Kodai Ueyoshi, Kota Ando, Kazutoshi Hirose, Shinya Takamaeda-Yamazaki, Mototsugu Hamada, Tadahiro Kuroda, Masato Motomura — IEEE Journal of Solid-State Circuits — Journal Papers — 2019
Radiography Contrast Enhancement: Smoothed LHE Filter, a Practical Solution for Digital X-rays with Mach Band
Prasoon Ambalathankandy, Yafei Ou, Jyotsna Kochiyil, Shinya Takamaeda-Yamazaki, Masato Motomura, Tetsuya Asai, Masayuki Ikebe — International Conference on Digital Image Computing: Techniques and Applications — International Conference — 2019
Sneak Path Free Reconfiguration with Minimized Programming Steps for Via-switch Crossbar Based FPGA
Ryutaro Doi, Jaehoon Yu, Masanori Hashimoto — IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems — Journal Papers — 2019
Ternarized Backpropagation: A Hardware-Oriented Optimization Algorithm for Edge-Oriented AI Devices
Tatsuya Kaneko, Masayuki Ikebe, Shinya Takamaeda-Yamazaki, Masato Motomura, Tetsuya Asai — RIEC International Symposium on Brain Functions and Brain Computer — International Conference — 2019
Training Data Reduction using Support Vectors for Neural Networks
Toranosuke Tanio, Kouya Takeda, Jaehoon Yu, Masanori Hashimoto — Asia-Pacific Signal and Information Processing Association (APSIPA) — International Conference — 2019
コンピューティングアーキテクチャ
本村 真人 — Books — 2019
深層学習プロセッサの展望
本村 真人 — Books — 2019

2018

[Best Paper Nomination] AxNoC: Low-power Approximate Network-on-Chips using Critical-Path Isolation
Akram Ben Ahmed, Daichi Fujiki, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano — International Symposium on Networks-on-Chip (NOCS) — International Conference — 2018
[Invited] Hardware-Oriented Approaches for Accelerating “AI” Workloads
Masato Motomura — Workshop — 2018
[Invited] Intelligence at the Edge: Frontiers for Energy-Efficient Hardware Architectures
Masato Motomura — Workshop — 2018
[Invited] Structure-Oriented Computing: Where Software Redefines Hardware Architecture
Masato Motomura — Workshop — 2018
A Novel Iris-Center Detection Algorithm towards Gaze Estimation Targeting Molecular Cellular Automata
Naoto Iwamaru, Shinya Takamaeda-Yamazaki, Masayuki Ikebe, Masato Motomura, Tetsuya Asai — International Workshop on Molecular Architectonics — International Conference — 2018
A Study on Ternary Back Propagation Algorithm for Embedded Egde-AI Processing
Tatsuya Kaneko, Masayuki Ikebe, Shinya Takamaeda-Yamazaki, Masato Motomura, Tetsuya Asai — Joint Workshop of UCL-ICN, NTT, UCL-Gatsby and AIBS: Analysis and Synthesis for Human/Artificial Cognition and Behaviour — International Conference — 2018
Adapting Soft Cascade to MAC Operations of Convolutional Neural Networks
Kenshi Ito, Jaehoon Yu, Masanori Hashimoto — International Symposium on Multimedia and Communication Technology — International Conference — 2018
Analysis of Smoothed LHE Methods for Processing Images with Optical Illusions
Prasoon Ambalathankandy, Takeshi Shimada, Shinya Takamaeda-Yamazaki, Masato Motomura, Tetsuya Asai, Masayuki Ikebe — IEEE International Conference on Visual Communications and Image Processing — International Conference — 2018
Area and Energy Optimization for Bit-Serial Log-Quantized DNN Accelerator with Shared Accumulators
Takumi Kudo, Kodai Ueyoshi, Kota Ando, Kazutoshi Hirose, Ryota Uematsu, Yuka Oba, Masayuki Ikebe, Tetsuya Asai, Masato Motomura, Shinya Takamaeda-Yamazaki — IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip — International Conference — 2018
BRein Memory: A Single-Chip Binary/Ternary Reconfigurable In-Memory Deep Neural Network Accelerator Achieving 1.4TOPS at 0.6W
Kota Ando, Kodai Ueyoshi, Kentaro Orimo, Haruyoshi Yonekawa, Shimpei Sato, Hiroki Nakahara, Shinya Takamaeda-Yamazaki, Masayuki Ikebe, Tetsuya Asai, Tadahiro Kuroda, Masato Motomura — IEEE Journal of Solid-State Circuits — Journal Papers — 2018
Decomposed Vector Histograms of Oriented Gradients for Efficient Hardware Implementation
Koichi Mitsunari, Yoshinori Takeuchi, Masaharu Imai, Jaehoon Yu — IEICE_J_FECACS — Journal Papers — 2018
Dither NN: An Accurate Neural Network with Dithering for Low Bit-Precision Hardware
Kota Ando, Kodai Ueyoshi, Yuka Oba, Kazutoshi Hirose, Ryota Uematsu, Takumi Kudo, Masayuki Ikebe, Tetsuya Asai, Shinya Takamaeda-Yamazaki, Masato Motomura — International Conference on Field-Programmable Technology (FPT) — International Conference — 2018
Exploring CNN Accelerator Design Space on a Dynamically Reconfigurable Hardware Platform
Ryota Uematsu, Kota Ando, Kodai Ueyoshi, Kazutoshi Hirose, Masayuki Ikebe, Tetsuya Asai, Shinya Takamaeda-Yamazaki, Masato Motomura — Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI) — International Conference — 2018
Hardware Architecture for Fast General Object Detection Using Aggregated Channel Features
Koichi Mitsunari, Jaehoon Yu, Masanori Hashimoto — International Conference — 2018
Hardware Architecture for High-Speed Object Detection Using Decision Tree Ensemble
Koichi Mitsunari, Jaehoon Yu, Takao Onoye, Masanori Hashimoto — IEICE_J_FECACS — Journal Papers — 2018
Interconnect Delay Analysis for RRAM Crossbar Based FPGA
Masanori Hashimoto, Yuki Nakazawa, Jaehoon Yu — IEEE Computer Society Annual Symposium on VLSI (ISVLSI) — International Conference — 2018
Interconnect Delay Analysis for RRAM Crossbar Based FPGA
Masanori Hashimoto, Yuki Nakazawa, Ryutaro Doi, Jaehoon Yu — International Conference — 2018
New Generation Dynamically Reconfigurable Processor Technology for Accelerating Embedded AI Applications
Taro Fujii, Takao Toi, Teruhito Tanaka, Katsumi Togawa, Toshiro Kitaoka, Kengo Nishino, Noritsugu Nakamura, Hiroki Nakahara, Masato Motomura — Symposia on VLSI Technology and Circuits — International Conference — 2018
Phase Locking Value Calculator based on Hardware-oriented Mathematical Expression
Tomoki Sugiura, Jaehoon Yu, Yoshinori Takeuchi — Journal Papers — 2018
Proto-Computing Architecture over A Digital Medium Aiming at Real-Time Video Processing
Aoi Tanibata, Alexandre Schmid, Shinya Takamaeda-Yamazaki, Masayuki Ikebe, Masato Motomura, Tetsuya Asai — Complexity — Journal Papers — 2018
Quantization Error-Based Regularization for Hardware-Aware Neural Network Training
Kazutoshi Hirose, Ryota Uematsu, Kota Ando, Kodai Ueyoshi, Masayuki Ikebe, Tetsuya Asai, Masato Motomura, Shinya Takamaeda-Yamazaki — Nonlinear Theory and Its Applications — Journal Papers — 2018
QUEST: A 7.49-TOPS Multi-Purpose Log-Quantized DNN Inference Engine Stacked on 96MB 3D SRAM using Inductive-Coupling Technology in 40nm CMOS
Kodai Ueyoshi, Kota Ando, Kazutoshi Hirose, Shinya Takamaeda-Yamazaki, Junichiro Kadomoto, Tomoki Miyata, Mototsugu Hamada, Tadahiro Kuroda, Masato Motomura — International Solid-State Circuits Conference (ISSCC 2018) — International Conference — 2018
Real-time HDTV to 4K and 8K-UHD Conversions Using Anti-Aliasing Based Super Resolution Algorithm on FPGA
Prasoon Ambalathankandy, Shinya Takamaeda-Yamazaki, Masato Motomura, Tetsuya Asai, Masayuki Ikebe, Hotaka Kusano — Microprocessors and Microsystems — Journal Papers — 2018
Sneak Path Free Reconfiguration of Via-switch Crossbars Based FPGA
Ryutaro Doi, Jaehoon Yu, Masanori Hashimoto — International Conference — 2018
Sparse Disparity Estimation Using Global Phase Only Correlation for Stereo Matching Acceleration
Takeshi Shimada, Masayuki Ikebe, Prasoon Ambalathankandy, Shinya Takamaeda-Yamazaki, Masato Motomura, Tetsuya Asai — IEEE International Conference on Acoustics, Speech and Signal Processing — International Conference — 2018
Via-Switch FPGA: Highly Dense Mixed-Grained Reconfigurable Architecture with Overlay Via-Switch Crossbars
Hiroyuki Ochi, Kosei Yamaguchi, Tetsuaki Fujimoto, Junshi Hotate, Takashi Kishimoto, Toshiki Higashi, Takashi Imagawa, Ryutaro Doi, Munehiro Tada, Tadahiko Sugibayashi, Wataru Takahashi, Kazutoshi Wakabayashi, Hidetoshi Onodera, Yukio Mitsuyama, Jaehoon Yu, Masanori Hashimoto — Journal Papers — 2018
ビアスイッチ FPGA 再構成時のスニークパス問題を回避するプログラミング順決定手法
土井龍太郎, 劉載勲, 橋本昌宜, others — DA シンポジウム 2018 論文集 — International Conference — 2018
ビアスイッチ FPGA 向け配線解析手法の検討 (VLSI 設計技術)
中澤祐希, 土井龍太郎, 劉載勲, 橋本昌宜 — 電子情報通信学会技術研究報告= IEICE technical report: 信学技報 — International Conference — 2018

2017

[Invited] A Binary/Ternary Reconfigurable in-Memory Deep Neural Network Accelerator
Masato Motomura — Workshop — 2017
[Invited] Research Activity on Deep Neural Network Accelerators
Masato Motomura — Workshop — 2017
[Invited] Rise of Deep Neural Network Accelerators
Masato Motomura — Workshop — 2017
[Invited] Trends toward Reconfigurable and in-Memory Processing Architectures for Deep Neural Networks
Masato Motomura — Workshop — 2017
[Invited] Trends toward Reconfigurable and in-Memory Processing Architectures for Deep Neural Networks
Masato Motomura — Workshop — 2017
6-DoF Camera Position and Posture Estimation Based on Local Patches of Image Sequence
Takuto Tsuji, Masayuki Ikebe, Shinya Takamaeda-Yamazaki, Masato Motomura, Tetsuya Asai — Journal of Signal Processing — Journal Papers — 2017
6-DoF Camera-Position and Posture Estimation Based on Local Patches of Image Sequence
Takuto Tsuji, Masayuki Ikebe, Shinya Takamaeda-Yamazaki, Masato Motomura, Tetsuya Asai — RISP International Workshop on Nonlinear Circuits, Communications and Signal Processing — International Conference — 2017
A Batch Normalization Free Binarized Convolutional Deep Neural Network on an FPGA
Hiroki Nakahara, Haruyoshi Yonekawa, Hisashi Iwamoto, Masato Motomura — International Symposium on Field-Programmable Gate Array (FPGA) — International Conference — 2017
A High Performance and Energy Efficient Microprocessor with a Novel Restricted Dynamically Reconfigurable Accelerator
Itaru Hida, Shinya Takamaeda-Yamazaki, Masayuki Ikebe, Masato Motomura, Tetsuya Asai — Circuits and Systems — Journal Papers — 2017
A Low-Energy Application Specific Instruction-Set Processor towards a Low-Computational Lossless Compression Method for Stimuli Position Data of Artificial Vision Systems
Tomoki Sugiura, Masaharu Imai, Jaehoon Yu, Yoshinori Takeuchi — Journal Papers — 2017
A Multithreaded CGRA for Convolutional Neural Network Processing
Kota Ando, Shinya Takamaeda-Yamazaki, Masayuki Ikebe, Tetsuya Asai, Masato Motomura — Circuits and Systems — Journal Papers — 2017
A Regularization Approach for Quantized Neural Networks
Kazutoshi Hirose, Ryota Uematsu, Kota Ando, Kodai Ueyoshi, Masayuki Ikebe, Tetsuya Asai, Masato Motomura, Shinya Takamaeda-Yamazaki — International Workshop on Highly Efficient Neural Networks Design (HENND) — International Conference — 2017
A Scalable Ising Model Implementation on An FPGA
Kasho Yamamoto, Shinya Takamaeda-Yamazaki, Masayuki Ikebe, Tetsuya Asai, Masato Motomura — COOL Chips — International Conference — 2017
A Time-Division Multiplexing Ising Machine on FPGAs
Kasho Yamamoto, Weiqiang Huang, Shinya Takamaeda-Yamazaki, Masayuki Ikebe, Tetsuya Asai, Masato Motomura — International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies (HEART) — International Conference — 2017
A Versatile and Energy-Efficient Reconfigurable Accelerator for Embedded Microprocessors
Itaru Hida, Shinya Takamaeda-Yamazaki, Masayuki Ikebe, Masato Motomura, Tetsuya Asai — GI-CoRE GSQ, GSB, & IGM Joint Symposium -Quantum, Informatics, Biology, & Medicine - — International Conference — 2017
Accelerating Deep Learning by Binarized Hardware
Shinya Takamaeda-Yamazaki, Kodai Ueyoshi, Kota Ando, Ryota Uematsu, Kazutoshi Hirose, Masayuki Ikebe, Tetsuya Asai, Masato Motomura — Asia-Pacific Signal and Information Processing Association Annual Summit and Conference (APSIPA ASC) — International Conference — 2017
An Energy-Efficient Dynamic Branch Predictor with a Two-Clock-Cycle Naive Bayes Classifier for Pipelined RISC Microprocessors
Itaru Hida, Shinya Takamaeda-Yamazaki, Masayuki Ikebe, Masato Motomura, Tetsuya Asai — Nonlinear Theory and Its Applications — Journal Papers — 2017
An FPGA Realization of a Deep Convolutional Neural Network Using A Threshold Neuron Pruning
Tomoya Fujii, Shimpei Sato, Hiroki Nakahara, Masato Motomura — International Symposium on Applied Reconfigurable Computing (ARC) — International Conference — 2017
BRein Memory: A 13-Layer 4.2 K Neuron/0.8 M Synapse Binary/Ternary Reconfigurable In-Memory Deep Neural Network Accelerator in 65 nm CMOS
Kota Ando, Kodai Ueyoshi, Kentaro Orimo, Haruyoshi Yonekawa, Shimpei Sato, Hiroki Nakahara, Masayuki Ikebe, Tetsuya Asai, Shinya Takamaeda-Yamazaki, Tadahiro Kuroda, Masato Motomura — Symposia on VLSI Technology and Circuits — International Conference — 2017
Deformable Part Model Based Arrhythmia Detection Using Time Domain Features
Yuuka Hirao, Yoshinori Takeuchi, Masaharu Imai, Jaehoon Yu — IEICE_J_FECACS — Journal Papers — 2017
Error Tolerance Analysis of Deep Learning Hardware Using Restricted Boltzmann Machine towards Low-Power Memory Implementation
Takao Marukame, Kodai Ueyoshi, Tetsuya Asai, Masato Motomura, Alexandre Schmid, Masamichi Suzuki, Yusuke Higashi, Yuichiro Mitani — IEEE Transactions on Circuits and Systems II — Journal Papers — 2017
Exploring Optimized Accelerator Design for Binarized Convolutional Neural Networks
Kodai Ueyoshi, Kota Ando, Kentaro Orimo, Masayuki Ikebe, Tetsuya Asai, Masato Motomura — International Joint Conference on Neural Networks — International Conference — 2017
Fast and Cycle-Accurate Emulation of Large-Scale Networks-on-Chip Using a Single FPGA
Thiem Van Chu, Shimpei Sato, Kenji Kise — ACM Transactions on Reconfigurable Technology and Systems (TRETS) — Journal Papers — 2017
Feature Extraction System Using Restricted Boltzmann Machines on FPGA
Kodai Ueyoshi, Takao Marukame, Tetsuya Asai, Masato Motomura, Alexandre Schmid — IEEE International Symposium on Circuits & Systems — International Conference — 2017
FPGA Implementation of Edge-Guided Pattern Generation for Motion-Vector Estimation of Textureless Objects (Demo Night)
Aoi Tanibata, Alexandre Schmid, Shinya Takamaeda-Yamazaki, Masayuki Ikebe, Masato Motomura, Tetsuya Asai — International Conference on Field-Programmable Logic and Applications (FPL) — International Conference — 2017
Hardware Accelerator Design for Convolutional Neural Networks with Low Bit Precision
Kodai Ueyoshi, Masayuki Ikebe, Tetsuya Asai, Shinya Takamaeda-Yamazaki, Masato Motomura — GI-CoRE GSQ, GSB, & IGM Joint Symposium - Quantum, Informatics, Biology, & Medicine - — International Conference — 2017
Hardware-Oriented Algorithm for Phase Synchronization Analysis of Biomedical Signals
Tomoki Sugiura, Jaehoon Yu, Yoshinori Takeuchi — IEEE_C_BCAS — International Conference — 2017
High-Performance Hardware Merge Sorter
Susumu Mashimo, Thiem Van Chu, Kenji Kise — IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM) — International Conference — 2017
In-Memory Area-Efficient Signal Streaming Processor Design for Binary Neural Networks
Kota Ando, Kodai Ueyoshi, Kazutoshi Hirose, Kentaro Orimo, Haruyoshi Yonekawa, Shimpei Sato, Hiroki Nakahara, Masayuki Ikebe, Shinya Takamaeda-Yamazaki, Tetsuya Asai, Tadahiro Kuroda, Masato Motomura — IEEE International Midwest Symposium on Circuits and Systems (MWSCAS) — International Conference — 2017
Logarithmic Compression for Memory Footprint Reduction in Neural Network Training
Kazutoshi Hirose, Ryota Uematsu, Kota Ando, Kentaro Orimo, Kodai Ueyoshi, Masayuki Ikebe, Tetsuya Asai, Shinya Takamaeda-Yamazaki, Masato Motomura — International Workshop on Computer Systems and Architectures (CSA) — International Conference — 2017
Low latency divider using ensemble of moving average curves
Yuhan Fu, Masayuki Ikebe, Takeshi Shimada, Masato Motomura, Tetsuya Asai — International Symposium on Quality Electronic Design (ISQED) — International Conference — 2017
Quantization Error-based Regularization in Neural Networks
Kazutoshi Hirose, Kota Ando, Kodai Ueyoshi, Masayuki Ikebe, Tetsuya Asai, Masato Motomura, Shinya Takamaeda-Yamazaki — SGAI International Conference on Artificial Intelligence (SGAI) — International Conference — 2017
Sign-Invariant Unsupervised Learning Facilitates Weighted-Sum Computation in Analog Neural-Network Devices
Itaru Hida, Kodai Ueyoshi, Shinya Takamaeda-Yamazaki, Masayuki Ikebe, Masato Motomura, Tetsuya Asai — International Symposium on Nonlinear Theory and Its Applications — International Conference — 2017
Throughput Analysis of A Data-Flow Reconfigurable Array Architecture for Convolutional Neural Networks
Kota Ando, Kodai Ueyoshi, Kentaro Orimo, Masayuki Ikebe, Shinya Takamaeda-Yamazaki, Tetsuya Asai, Masato Motomura — RIEC International Symposium on Brain Functions and Brain Computer — International Conference — 2017
Time-Division Multiplexing
Kasho Yamamoto, Masayuki Ikebe, Tetsuya Asai, Masato Motomura, Shinya Takamaeda-Yamazaki — GI-CoRE GSQ, GSB, & IGM Joint Symposium - Quantum, Informatics, Biology, & Medicine - — International Conference — 2017

2016

[Invited] 3D Stacked Image Sensor Featuring Low Noise Inductive Coupling Channels
Masayuki Ikebe, Daisuke Uchida, Yasuhiro Take, Tetsuya Asai, Tadahiro Kuroda, Masato Motomura — International Workshop on Image Sensors and Imaging Systems — International Conference — 2016
[Invited] AI and SoC
Masato Motomura — Workshop — 2016
3D Stacked Imager Featuring Inductive Coupling Channels for High Speed/Low-Noise Image Transfer
Masayuki Ikebe, Daisuke Uchida, Yasuhiro Take, Makito Someya, Satoshi Chikuda, Kento Matsuyama, Tetsuya Asai, Tadahiro Kuroda, Masato Motomura — ITE Transactions on Media Technology and Applications — Journal Papers — 2016
A Hardware Cellular-Automaton Architecture for Spatial Pattern Generation towards Motion-Vector Estimation of Textureless Objects
Aoi Tanibata, Miho Ushida, Alexandre Schmid, Masayuki Ikebe, Tetsuya Asai, Masato Motomura — International Symposium on Nonlinear Theory and its Applications — International Conference — 2016
A Memory-Based Realization of A Binarized Deep Convolutional Neural Network
Hiroki Nakahara, Haruyoshi Yonekawa, Tsutomu Sasao, Hisashi Iwamoto, Masato Motomura — International Conference on Field-Programmable Technology (FPT) — International Conference — 2016
A Programmable Controller for Spatio-Temporal Pattern Stimulation of Cortical Visual Prosthesis
Tomoki Sugiura, Arif Ullah Khan, Jaehoon Yu, Yoshinori Takeuchi, Seiji Kameda, Takatsugu Kamata, Yuki Hayashida, Tetsuya Yagi, Masaharu Imai — IEEE_C_BCAS — International Conference — 2016
A Two-Clock-Cycle Naive Bayes Classifier for Dynamic Branch Prediction in Pipelined RISC Microprocessors
Itaru Hida, Masayuki Ikebe, Tetsuya Asai, Masato Motomura — IEEE Asia Pacific Conference on Circuits and Systems — International Conference — 2016
An FPGA-Optimized Architecture of Anti-Aliasing Based Super Resolution for Real-time HDTV to 4K- and 8K-UHD Conversions
Hotaka Kusano, Masayuki Ikebe, Tetsuya Asai, Masato Motomura — International Conference on Reconfigurable Computing and FPGAs — International Conference — 2016
Arrhythmia Detection Using a Deformable Part Model and Time Domain Features
Yuuka Hirao, Jaehoon Yu, Yoshinori Takeuchi, Masaharu Imai — International Conference — 2016
Cognitive Motion Processing in Imager/Neural Processor 3D Stacked Systems
Tetsuya Asai, Masayuki Ikebe, Masato Motomura — Workshop — 2016
ECG の可変形状モデルに基づく不整脈検出アルゴリズム (スマートインフォメディアシステム)
平尾優香, 劉載勲, 武内良典, 今井正治 — 電子情報通信学会技術研究報告= IEICE technical report: 信学技報 — International Conference — 2016
FPGA Architecture for Feed-Forward Sequential Memory Network Targeting Long-Term Time-Series Forecasting
Kentaro Orimo, Kota Ando, Kodai Ueyoshi, Masayuki Ikebe, Tetsuya Asai, Masato Motomura — International Conference on Reconfigurable Computing and FPGAs — International Conference — 2016
FPGA Implementation of A Scalable and Highly Parallel Architecture for Restricted Boltzmann Machines
Kodai Ueyoshi, Takao Marukame, Tetsuya Asai, Masato Motomura, Alexandre Schmid — Circuits and Systems — Journal Papers — 2016
FPGA-Based Stream Processing for Frequent Itemset Mining with Incremental Multiple Hashes
Kasho Yamamoto, Masayuki Ikebe, Tetsuya Asai, Masato Motomura — Circuits and Systems — Journal Papers — 2016
Hardware Architecture for Online Frequent Items Mining with Memory-Efficient Data Structure
Kasho Yamamoto, Tetsuya Asai, Masato Motomura — COOL Chips XIX — International Conference — 2016
Influence of Numerical Precision on Machine Learning and Embedded Systems
Koichi Mitsunari, Jaehoon Yu — C_SISA — International Conference — 2016
Memory-Error Tolerance of Scalable and Highly Parallel Architecture for Restricted Boltzmann Machines in Deep Belief Network
Kodai Ueyoshi, Takao Marukame, Tetsuya Asai, Masato Motomura, Alexandre Schmid — IEEE International Symposium on Circuits and Systems — International Conference — 2016
Motion Vector Estimation of Textureless Objects Exploiting Reaction-Diffusion Cellular Automata
Miho Ushida, Alexandre Schmid, Tetsuya Asai, Kazuyoshi Ishimura, Masato Motomura — International Journal of Unconventional Computing — Journal Papers — 2016
Motion-Vector Estimation and Cognitive Classification on An Image Sensor/Processor 3D Stacked System Featuring ThruChip Interfaces
Tetsuya Asai, Masafumi Mori, Toshiyuki Itou, Yasuhiro Take, Masayuki Ikebe, Tadahiro Kuroda, Masato Motomura — European Solid-State Circuits Conference — International Conference — 2016
Object Tracking based on Path Similarity of Boosted Decision Trees
Koichi Mitsunari, Jaehoon Yu, Yoshinori Takeuchi, Masaharu Imai — International Conference — 2016
Proposal of An Efficient Clock-Gating Mechanism for Multi-Core Processors to Reduce Power Supply Noise
Jun Kawabe, Yoshinori Takeuchi, Jaehoon Yu, Masaharu Imai — Workshop on Synthesis And System Integration of Mixed Information technologies — International Conference — 2016
Reconfigurable Processor Array Architecture for Deep Convolutional Neural Networks
Kota Ando, Kentaro Orimo, Kodai Ueyoshi, Masayuki Ikebe, Tetsuya Asai, Masato Motomura — Workshop on Synthesis And System Integration of Mixed Information Technologies — International Conference — 2016
Reconfigurable Processor Array Architecture for Deep Convolutional Neural Networks
Kota Ando, Kentaro Orimo, Kodai Ueyoshi, Masayuki Ikebe, Tetsuya Asai, Masato Motomura — Workshop on Synthesis And System Integration of Mixed Information Technologies — International Conference — 2016
Robustness of Hardware-Oriented Restricted Boltzmann Machines in Deep Belief Networks for Reliable Processing
Kodai Ueyoshi, Takao Marukame, Tetsuya Asai, Masato Motomura, Alexandre Schmid — Nonlinear Theory and Its Applications — Journal Papers — 2016
Stochastic Resonance Induced by Internal Noise in A Unidirectional Network of Excitable FitzHugh-Nagumo Neurons
Kazuyoshi Ishimura, Alexandre Schmid, Tetsuya Asai, Masato Motomura — Nonlinear Theory and Its Applications — Journal Papers — 2016
System Design of Vision-based Framework for Senior Driver Assistance
Eric Aliwarga, Koichi Mitsunari, Jaehoon Yu, Takao Onoye, Toshitaka Azuma, Mitsuhiko Koga — Workshop on Synthesis And System Integration of Mixed Information technologies — International Conference — 2016
The Synchronous vs. Asynchronous NoC Routers: An Apple-to-Apple Comparison between Synchronous and Transition Signaling Asynchronous Designs
Masashi Imai, Thiem Van Chu, Kenji Kise, Tomohiro Yoneda — IEEE/ACM International Symposium on Networks-on-Chip (NOCS) — International Conference — 2016
Vision-based Comprehensive Framework for Senior Driver Assistance
Mitsuhiko Koga, Takao Onoye, Jaehoon Yu, Toshitaka Azuma, Eric Aliwarga — ERTICO — International Conference — 2016
心疾患発症を検出するための就寝時心電計測システムの提案
武内良典, 劉載勲, 今井正治, others — 研究報告システム・アーキテクチャ (ARC) — International Conference — 2016
電源ノイズ削減のためのマルチコアプロセッサ向けクロックゲーティング機構の提案
川部純, 武内良典, 劉載勲, 今井正治, others — DA シンポジウム 2016 論文集 — International Conference — 2016

2015

A Low-Energy ASIP with Flexible Exponential Golomb Codec for Lossless Data Compression toward Artificial Vision Systems
Tomoki Sugiura, Jaehoon Yu, Yoshinori Takeuchi, Masaharu Imai — International Conference — 2015
A New Architecture for Feature Extraction to Perform Machine Learning by Using Motion Vectors and Its Implementation in An FPGA
Toshiyuki Itou, Masafumi Mori, Masayuki Ikebe, Tetsuya Asai, Tadahiro Kuroda, Masato Motomura — RISP International Workshop on Nonlinear Circuits, Communications and Signal Processing — International Conference — 2015
A Reaction-Diffusion Algorithm for Texture Generation towards Motion-Vector Estimation of Textureless-Objects
Miho Ushida, Kazuyoshi Ishimura, Tetsuya Asai, Masato Motomura — RISP International Workshop on Nonlinear Circuits, Communications and Signal Processing — International Conference — 2015
An Accelerator for Frequent Itemset Mining from Data Stream with Parallel Item Tree
Kasho Yamamoto, Eric S Fukuda, Tetsuya Asai, Masato Motomura — Workshop on Synthesis And System Integration of Mixed Information Technologies — International Conference — 2015
Crosstalk Rejection in 3D-Stacked Inter-Chip Communication with Blind Source Separation
Kamal El-Sankary, Tetsuya Asai, Tadahiro Kuroda, Masato Motomura — IEEE Transactions on Circuits and Systems II — Journal Papers — 2015
Design of Generic Hardware for Soft Cascade-Based Linear SVM Classification
Eric Aliwarga, Jaehoon Yu, Masahide Hatanaka, Takao Onoye — International Conference — 2015
Enhancing Memcached by Caching its Data and Functionalities at Network Interface
Eric S Fukuda, Hiroaki Inoue, Takashi Takenaka, Dahoo Kim, Tsunaki Sadahisa, Tetsuya Asai, Masato Motomura — IPSJ Journal — Journal Papers — 2015
FPGA Implementation of Hardware-Oriented Reaction-Diffusion Cellular Automata Models
Kazuyoshi Ishimura, Katsuro Komuro, Alexandre Schmid, Tetsuya Asai, Masato Motomura — Nonlinear Theory and Its Applications — Journal Papers — 2015
Image Sensor/Digital Logic 3D Stacked Module Featuring Inductive Coupling Channels for High Speed/Low-Noise Image Transfer
Masayuki Ikebe, Daisuke Uchida, Yasuhiro Take, Makito Someya, Satoshi Chikuda, Kento Matsuyama, Tetsuya Asai, Tadahiro Kuroda, Masato Motomura — Symposia on VLSI Technology and Circuits — International Conference — 2015
Motion Vector Estimation of Textureless Objects Exploiting Reaction-Diffusion Cellular Automata
Miho Ushida, Kazuyoshi Ishimura, Alexandre Schmid, Tetsuya Asai, Masato Motomura — International Symposium on Nonlinear Theory and its Applications — International Conference — 2015
Scalable and Highly-Parallel Architecture for Restricted Boltzmann Machines
Kodai Ueyoshi, Tetsuya Asai, Masato Motomura — RISP International Workshop on Nonlinear Circuits, Communications and Signal Processing — International Conference — 2015
Through Chip Interface Based Three-Dimensional FPGA Architecture Exploration
Li-Chung Hsu, Masato Motomura, Yasuhiro Take, Tadahiro Kuroda — IEICE Transactions on Electronics — Journal Papers — 2015
就寝時心電取得のための無意識生体電位計測システムの提案
武内良典, 劉載勲, 山中達哉, 関根正樹, 今井正治, others — 研究報告組込みシステム (EMB) — International Conference — 2015

2014

A 4.5 to 13 Times Energy-Efficient Embedded Microprocessor with Mainly-Static/Partially-Dynamic Reconfigurable Array Accelerator
Itaru Hida, Dahoo Kim, Tetsuya Asai, Masato Motomura — Asian Solid-State Circuits Conference — International Conference — 2014
A Study of Transparent On-Chip Instruction Cache for NV Microcontrollers
Dahoo Kim, Itaru Hida, Eric S Fukuda, Tetsuya Asai, Masato Motomura — International Conference on Advances in Circuits, Electronics and Micro-electronics — International Conference — 2014
Achieving Higher Performance of Memcached by Caching at Network Interface
Eric S Fukuda, Hiroaki Inoue, Takashi Takenaka, Dahoo Kim, Tsunaki Sadahisa, Tetsuya Asai, Masato Motomura — International Conference on Field Programmable Technology (FPT) — International Conference — 2014
An Efficient Data Compression Method for Artificial Vision Systems and Its Low Energy Implementation Using ASIP Technology
Tomoki Sugiura, Shoko Nakatsuka, Jaehoon Yu, Yoshinori Takeuchi, Masaharu Imai — IEEE_C_BCAS — International Conference — 2014
Application of Nonlinear Systems for Designing Low-Power Logic Gates Based on Stochastic Resonance
Gonzalez-Carabarin Lizeth, Tetsuya Asai, Masato Motomura — Nonlinear Theory and Its Applications — Journal Papers — 2014
Caching Memcached at Reconfigurable Network Interface
Eric S Fukuda, Hiroaki Inoue, Takashi Takenaka, Dahoo Kim, Tsunaki Sadahisa, Tetsuya Asai, Masato Motomura — International Conference on Field Programmable Logic and Applications (FPL) — International Conference — 2014
Dual-Rail Asynchronous Pipeline Based on Stochastic Resonance Logic Gates
Gonzalez-Carabarin Lizeth, Tetsuya Asai, Masato Motomura — International Symposium on Nonlinear Theory and its Applications — International Conference — 2014
FPGA Implementation of A Memory-Efficient Stereo Vision Algorithm Based on 1-D Guided Filtering
Yuki Sanada, Katsuki Ohata, Tetsuro Ogaki, Kento Matsuyama, Takanori Ohira, Satoshi Chikuda, Masaki Igarashi, Tadahiro Kuroda, Masayuki Ikebe, Tetsuya Asai, Masato Motomura — International Conference on Circuits, Systems, and Control — International Conference — 2014
FPGA-Based Design for Motion-Vector Estimation Exploiting High-Speed Imaging and Its Application to Machine Learning
Masafumi Mori, Toshiyuki Itou, Masayuki Ikebe, Tetsuya Asai, Tadahiro Kuroda, Masato Motomura — RISP International Workshop on Nonlinear Circuits, Communications and Signal Processing — International Conference — 2014
FPGA-Based Design for Motion-Vector Estimation Exploiting High-Speed Imaging and Its Application to Motion Classification with Neural Networks
Masafumi Mori, Toshiyuki Itou, Masayuki Ikebe, Tetsuya Asai, Tadahiro Kuroda, Masato Motomura — Journal of Signal Processing — Journal Papers — 2014
Hardware Architecture for Accelerating Key-Value Retrieval Implemented on FPGA
Dahoo Kim, Eric S Fukuda, Tsunaki Sadahisa, Tetsuya Asai, Masato Motomura — Japan-Korea Joint Workshop on Complex Communication Sciences — International Conference — 2014
Image Steganography Based on Reaction Diffusion Models toward Hardware Implementation
Kazuyoshi Ishimura, Katsuro Komuro, Alexandre Schmid, Tetsuya Asai, Masato Motomura — Nonlinear Theory and Its Applications — Journal Papers — 2014
Low-Power Asynchronous Digital Pipeline Based on Mismatch-Tolerant Logic Gates
Gonzalez-Carabarin Lizeth, Tetsuya Asai, Masato Motomura — IEICE Electronics Express — Journal Papers — 2014
Normalized Channel Features for Accurate Pedestrian Detection
Ryusuke Miyamoto, Jaehoon Yu, Takao Onoye — International Symposium on Communications, Control and Signal Processing — International Conference — 2014
Reducing Power and Energy Consumption of Nonvolatile Microcontrollers with Transparent On-Chip Instruction Cache
Dahoo Kim, Itaru Hida, Eric S Fukuda, Tetsuya Asai, Masato Motomura — Circuits and Systems — Journal Papers — 2014
Stochastic Resonance in A Unidirectional Network of Nonlinear Oscillators Driven by Internal Noise
Kazuyoshi Ishimura, Katsuro Komuro, Alexandre Schmid, Tetsuya Asai, Masato Motomura — International Symposium on Nonlinear Theory and its Applications — International Conference — 2014
コンパイラ生成のための ASIP 必要命令セット判定手法
由井暁大, 劉載勲, 武内良典, 今井正治, others — DA シンポジウム 論文集 — International Conference — 2014
ソフトカスケードを用いた SVM 識別器の専用ハードウェア実装 (スマートインフォメディアシステム)
竹内一貴, 劉載勲, 宮本龍介, 尾上孝雄 — 電子情報通信学会技術研究報告= IEICE technical report: 信学技報 — International Conference — 2014
回転変化に対する耐性を持つ画像認識のための特徴抽出手法 (スマートインフォメディアシステム)
岩崎裕也, 劉載勲, 宮本龍介, 尾上孝雄 — 電子情報通信学会技術研究報告= IEICE technical report: 信学技報 — International Conference — 2014
圧縮センシングに基づく超解像処理の高速化 (信号処理)
山下智博, 劉載勲, 武内良典, 今井正治 — 電子情報通信学会技術研究報告= IEICE technical report: 信学技報 — International Conference — 2014

2013

A Restricted Dynamically Reconfigurable Architecture for Low Power Processors
Takeshi Hirao, Dahoo Kim, Itaru Hida, Tetsuya Asai, Masato Motomura — International Conference on ReConFigurable Computing and FPGAs — International Conference — 2013
A Restricted Dynamically Reconfigurable Architecture for Low Power Processors
Takeshi Hirao, Dahoo Kim, Itaru Hida, Tetsuya Asai, Masato Motomura — Workshop on Synthesis And System Integration of Mixed Information Technologies — International Conference — 2013
A Speed-Up Scheme Based on Multiple-Instance Pruning for Pedestrian Detection Using A Support Vector Machine
Jaehoon Yu, Ryusuke Miyamoto, Takao Onoye — Journal Papers — 2013
Asynchronous Digital Circuit Design Using Noise-Driven Stochastic Gates
Gonzalez-Carabarin Lizeth, Tetsuya Asai, Masato Motomura — International Symposium on Nonlinear Theory and its Applications — International Conference — 2013
C-Based Adaptive Stream Processing on Dynamically Reconfigurable Hardware: Window Join Case Study
Eric S Fukuda, Hideyuki Kawashima, Hiroaki Inoue, Taro Fujii, Koichiro Furuta, Tetsuya Asai, Masato Motomura — International Symposium on Applied Reconfigurable Computing (ARC) — International Conference — 2013
C-Based Complex Event Processing on Reconfigurable Hardware
Hiroaki Inoue, Takashi Takenaka, Masato Motomura — IEEE Transactions on Very Large Scale Integration Systems — Journal Papers — 2013
C-Based Design of Window Join for Dynamically Reconfigurable Hardware
Eric S Fukuda, Hideyuki Kawashima, Hiroaki Inoue, Tetsuya Asai, Masato Motomura — Journal of Computer Science and Engineering — Journal Papers — 2013
Chaotic Resonance in Forced Chua’s Oscillators
Kazuyoshi Ishimura, Tetsuya Asai, Masato Motomura — Journal of Signal Processing — Journal Papers — 2013
CoHOG 特徴を用いた歩行者検出の確率的サンプリングに基づく高速化
劉載勲, 宮本龍介, 尾上孝雄 — 画像電子学会誌 — Journal Papers — 2013
Exploiting Hardware Reconfigurability on Window Join
Eric S Fukuda, Hideyuki Kawashima, Hiroaki Inoue, Tetsuya Asai, Masato Motomura — International Conference on High Performance Computing & Simulation — International Conference — 2013
FPGA Implementation of 60-FPS QVGA-to-VGA Single-Image Super Resolution
Satoshi Chikuda, Takanori Ohira, Yuki Sanada, Masaki Igarashi, Masayuki Ikebe, Tetsuya Asai, Masato Motomura — International Conference on Solid State Devices and Materials — International Conference — 2013
FPGA Implementation of Single-Image Super Resolution Based on Frame-Bufferless Box Filtering
Yuki Sanada, Takanori Ohira, Satoshi Chikuda, Masaki Igarashi, Masayuki Ikebe, Tetsuya Asai, Masato Motomura — Journal of Signal Processing — Journal Papers — 2013
FPGA Implementation of Single-Image Super Resolution Based on Frame-Bufferless Box Filtering
Yuki Sanada, Takanori Ohira, Satoshi Chikuda, Masaki Igarashi, Masayuki Ikebe, Tetsuya Asai, Masato Motomura — RISP International Workshop on Nonlinear Circuits, Communications and Signal Processing — International Conference — 2013
Hardware-Oriented Stereo Vision Algorithm Based on 1-D Guided Filtering and Its FPGA Implementation
Katsuki Ohata, Yuki Sanada, Tetsuro Ogaki, Kento Matsuyama, Takanori Ohira, Satoshi Chikuda, Masaki Igarashi, Masayuki Ikebe, Tetsuya Asai, Masato Motomura, Tadahiro Kuroda — IEEE International Conference on Electronics, Circuits, and Systems — International Conference — 2013
High Level Synthesis with Stream Query to C Parser: Eliminating Hardware Development Difficulties for Software Developers
Eric S Fukuda, Takashi Takenaka, Hiroaki Inoue, Hideyuki Kawashima, Tetsuya Asai, Masato Motomura — Workshop on Synthesis And System Integration of Mixed Information Technologies — International Conference — 2013
Image steganography based on hardware-oriented reaction-diffusion models
Kazuyoshi Ishimura, Alexandre Schmid, Tetsuya Asai, Masato Motomura — International Symposium on Nonlinear Theory and its Applications — International Conference — 2013
Image Steganography on Digital Reaction-Diffusion Processor
Kazuyoshi Ishimura, Alexandre Schmid, Tetsuya Asai, Masato Motomura — Nonlinear Dynamics of Electronic Systems — International Conference — 2013
Towards Asynchronous Digital Circuit Design Based on Stochastic Resonance
Gonzalez-Carabarin Lizeth, Tetsuya Asai, Masato Motomura — International Conference on Nanoenergy — International Conference — 2013
狭帯域ボディエリアネットワーク向け命令セットプロセッサの提案
百谷和幸, 劉載勲, 武内良典, 今井正治 — IEEE COMS 関西チャプタ 学生研究発表会 — International Conference — 2013

2012

A Memristor-Based Synaptic Device Having an Asymmetric STDP Time Window
Taku Adachi, Tetsuya Asai, Masato Motomura — RISP International Workshop on Nonlinear Circuits, Communications and Signal Processing — International Conference — 2012
Chaotic Resonance in Forced Chua’s Oscillator
Kazuyoshi Ishimura, Tetsuya Asai, Masato Motomura — RISP International Workshop on Nonlinear Circuits, Communications and Signal Processing — International Conference — 2012
Excitable Reaction-Diffusion Media with Memristors
Xiyuan Gong, Tetsuya Asai, Masato Motomura — Journal of Signal Processing — Journal Papers — 2012
Excitable Reaction-Diffusion Media with Memristors
Xiyuan Gong, Tetsuya Asai, Masato Motomura — RISP International Workshop on Nonlinear Circuits, Communications and Signal Processing — International Conference — 2012
Impact of Noise on Spike Transmission through Serially-Connected Electrical FitzHugh-Nagumo Circuits with Subthreshold and Suprathreshold Interconductances
Gonzalez-Carabarin Lizeth, Tetsuya Asai, Masato Motomura — Journal of Signal Processing — Journal Papers — 2012
Noise Impact on Spike Transmission through Serially-Connected Electrical FitzHugh-Nagumo Model with Subthreshold and Suprathreshold Interconductances
Gonzalez-Carabarin Lizeth, Tetsuya Asai, Masato Motomura — International Conference On Cognitive and Neural Systems — International Conference — 2012
Noise-Assisted Spike Transmission on An Array of Electrical FitzHugh-Nagumo Models
Gonzalez-Carabarin Lizeth, Tetsuya Asai, Masato Motomura — RISP International Workshop on Nonlinear Circuits, Communications and Signal Processing — International Conference — 2012
Noise-Induced Phase Synchronization among Simple Digital Counters
Masakazu Matsuura, Tetsuya Asai, Masato Motomura — Journal of Signal Processing — Journal Papers — 2012
Noise-Induced Phase Synchronization in Digital Counters
Masakazu Matsuura, Tetsuya Asai, Masato Motomura — RISP International Workshop on Nonlinear Circuits, Communications and Signal Processing — International Conference — 2012
Pedestrian Localization Using CoHOG-based Detection and HSV-based Tracking
Jaehoon Yu, Ryusuke Miyamoto, Takao Onoye, Hiroki Sugano, Yukihiro Nakamura — C_ITC-CSCC — International Conference — 2012
Reaction-Diffusion Media with Excitable Oregonators Coupled by Memristors
Xiyuan Gong, Tetsuya Asai, Masato Motomura — International Workshop on Cellular Nanoscale Networks and their Applications (Memristor and Memristive Symposium) — International Conference — 2012
Spatio-Temporal Pattern Formation on Memristive Reaction-Diffusion Systems
Xiyuan Gong, Tetsuya Asai, Masato Motomura — Asia Conference on Nanoscience and Nanotechnology — International Conference — 2012
Spike Propagation in Excitable Systems Enhanced by Membrane-Potential-Dependent Noise
Gonzalez-Carabarin Lizeth, Tetsuya Asai, Masato Motomura — International Symposium on Nonlinear Theory and its Applications — International Conference — 2012
Spike Transmission in Locally Coupled Excitable Circuits Enhanced by Membrane-Potential-Dependent Noise
Gonzalez-Carabarin Lizeth, Tetsuya Asai, Masato Motomura — Asia Conference on Nanoscience and Nanotechnology 2012 — International Conference — 2012
メトロポリス・ヘイスティングス法を用いた物体検出手法の並列化検討
劉載勲, 宮本龍介, 尾上孝雄 — 電子情報通信学会技術研究報告. SIS, スマートインフォメディアシステム — International Conference — 2012

2011

20Gbps C-Based Complex Event Processing
Hiroaki Inoue, Takashi Takenaka, Masato Motomura — International Conference on Field Programmable Logic and Applications (FPL) — International Conference — 2011
A Subthreshold Memory Cell Utilizing Nonlinear Characteristics of Positive-Feedback Operational Transconductance Amplifier
Kazunori Yoshida, Tetsuya Asai, Masato Motomura — Kyoto Workshop on NOLTA — International Conference — 2011
Test Compression for Dynamically Reconfigurable Processors
Hiroaki Inoue, Junya Yamada, Hideyuki Yoneda, Katsumi Togawa, Masato Motomura, Koichiro Furuta — ACM Transactions on Reconfigurable Technology and Systems (TRETS) — Journal Papers — 2011
Time and Space-Multiplexed Compilation Challenge for Dynamically Reconfigurable Processors
Takao Toi, Toru Awashima, Masato Motomura, Hideharu Amano — IEEE International Midwest Symposium on Circuits and Systems (MWSCAS) — International Conference — 2011
多重領域分割に基づく複数の手掛りを用いた画像構造識別手法
劉載勲, 宮本龍介, 尾上孝雄 — 電子情報通信学会技術研究報告. SIS, スマートインフォメディアシステム — International Conference — 2011

2010

AS-2-4 階層探索による Full HD 対応 H. 264 小面積動き検出回路の開発 (AS-2. ディジタル信号処理システムの実装技術, シンポジウムセッション)
渡邊賢治, 平井直行, 今川隆司, 劉載勲, 橋本亮司, 藤田玄 — 電子情報通信学会総合大会講演論文集 — International Conference — 2010
Computationally Efficient Pedestrian Detection Based on Markov Chain Monte Carlo
Jaehoon Yu, Hiroki Sugano, Ryusuke Miyamoto, Takao Onoye — APSIPA Annual Summit and Conference — International Conference — 2010
GPU Implementation of Efficient Pedestrian Detection Based on MCMC
Jaehoon Yu, Hiroki Sugano, Ryusuke Miyamoto, Takao Onoye — Joint International Conference on Soft Computing and Intelligent Systems and International Symposium on Advanced Intelligent Systems — International Conference — 2010
MCMC を用いた効率的な歩行者認識に関する研究
劉載勲, 菅野裕揮, 宮本龍介, 尾上孝雄 — 電子情報通信学会技術研究報告. SIS, スマートインフォメディアシステム — International Conference — 2010

2009

STP Engine, a C-based Programmable HW Core featuring Massively Parallel and Reconfigurable PE Array: Its Architecture, Tool, and System Implications
Masato Motomura — IEEE Symposium on Low-Power and High-Speed Chips (Cool Chips) — International Conference — 2009
Link

2007

Implementation of AV Streaming System Using Peer-to-Peer Communication
Norihiro Ishikawa, Hiroshi Tsutsui, Jaehoon Yu, Tomonori Izumi, Hiroyuki Ochi, Yukihiro Nakamura, Takaaki Komura, Yoshitaka Uchida — IEEE Consumer Communications and Networking Conference — International Conference — 2007
可変ウィンドウ手法に基づく高精度ステレオマッチングプロセッサ
宮本龍介, 劉載勲, 筒井弘, 中村行宏 — 画像電子学会誌 — Journal Papers — 2007

2006

可変ウィンドウステレオマッチングプロセッサのアーキテクチャ (映像信号処理)
宮本龍介, 劉載勲, 筒井弘 — 回路とシステム軽井沢ワークショップ論文集 — International Conference — 2006

2005

Implementation of AV Control System Over Universal P2P Network
Tomonori Izumi, Jaehoon Yu, Tetsuya Kimata, Hiroyuki Ochi, Yukihiro Nakamura — International Conference on Computing, Communications and Control Technologies — International Conference — 2005
情報家電ネットワークと携帯端末ネットワークをつなぐ P2P 動画配信システムの構築
劉載勲, 木全哲也, 越智直紀, 泉知論, 越智裕之, 中村行宏, 小俣栄治, 石川憲洋, others — 情報処理学会研究報告モバイルコンピューティングとユビキタス通信 (MBL) — International Conference — 2005

2002

A Dynamically Reconfigurable Processor Architecture
Masato Motomura — Microprocessor Forum (MPF) — International Conference — 2002
Link
New NEC Array Speeds Data NEC Introduces Its Dynamically Reconfigurable 512-Processor Array
Microprocessor Report — Books — 2002
Link