2020
|
101. | Junnosuke Suzuki, Kota Ando, Kazutoshi Hirose, Kazushi Kawamura, Thiem Van Chu, Masato Motomura, Jaehoon Yu ProgressiveNN: Achieving Computational Scalability without Network Alteration by MSB-first Accumulative Computation Proceedings Article In: International Symposium on Computing and Networking (CANDAR), 2020. @inproceedings{suzuki-candar2020,
title = {ProgressiveNN: Achieving Computational Scalability without Network Alteration by MSB-first Accumulative Computation},
author = {Junnosuke Suzuki and Kota Ando and Kazutoshi Hirose and Kazushi Kawamura and Thiem Van Chu and Masato Motomura and Jaehoon Yu},
year = {2020},
date = {2020-11-24},
booktitle = {International Symposium on Computing and Networking (CANDAR)},
keywords = {Conference Papers},
pubstate = {published},
tppubtype = {inproceedings}
}
|
102. | Masato Motomura [Invited] Designing AI Accelerator Chips for the Smarter Future Presentation IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA), 23.11.2020. @misc{motomura-icta2020,
title = {[Invited] Designing AI Accelerator Chips for the Smarter Future},
author = {Masato Motomura},
year = {2020},
date = {2020-11-23},
address = {IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)},
keywords = {Invited Talks},
pubstate = {published},
tppubtype = {presentation}
}
|
103. | Masato Motomura [Invited] Stochastic Cellular Automata Annealing (SCA) and its Non-Quantum Silicon Chip Implementation Presentation Seminar at National University of Singapore, 10.11.2020. @misc{motomura-nus2020,
title = {[Invited] Stochastic Cellular Automata Annealing (SCA) and its Non-Quantum Silicon Chip Implementation},
author = {Masato Motomura},
year = {2020},
date = {2020-11-10},
address = {Seminar at National University of Singapore},
keywords = {Invited Talks},
pubstate = {published},
tppubtype = {presentation}
}
|
104. | Daichi Fujiki, Shunhao Wu, Nathan Ozog, Kush Goliya, David T. Blaauw, Satish Narayanasamy, Reetuparna Das [IEEE CS Tokyo/Japan Joint Local Chapters Young Author Award 2022] SeedEx: A Genome Sequencing Accelerator for Optimal Alignments in Subminimal Space Proceedings Article In: International Symposium on Microarchitecture (MICRO), 2020. @inproceedings{ieee-cs-award-2022,
title = {[IEEE CS Tokyo/Japan Joint Local Chapters Young Author Award 2022] SeedEx: A Genome Sequencing Accelerator for Optimal Alignments in Subminimal Space},
author = {Daichi Fujiki and Shunhao Wu and Nathan Ozog and Kush Goliya and David T. Blaauw and Satish Narayanasamy and Reetuparna Das},
year = {2020},
date = {2020-10-22},
urldate = {2020-10-22},
booktitle = {International Symposium on Microarchitecture (MICRO)},
keywords = {Awards, Conference Papers},
pubstate = {published},
tppubtype = {inproceedings}
}
|
105. | Kasho Yamamoto, Kazushi Kawamura, Kota Ando, Normann Mertig, Takashi Takemoto, Masanao Yamaoka, Hiroshi Teramoto, Akira Sakai, Shinya Takamaeda-Yamazaki, Masato Motomura STATICA: A 512-Spin 0.25M-Weight Annealing Processor With an All-Spin-Updates-at-Once Architecture for Combinatorial Optimization With Complete Spin-Spin Interactions Journal Article In: IEEE Journal of Solid-State Circuits (JSSC), 2020. @article{statica-jssc,
title = {STATICA: A 512-Spin 0.25M-Weight Annealing Processor With an All-Spin-Updates-at-Once Architecture for Combinatorial Optimization With Complete Spin-Spin Interactions},
author = {Kasho Yamamoto and Kazushi Kawamura and Kota Ando and Normann Mertig and Takashi Takemoto and Masanao Yamaoka and Hiroshi Teramoto and Akira Sakai and Shinya Takamaeda-Yamazaki and Masato Motomura},
year = {2020},
date = {2020-10-13},
journal = {IEEE Journal of Solid-State Circuits (JSSC)},
keywords = {Journal Papers},
pubstate = {published},
tppubtype = {article}
}
|
106. | Ángel López García-Arias, Jaehoon Yu, Masanori Hashimoto Low-Cost Reservoir Computing using Cellular Automata and Random Forests Proceedings Article In: IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1-5, 2020. @inproceedings{reca-lopez-iscas2020,
title = {Low-Cost Reservoir Computing using Cellular Automata and Random Forests},
author = {Ángel López García-Arias and Jaehoon Yu and Masanori Hashimoto},
year = {2020},
date = {2020-10-10},
booktitle = {IEEE International Symposium on Circuits and Systems (ISCAS)},
pages = {1-5},
keywords = {Conference Papers},
pubstate = {published},
tppubtype = {inproceedings}
}
|
107. | Kota Shiba, Tatsuo Omori, Kodai Ueyoshi, Kota Ando, Kazutoshi Hirose, Shinya Takamaeda-Yamazaki, Masato Motomura, Mototsugu Hamada, Tadahiro Kuroda A 3D-Stacked SRAM Using Inductive Coupling with Low-Voltage Transmitter and 12:1 SerDes Proceedings Article In: IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1-5, 2020. @inproceedings{shiba-iscas2020,
title = {A 3D-Stacked SRAM Using Inductive Coupling with Low-Voltage Transmitter and 12:1 SerDes},
author = {Kota Shiba and Tatsuo Omori and Kodai Ueyoshi and Kota Ando and Kazutoshi Hirose and Shinya Takamaeda-Yamazaki and Masato Motomura and Mototsugu Hamada and Tadahiro Kuroda},
year = {2020},
date = {2020-10-10},
booktitle = {IEEE International Symposium on Circuits and Systems (ISCAS)},
pages = {1-5},
keywords = {Conference Papers},
pubstate = {published},
tppubtype = {inproceedings}
}
|
108. | Masato Motomura [Invited] Stochastic Cellular Automata Annealing (SCA) and its Non-Quantum Silicon Chip Implementation: Realizing Fully-Parallel Spin-Updates for Fully-Connected Spin Systems Presentation Conference on Quantum Annealing/Adiabatic Quantum Computation, 05.10.2020. @misc{motomura-quantumconf-2020,
title = {[Invited] Stochastic Cellular Automata Annealing (SCA) and its Non-Quantum Silicon Chip Implementation: Realizing Fully-Parallel Spin-Updates for Fully-Connected Spin Systems},
author = {Masato Motomura},
year = {2020},
date = {2020-10-05},
address = {Conference on Quantum Annealing/Adiabatic Quantum Computation},
keywords = {Invited Talks},
pubstate = {published},
tppubtype = {presentation}
}
|
109. | Kazuki Onishi, Jaehoon Yu, Masanori Hashimoto Memory Efficient Training using Lookup-Table-based Quantization for Neural Network Proceedings Article In: IEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS), pp. 251–255, IEEE 2020. @inproceedings{onishi2020memory,
title = {Memory Efficient Training using Lookup-Table-based Quantization for Neural Network},
author = {Kazuki Onishi and Jaehoon Yu and Masanori Hashimoto},
year = {2020},
date = {2020-09-04},
booktitle = {IEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS)},
pages = {251--255},
organization = {IEEE},
keywords = {Conference Papers},
pubstate = {published},
tppubtype = {inproceedings}
}
|
110. | 池田 泰我, 植吉 晃大, 安藤 洸太, 廣瀨 一俊, 浅井 哲也, 本村 真人, 高前田 伸也 [若手奨励賞] 効率的なDNN計算のための無効ニューロン予測手法の評価 Technical Report 情報処理学会 システム・アーキテクチャ研究会, 2020. @techreport{award-ikeda20190725,
title = {[若手奨励賞] 効率的なDNN計算のための無効ニューロン予測手法の評価},
author = {池田 泰我 and 植吉 晃大 and 安藤 洸太 and 廣瀨 一俊 and 浅井 哲也 and 本村 真人 and 高前田 伸也},
year = {2020},
date = {2020-07-25},
urldate = {2020-07-25},
address = {情報処理学会 システム・アーキテクチャ研究会},
keywords = {Awards, Technical Reports},
pubstate = {published},
tppubtype = {techreport}
}
|
111. | Yuki Hirayama, Tetsuya Asai, Masato Motomura, Shinya Takamaeda-Yamazaki A Hardware-Efficient Weight Sampling Circuit for Bayesian Neural Networks Journal Article In: International Journal of Networking and Computing, vol. 10, 2020. @article{hirayama-ijnc2020,
title = {A Hardware-Efficient Weight Sampling Circuit for Bayesian Neural Networks},
author = {Yuki Hirayama and Tetsuya Asai and Masato Motomura and Shinya Takamaeda-Yamazaki},
year = {2020},
date = {2020-07-01},
journal = {International Journal of Networking and Computing},
volume = {10},
keywords = {Journal Papers},
pubstate = {published},
tppubtype = {article}
}
|
112. | Tai-Yu Cheng, Yukata Masuda, Jun Chen, Jaehoon Yu, Masanori Hashimoto Logarithm-Approximate Floating-Point Multiplier is Applicable to Power-Efficient Neural Network Training Journal Article In: Integration, vol. 74, pp. 19–31, 2020. @article{cheng2020logarithm,
title = {Logarithm-Approximate Floating-Point Multiplier is Applicable to Power-Efficient Neural Network Training},
author = {Tai-Yu Cheng and Yukata Masuda and Jun Chen and Jaehoon Yu and Masanori Hashimoto},
year = {2020},
date = {2020-05-14},
journal = {Integration},
volume = {74},
pages = {19--31},
keywords = {Journal Papers},
pubstate = {published},
tppubtype = {article}
}
|
113. | 本村 真人, 高前田 伸也, 植吉 晃大, 安藤 洸太, 廣瀨 一俊 深層ニューラルネットワーク向けプロセッサ技術の実例と展望 Journal Article In: 電子情報通信学会和文論文誌C, vol. J103-C, no. 05, 2020. @article{Motomura-IEICE-C-2020,
title = {深層ニューラルネットワーク向けプロセッサ技術の実例と展望},
author = {本村 真人 and 高前田 伸也 and 植吉 晃大 and 安藤 洸太 and 廣瀨 一俊},
year = {2020},
date = {2020-05-01},
journal = {電子情報通信学会和文論文誌C},
volume = {J103-C},
number = {05},
keywords = {Journal Papers},
pubstate = {published},
tppubtype = {article}
}
|
114. | IEEE Spectrum Novel Annealing Processor Is the Best Ever at Solving Combinatorial Optimization Problems Book Section In: 2020. @incollection{statica-pressrelease-ieee,
title = {Novel Annealing Processor Is the Best Ever at Solving Combinatorial Optimization Problems},
author = {IEEE Spectrum},
url = {https://spectrum.ieee.org/tech-talk/computing/hardware/japanese-researchers-develop-a-novel-annealing-processor-thats-the-fastest-technology-yet-at-solving-combinatorial-optimization-problems},
year = {2020},
date = {2020-04-14},
keywords = {Press Releases},
pubstate = {published},
tppubtype = {incollection}
}
|
115. | Taiga Ikeda, Kento Sakurada, Atsuyoshi Nakamura, Masato Motomura, Shinya Takamaeda-Yamazaki Hardware/Algorithm Co-optimization for Fully-Parallelized Compact Decision Tree Ensembles on FPGAs Proceedings Article In: International Symposium on Applied Reconfigurable Computing (ARC), Universidad de Castilla-La Mancha, Toledo, Spain, 2020. @inproceedings{Motomura-ARC-2020,
title = {Hardware/Algorithm Co-optimization for Fully-Parallelized Compact Decision Tree Ensembles on FPGAs},
author = {Taiga Ikeda and Kento Sakurada and Atsuyoshi Nakamura and Masato Motomura and Shinya Takamaeda-Yamazaki},
year = {2020},
date = {2020-04-01},
booktitle = {International Symposium on Applied Reconfigurable Computing (ARC)},
address = {Universidad de Castilla-La Mancha, Toledo, Spain},
keywords = {Conference Papers},
pubstate = {published},
tppubtype = {inproceedings}
}
|
116. | 東工大プレスリリース 組合せ最適化問題を高速に解く新しいアニーリングマシンを開発 Book Section In: 2020, (日経新聞,毎日新聞,日経xTECH等各種ウェブメディアに掲載). @incollection{statica-pressrelease-tokodai,
title = {組合せ最適化問題を高速に解く新しいアニーリングマシンを開発},
author = {東工大プレスリリース},
url = {https://www.titech.ac.jp/news/2020/046309.html},
year = {2020},
date = {2020-02-18},
note = {日経新聞,毎日新聞,日経xTECH等各種ウェブメディアに掲載},
keywords = {Press Releases},
pubstate = {published},
tppubtype = {incollection}
}
|
117. | Masanori Hashimoto, Xu Bai, Naoki Banno, Munehiro Tada, Toshitsugu Sakamoto, Jaehoon Yu, Ryutaro Doi, Yusuke Araki, Hidetoshi Onodera, Takashi Imagawa, Hiroyuki Ochi, Kazutoshi Wakabayashi, Yukio Mitsuyama, Tadahiko Sugibayashi Via-Switch FPGA: 65nm CMOS Implementation and Architecture Extension for AI Applications Proceedings Article In: International Solid-State Circuits Conference (ISSCC), pp. 502–503, 2020. @inproceedings{id529,
title = {Via-Switch FPGA: 65nm CMOS Implementation and Architecture Extension for AI Applications},
author = {Masanori Hashimoto and Xu Bai and Naoki Banno and Munehiro Tada and Toshitsugu Sakamoto and Jaehoon Yu and Ryutaro Doi and Yusuke Araki and Hidetoshi Onodera and Takashi Imagawa and Hiroyuki Ochi and Kazutoshi Wakabayashi and Yukio Mitsuyama and Tadahiko Sugibayashi},
year = {2020},
date = {2020-02-17},
booktitle = {International Solid-State Circuits Conference (ISSCC)},
pages = {502--503},
keywords = {Conference Papers},
pubstate = {published},
tppubtype = {inproceedings}
}
|
118. | Kasho Yamamoto, Kota Ando, Normann Mertig, Takashi Takemoto, Masanao Yamaoka, Hiroshi Teramoto, Akira Sakai, Shinya Takamaeda-Yamazaki, Masato Motomura STATICA: A 512-Spin 0.25M-Weight Full-Digital Annealing Processor with a Near-Memory All-Spin-Updates-at-Once Architecture for Combinatorial Optimization with Complete Spin-Spin Interactions Proceedings Article In: International Solid-State Circuits Conference (ISSCC), pp. 138–139, 2020. @inproceedings{statica,
title = {STATICA: A 512-Spin 0.25M-Weight Full-Digital Annealing Processor with a Near-Memory All-Spin-Updates-at-Once Architecture for Combinatorial Optimization with Complete Spin-Spin Interactions},
author = {Kasho Yamamoto and Kota Ando and Normann Mertig and Takashi Takemoto and Masanao Yamaoka and Hiroshi Teramoto and Akira Sakai and Shinya Takamaeda-Yamazaki and Masato Motomura},
year = {2020},
date = {2020-02-17},
booktitle = {International Solid-State Circuits Conference (ISSCC)},
pages = {138--139},
keywords = {Conference Papers},
pubstate = {published},
tppubtype = {inproceedings}
}
|
119. | 本村 真人(監修) Q&Aで分かるAIチップ Book 週刊エコノミスト, 2020. @book{Motomura-ECONOMIST-2020,
title = {Q&Aで分かるAIチップ},
author = {本村 真人(監修)},
year = {2020},
date = {2020-02-04},
publisher = {週刊エコノミスト},
keywords = {Books},
pubstate = {published},
tppubtype = {book}
}
|
120. | 大羽 由華, 村上 大輔, 中江 達哉, 安藤 洸太, 浅井 哲也, 本村 真人, 高前田 伸也 [優秀若手発表賞] 二値化ニューラルネットワークのハードウェア指向精度向上手法の検討 Technical Report 電子情報通信学会 コンピュータシステム研究会, 2020. @techreport{award-oba20200123,
title = {[優秀若手発表賞] 二値化ニューラルネットワークのハードウェア指向精度向上手法の検討},
author = {大羽 由華 and 村上 大輔 and 中江 達哉 and 安藤 洸太 and 浅井 哲也 and 本村 真人 and 高前田 伸也},
year = {2020},
date = {2020-01-23},
urldate = {2020-01-23},
address = {電子情報通信学会 コンピュータシステム研究会},
keywords = {Awards, Technical Reports},
pubstate = {published},
tppubtype = {techreport}
}
|
121. | 植吉 晃大, 池田 泰我, 安藤 洸太, 廣瀨 一俊, 浅井 哲也, 高前田 伸也, 本村 真人 [優秀講演賞] 無効ニューロン予測によるDNN計算効率化手法 Technical Report 電子情報通信学会 リコンフィギャラブルシステム研究会, 2020. @techreport{award-ueyoshi20200123,
title = {[優秀講演賞] 無効ニューロン予測によるDNN計算効率化手法},
author = {植吉 晃大 and 池田 泰我 and 安藤 洸太 and 廣瀨 一俊 and 浅井 哲也 and 高前田 伸也 and 本村 真人},
year = {2020},
date = {2020-01-23},
urldate = {2020-01-23},
address = {電子情報通信学会 リコンフィギャラブルシステム研究会},
keywords = {Awards, Technical Reports},
pubstate = {published},
tppubtype = {techreport}
}
|
122. | Yafei Ou, Prasoon Ambalathankandy, Masayuki Ikebe, Shinya Takamaeda, Masato Motomura, Tetsuya Asai Real-time Tone Mapping: A State of the Art Report Journal Article In: IEEE Transactions on Circuits and Systems for Video Technology, 2020. @article{Motomura-TCSVT-2020,
title = {Real-time Tone Mapping: A State of the Art Report},
author = {Yafei Ou and Prasoon Ambalathankandy and Masayuki Ikebe and Shinya Takamaeda and Masato Motomura and Tetsuya Asai},
year = {2020},
date = {2020-01-01},
journal = {IEEE Transactions on Circuits and Systems for Video Technology},
keywords = {Journal Papers},
pubstate = {published},
tppubtype = {article}
}
|
123. | Thiem Van Chu, Kenji Kise, Kiyofumi Tanaka Dependency-Driven Trace-Based Network-on-Chip Emulation on FPGAs Proceedings Article In: ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA), pp. 211–221, 2020. @inproceedings{thiem-fpga2020,
title = {Dependency-Driven Trace-Based Network-on-Chip Emulation on FPGAs},
author = {Thiem Van Chu and Kenji Kise and Kiyofumi Tanaka},
year = {2020},
date = {2020-01-01},
booktitle = {ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA)},
pages = {211--221},
keywords = {Conference Papers},
pubstate = {published},
tppubtype = {inproceedings}
}
|
2019
|
124. | Masato Motomura [Invited] AI Computing: The Promised Land for Computer Architecture Innovation? Presentation Future Chips Forum, Tsinghua University, Beijin, China, 17.12.2019. @misc{Motomura-FCF-2019,
title = {[Invited] AI Computing: The Promised Land for Computer Architecture Innovation?},
author = {Masato Motomura},
year = {2019},
date = {2019-12-17},
address = {Future Chips Forum, Tsinghua University, Beijin, China},
keywords = {Invited Talks},
pubstate = {published},
tppubtype = {presentation}
}
|
125. | Prasoon Ambalathankandy, Yafei Ou, Jyotsna Kochiyil, Shinya Takamaeda-Yamazaki, Masato Motomura, Tetsuya Asai, Masayuki Ikebe Radiography Contrast Enhancement: Smoothed LHE Filter, a Practical Solution for Digital X-rays with Mach Band Proceedings Article In: International Conference on Digital Image Computing: Techniques and Applications, University of Western Australia, Perth, Australia, 2019. @inproceedings{Motomura-DICTA-2019,
title = {Radiography Contrast Enhancement: Smoothed LHE Filter, a Practical Solution for Digital X-rays with Mach Band},
author = {Prasoon Ambalathankandy and Yafei Ou and Jyotsna Kochiyil and Shinya Takamaeda-Yamazaki and Masato Motomura and Tetsuya Asai and Masayuki Ikebe},
year = {2019},
date = {2019-12-02},
booktitle = {International Conference on Digital Image Computing: Techniques and Applications},
address = {University of Western Australia, Perth, Australia},
keywords = {Conference Papers},
pubstate = {published},
tppubtype = {inproceedings}
}
|
126. | Kota Ando, Kodai Ueyoshi, Yuka Oba, Kazutoshi Hirose, Ryota Uematsu, Takumi Kudo, Masayuki Ikebe, Tetsuya Asai, Shinya Takamaeda-Yamazaki, Masato Motomura Dither NN: Hardware/Algorithm Co-Design for Accurate Quantized Neural Networks Journal Article In: IEICE Transactions on Information and Systems, vol. E102, 2019. @article{motomura_00003,
title = {Dither NN: Hardware/Algorithm Co-Design for Accurate Quantized Neural Networks},
author = {Kota Ando and Kodai Ueyoshi and Yuka Oba and Kazutoshi Hirose and Ryota Uematsu and Takumi Kudo and Masayuki Ikebe and Tetsuya Asai and Shinya Takamaeda-Yamazaki and Masato Motomura},
year = {2019},
date = {2019-12-01},
journal = {IEICE Transactions on Information and Systems},
volume = {E102},
keywords = {Journal Papers},
pubstate = {published},
tppubtype = {article}
}
|
127. | Kasho Yamamoto, Masayuki Ikebe, Tetsuya Asai, Masato Motomura, Shinya Takamaeda-Yamazaki FPGA-Based Annealing Processor with Time-Division Multiplexing Journal Article In: IEICE Transactions on Information and Systems, vol. E102, 2019. @article{motomura_00002,
title = {FPGA-Based Annealing Processor with Time-Division Multiplexing},
author = {Kasho Yamamoto and Masayuki Ikebe and Tetsuya Asai and Masato Motomura and Shinya Takamaeda-Yamazaki},
year = {2019},
date = {2019-12-01},
journal = {IEICE Transactions on Information and Systems},
volume = {E102},
keywords = {Journal Papers},
pubstate = {published},
tppubtype = {article}
}
|
128. | 本村 真人 AIエッジコンピューティングへの希望と展望 Book OKIテクニカルレビュー,「AIエッジコンピューティングが拓く高度IoT社会」特集,第234号, 2019. @book{motomura-oki-techreview-2019,
title = {AIエッジコンピューティングへの希望と展望},
author = {本村 真人},
year = {2019},
date = {2019-12-01},
publisher = {OKIテクニカルレビュー,「AIエッジコンピューティングが拓く高度IoT社会」特集,第234号},
keywords = {Books},
pubstate = {published},
tppubtype = {book}
}
|
129. | Prasoon Ambalathankandy, Masayuki Ikebe, Takashi Yoshida, Takeshi Shimada, Shinya Takamaeda-Yamazaki, Masato Motomura, Tetsuya Asai An Adaptive Global and Local Tone Mapping Algorithm Implemented on FPGA Journal Article In: IEEE Transactions on Circuits and Systems for Video Technology, vol. 29, 2019. @article{motomura_00001,
title = {An Adaptive Global and Local Tone Mapping Algorithm Implemented on FPGA},
author = {Prasoon Ambalathankandy and Masayuki Ikebe and Takashi Yoshida and Takeshi Shimada and Shinya Takamaeda-Yamazaki and Masato Motomura and Tetsuya Asai},
year = {2019},
date = {2019-12-01},
journal = {IEEE Transactions on Circuits and Systems for Video Technology},
volume = {29},
keywords = {Journal Papers},
pubstate = {published},
tppubtype = {article}
}
|
130. | 本村 真人 AIエッジコンピューティングへの希望と展望 Book OKIテクニカルレビュー、「AIエッジコンピューティングが拓く高度IoT社会」特集, 2019. @book{Motomura-OKI-2019,
title = {AIエッジコンピューティングへの希望と展望},
author = {本村 真人},
year = {2019},
date = {2019-12-01},
number = {234},
publisher = {OKIテクニカルレビュー、「AIエッジコンピューティングが拓く高度IoT社会」特集},
keywords = {Books},
pubstate = {published},
tppubtype = {book}
}
|
131. | Yuki Hirayama, Tetsuya Asai, Masato Motomura, Shinya Takamaeda-Yamazaki A Resource-Efficient Weight Sampling Method for Bayesian Neural Networks Accelerators Proceedings Article In: International Symposium on Computing and Networking (CANDAR), 2019. @inproceedings{Motomura-CANDAR-2019,
title = {A Resource-Efficient Weight Sampling Method for Bayesian Neural Networks Accelerators},
author = {Yuki Hirayama and Tetsuya Asai and Masato Motomura and Shinya Takamaeda-Yamazaki},
year = {2019},
date = {2019-11-26},
booktitle = {International Symposium on Computing and Networking (CANDAR)},
keywords = {Conference Papers},
pubstate = {published},
tppubtype = {inproceedings}
}
|
132. | Masato Motomura [Tutorial] AI Computing: What it is about & How hardware can help it out Presentation Asian Solid-State Circuit Conference (A-SSCC), Macau, SAR, China, 14.11.2019. @misc{Motomura-A-SSCC-2019,
title = {[Tutorial] AI Computing: What it is about & How hardware can help it out},
author = {Masato Motomura},
year = {2019},
date = {2019-11-14},
address = {Asian Solid-State Circuit Conference (A-SSCC), Macau, SAR, China},
keywords = {Invited Talks},
pubstate = {published},
tppubtype = {presentation}
}
|
133. | Shota Fukui, Jaehoon Yu, Masanori Hashimoto Distilling Knowledge for Non-Neural Networks Proceedings Article In: Asia-Pacific Signal and Information Processing Association (APSIPA), 2019. @inproceedings{2019-11-Fukui-APSIPA,
title = {Distilling Knowledge for Non-Neural Networks},
author = {Shota Fukui and Jaehoon Yu and Masanori Hashimoto},
year = {2019},
date = {2019-11-01},
booktitle = {Asia-Pacific Signal and Information Processing Association (APSIPA)},
keywords = {Conference Papers},
pubstate = {published},
tppubtype = {inproceedings}
}
|
134. | Toranosuke Tanio, Kouya Takeda, Jaehoon Yu, Masanori Hashimoto Training Data Reduction using Support Vectors for Neural Networks Proceedings Article In: Asia-Pacific Signal and Information Processing Association (APSIPA), 2019. @inproceedings{2019-11-Tanio-APSIPA,
title = {Training Data Reduction using Support Vectors for Neural Networks},
author = {Toranosuke Tanio and Kouya Takeda and Jaehoon Yu and Masanori Hashimoto},
year = {2019},
date = {2019-11-01},
booktitle = {Asia-Pacific Signal and Information Processing Association (APSIPA)},
keywords = {Conference Papers},
pubstate = {published},
tppubtype = {inproceedings}
}
|
135. | 本村 真人 [Invited] AIチップ: 世界の研究動向と東工大の研究戦略 Presentation 科学技術創成研究院公開,東工大すずかけ台キャンパス,横浜, 10.10.2019. @misc{Motomura-IIR-2019,
title = {[Invited] AIチップ: 世界の研究動向と東工大の研究戦略},
author = {本村 真人},
year = {2019},
date = {2019-10-10},
address = {科学技術創成研究院公開,東工大すずかけ台キャンパス,横浜},
keywords = {Invited Talks},
pubstate = {published},
tppubtype = {presentation}
}
|
136. | Tatsuya Kaneko, Kentaro Orimo, Itaru Hida, Shinya Takamaeda-Yamazaki, Masayuki Ikebe, Masato Motomura, Tetsuya Asai A Study on a Low Power Optimization Algorithm for An Edge-AI Device Journal Article In: Nonlinear Theory and Its Applications, vol. E10-N, no. 4, 2019. @article{motomura_00004,
title = {A Study on a Low Power Optimization Algorithm for An Edge-AI Device},
author = {Tatsuya Kaneko and Kentaro Orimo and Itaru Hida and Shinya Takamaeda-Yamazaki and Masayuki Ikebe and Masato Motomura and Tetsuya Asai},
year = {2019},
date = {2019-10-01},
journal = {Nonlinear Theory and Its Applications},
volume = {E10-N},
number = {4},
keywords = {Journal Papers},
pubstate = {published},
tppubtype = {article}
}
|
137. | 本村 真人 [Invited] AI関連半導体技術の動向 Presentation HAB研セミナー,京都テルサ,京都, 30.08.2019. @misc{Motomura-HAB-2019,
title = {[Invited] AI関連半導体技術の動向},
author = {本村 真人},
year = {2019},
date = {2019-08-30},
address = {HAB研セミナー,京都テルサ,京都},
keywords = {Invited Talks},
pubstate = {published},
tppubtype = {presentation}
}
|
138. | 本村 真人 [Invited] AIチップの世界動向と日本がとるべき戦略 Presentation EPFCシンポジウム,川崎ソリッドスクエア,川崎, 04.07.2019. @misc{Motomura-EPEC-2019,
title = {[Invited] AIチップの世界動向と日本がとるべき戦略},
author = {本村 真人},
year = {2019},
date = {2019-07-04},
address = {EPFCシンポジウム,川崎ソリッドスクエア,川崎},
keywords = {Invited Talks},
pubstate = {published},
tppubtype = {presentation}
}
|
139. | Tatsuya Kaneko, Masayuki Ikebe, Shinya Takamaeda-Yamazaki, Masato Motomura, Tetsuya Asai Hardware-Oriented Algorithm and Architecture for Generative Adversarial Networks Journal Article In: Journal of Signal Processing, vol. 23, no. 4, pp. 151-154, 2019. @article{motomura_00005,
title = {Hardware-Oriented Algorithm and Architecture for Generative Adversarial Networks},
author = {Tatsuya Kaneko and Masayuki Ikebe and Shinya Takamaeda-Yamazaki and Masato Motomura and Tetsuya Asai},
year = {2019},
date = {2019-07-01},
journal = {Journal of Signal Processing},
volume = {23},
number = {4},
pages = {151-154},
keywords = {Journal Papers},
pubstate = {published},
tppubtype = {article}
}
|
140. | Yuka Oba, Kota Ando, Tetsuya Asai, Masato Motomura, Shinya Takamaeda-Yamazaki DeltaNet: Differential Binary Neural Network Proceedings Article In: IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP), New York, USA, 2019. @inproceedings{motomura_00039b,
title = {DeltaNet: Differential Binary Neural Network},
author = {Yuka Oba and Kota Ando and Tetsuya Asai and Masato Motomura and Shinya Takamaeda-Yamazaki},
year = {2019},
date = {2019-07-01},
booktitle = {IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP)},
address = {New York, USA},
keywords = {Conference Papers},
pubstate = {published},
tppubtype = {inproceedings}
}
|
141. | 平山 侑樹, 浅井 哲也, 本村 真人, 高前田 伸也 [2019年度研究会優秀賞] 決定論的変分推論に基づくベイジアンCNNの検討 Technical Report 人工知能学会, 2019. @techreport{award-hirayama20190622,
title = {[2019年度研究会優秀賞] 決定論的変分推論に基づくベイジアンCNNの検討},
author = {平山 侑樹 and 浅井 哲也 and 本村 真人 and 高前田 伸也},
year = {2019},
date = {2019-06-22},
urldate = {2019-06-22},
address = {人工知能学会},
keywords = {Awards, Technical Reports},
pubstate = {published},
tppubtype = {techreport}
}
|
142. | 池田 泰我, 植吉 晃大, 安藤 洸太, 廣瀨 一俊, 浅井 哲也, 本村 真人, 高前田 伸也 [若手優秀講演賞] 効率的なDNN計算のための無効ニューロン予測手法の評価 Technical Report 電子情報通信学会 DC研究会, 2019. @techreport{award-ikeda20190611,
title = {[若手優秀講演賞] 効率的なDNN計算のための無効ニューロン予測手法の評価},
author = {池田 泰我 and 植吉 晃大 and 安藤 洸太 and 廣瀨 一俊 and 浅井 哲也 and 本村 真人 and 高前田 伸也},
year = {2019},
date = {2019-06-11},
urldate = {2019-06-11},
address = {電子情報通信学会 DC研究会},
keywords = {Awards, Technical Reports},
pubstate = {published},
tppubtype = {techreport}
}
|
143. | Shunya Suzuki, Seunggoo Rim, Shinya Takamaeda-Yamazaki, Masayuki Ikebe, Masato Motomura, Tetsuya Asai Experimental Demonstration of Physical Reservoir Computing with Nonlinear Electronic Devices Proceedings Article In: RISP International Workshop on Nonlinear Circuits, Communications and Signal Processing, Honolulu, USA, 2019. @inproceedings{motomura_00045b,
title = {Experimental Demonstration of Physical Reservoir Computing with Nonlinear Electronic Devices},
author = {Shunya Suzuki and Seunggoo Rim and Shinya Takamaeda-Yamazaki and Masayuki Ikebe and Masato Motomura and Tetsuya Asai},
year = {2019},
date = {2019-03-01},
booktitle = {RISP International Workshop on Nonlinear Circuits, Communications and Signal Processing},
address = {Honolulu, USA},
keywords = {Conference Papers},
pubstate = {published},
tppubtype = {inproceedings}
}
|
144. | Masato Motomura [Invited] AI Computing: The Promised Land for Hardware? Presentation Multimedia Workshop, Tokyo, Japan, 01.03.2019. @misc{motomura_00041,
title = {[Invited] AI Computing: The Promised Land for Hardware?},
author = {Masato Motomura},
year = {2019},
date = {2019-03-01},
address = {Multimedia Workshop, Tokyo, Japan},
keywords = {Invited Talks},
pubstate = {published},
tppubtype = {presentation}
}
|
145. | Masato Motomura [Invited] Intelligence at the Edge: Frontiers for Energy-Efficient Hardware Architectures Presentation Riken International Workshop on Neuromorphic Computing (R-WoNC), Kobe, Japan, 01.03.2019. @misc{motomura_00043,
title = {[Invited] Intelligence at the Edge: Frontiers for Energy-Efficient Hardware Architectures},
author = {Masato Motomura},
year = {2019},
date = {2019-03-01},
address = {Riken International Workshop on Neuromorphic Computing (R-WoNC), Kobe, Japan},
keywords = {Invited Talks},
pubstate = {published},
tppubtype = {presentation}
}
|
146. | Koyo Minamikawa, Shinya Takamaeda-Yamazaki, Masayuki Ikebe, Masato Motomura, Tetsuya Asai FPGA-Based FORCE Learning Accelerator towards Real-Time Online Reservoir Computing Proceedings Article In: RISP International Workshop on Nonlinear Circuits, Communications and Signal Processing, Honolulu, USA, 2019. @inproceedings{motomura_00046b,
title = {FPGA-Based FORCE Learning Accelerator towards Real-Time Online Reservoir Computing},
author = {Koyo Minamikawa and Shinya Takamaeda-Yamazaki and Masayuki Ikebe and Masato Motomura and Tetsuya Asai},
year = {2019},
date = {2019-03-01},
booktitle = {RISP International Workshop on Nonlinear Circuits, Communications and Signal Processing},
address = {Honolulu, USA},
keywords = {Conference Papers},
pubstate = {published},
tppubtype = {inproceedings}
}
|
147. | Tatsuya Kaneko, Masayuki Ikebe, Shinya Takamaeda-Yamazaki, Masato Motomura, Tetsuya Asai Hardware-Oriented Algorithm and Architecture for Generative Adversarial Networks Proceedings Article In: RISP International Workshop on Nonlinear Circuits, Communications and Signal Processing, Honolulu, USA, 2019. @inproceedings{motomura_00044b,
title = {Hardware-Oriented Algorithm and Architecture for Generative Adversarial Networks},
author = {Tatsuya Kaneko and Masayuki Ikebe and Shinya Takamaeda-Yamazaki and Masato Motomura and Tetsuya Asai},
year = {2019},
date = {2019-03-01},
booktitle = {RISP International Workshop on Nonlinear Circuits, Communications and Signal Processing},
address = {Honolulu, USA},
keywords = {Conference Papers},
pubstate = {published},
tppubtype = {inproceedings}
}
|
148. | 本村 真人 コンピューティングアーキテクチャ Book JST CRDS 研究開発の俯瞰報告書 2019年版, 2019. @book{motomura-jstcrds-2019,
title = {コンピューティングアーキテクチャ},
author = {本村 真人},
year = {2019},
date = {2019-03-01},
publisher = {JST CRDS 研究開発の俯瞰報告書 2019年版},
keywords = {Books},
pubstate = {published},
tppubtype = {book}
}
|
149. | Tatsuya Kaneko, Masayuki Ikebe, Shinya Takamaeda-Yamazaki, Masato Motomura, Tetsuya Asai Ternarized Backpropagation: A Hardware-Oriented Optimization Algorithm for Edge-Oriented AI Devices Proceedings Article In: RIEC International Symposium on Brain Functions and Brain Computer, Sendai, Japan, 2019. @inproceedings{motomura_00047,
title = {Ternarized Backpropagation: A Hardware-Oriented Optimization Algorithm for Edge-Oriented AI Devices},
author = {Tatsuya Kaneko and Masayuki Ikebe and Shinya Takamaeda-Yamazaki and Masato Motomura and Tetsuya Asai},
year = {2019},
date = {2019-02-01},
booktitle = {RIEC International Symposium on Brain Functions and Brain Computer},
address = {Sendai, Japan},
keywords = {Conference Papers},
pubstate = {published},
tppubtype = {inproceedings}
}
|
150. | Salita Sombatsiri, Seiya Shibata, Yuki Kobayashi, Hiroaki Inoue, Takashi Takenaka, Takeo Hosomi, Jaehoon Yu, Yoshinori Takeuchi Parallelism-Flexible Convolution Core for Sparse Convolutional Neural Networks on FPGA Journal Article In: vol. 12, pp. 22–37, 2019. @article{sombatsiri2019parallelism,
title = {Parallelism-Flexible Convolution Core for Sparse Convolutional Neural Networks on FPGA},
author = {Salita Sombatsiri and Seiya Shibata and Yuki Kobayashi and Hiroaki Inoue and Takashi Takenaka and Takeo Hosomi and Jaehoon Yu and Yoshinori Takeuchi},
year = {2019},
date = {2019-01-01},
volume = {12},
pages = {22--37},
keywords = {Journal Papers},
pubstate = {published},
tppubtype = {article}
}
|