2019
|
101. | Kasho Yamamoto, Masayuki Ikebe, Tetsuya Asai, Masato Motomura, Shinya Takamaeda-Yamazaki FPGA-Based Annealing Processor with Time-Division Multiplexing Journal Article In: IEICE Transactions on Information and Systems, vol. E102, 2019. @article{motomura_00002,
title = {FPGA-Based Annealing Processor with Time-Division Multiplexing},
author = {Kasho Yamamoto and Masayuki Ikebe and Tetsuya Asai and Masato Motomura and Shinya Takamaeda-Yamazaki},
year = {2019},
date = {2019-12-01},
journal = {IEICE Transactions on Information and Systems},
volume = {E102},
keywords = {Journal Papers},
pubstate = {published},
tppubtype = {article}
}
|
102. | Kota Ando, Kodai Ueyoshi, Yuka Oba, Kazutoshi Hirose, Ryota Uematsu, Takumi Kudo, Masayuki Ikebe, Tetsuya Asai, Shinya Takamaeda-Yamazaki, Masato Motomura Dither NN: Hardware/Algorithm Co-Design for Accurate Quantized Neural Networks Journal Article In: IEICE Transactions on Information and Systems, vol. E102, 2019. @article{motomura_00003,
title = {Dither NN: Hardware/Algorithm Co-Design for Accurate Quantized Neural Networks},
author = {Kota Ando and Kodai Ueyoshi and Yuka Oba and Kazutoshi Hirose and Ryota Uematsu and Takumi Kudo and Masayuki Ikebe and Tetsuya Asai and Shinya Takamaeda-Yamazaki and Masato Motomura},
year = {2019},
date = {2019-12-01},
journal = {IEICE Transactions on Information and Systems},
volume = {E102},
keywords = {Journal Papers},
pubstate = {published},
tppubtype = {article}
}
|
103. | 本村 真人 AIエッジコンピューティングへの希望と展望 Book OKIテクニカルレビュー,「AIエッジコンピューティングが拓く高度IoT社会」特集,第234号, 2019. @book{motomura-oki-techreview-2019,
title = {AIエッジコンピューティングへの希望と展望},
author = {本村 真人},
year = {2019},
date = {2019-12-01},
publisher = {OKIテクニカルレビュー,「AIエッジコンピューティングが拓く高度IoT社会」特集,第234号},
keywords = {Books},
pubstate = {published},
tppubtype = {book}
}
|
104. | Yuki Hirayama, Tetsuya Asai, Masato Motomura, Shinya Takamaeda-Yamazaki A Resource-Efficient Weight Sampling Method for Bayesian Neural Networks Accelerators Proceedings Article In: International Symposium on Computing and Networking (CANDAR), 2019. @inproceedings{Motomura-CANDAR-2019,
title = {A Resource-Efficient Weight Sampling Method for Bayesian Neural Networks Accelerators},
author = {Yuki Hirayama and Tetsuya Asai and Masato Motomura and Shinya Takamaeda-Yamazaki},
year = {2019},
date = {2019-11-26},
booktitle = {International Symposium on Computing and Networking (CANDAR)},
keywords = {Conference Papers},
pubstate = {published},
tppubtype = {inproceedings}
}
|
105. | Masato Motomura [Tutorial] AI Computing: What it is about & How hardware can help it out Presentation Asian Solid-State Circuit Conference (A-SSCC), Macau, SAR, China, 14.11.2019. @misc{Motomura-A-SSCC-2019,
title = {[Tutorial] AI Computing: What it is about & How hardware can help it out},
author = {Masato Motomura},
year = {2019},
date = {2019-11-14},
address = {Asian Solid-State Circuit Conference (A-SSCC), Macau, SAR, China},
keywords = {Invited Talks},
pubstate = {published},
tppubtype = {presentation}
}
|
106. | Toranosuke Tanio, Kouya Takeda, Jaehoon Yu, Masanori Hashimoto Training Data Reduction using Support Vectors for Neural Networks Proceedings Article In: Asia-Pacific Signal and Information Processing Association (APSIPA), 2019. @inproceedings{2019-11-Tanio-APSIPA,
title = {Training Data Reduction using Support Vectors for Neural Networks},
author = {Toranosuke Tanio and Kouya Takeda and Jaehoon Yu and Masanori Hashimoto},
year = {2019},
date = {2019-11-01},
booktitle = {Asia-Pacific Signal and Information Processing Association (APSIPA)},
keywords = {Conference Papers},
pubstate = {published},
tppubtype = {inproceedings}
}
|
107. | Shota Fukui, Jaehoon Yu, Masanori Hashimoto Distilling Knowledge for Non-Neural Networks Proceedings Article In: Asia-Pacific Signal and Information Processing Association (APSIPA), 2019. @inproceedings{2019-11-Fukui-APSIPA,
title = {Distilling Knowledge for Non-Neural Networks},
author = {Shota Fukui and Jaehoon Yu and Masanori Hashimoto},
year = {2019},
date = {2019-11-01},
booktitle = {Asia-Pacific Signal and Information Processing Association (APSIPA)},
keywords = {Conference Papers},
pubstate = {published},
tppubtype = {inproceedings}
}
|
108. | 本村 真人 [Invited] AIチップ: 世界の研究動向と東工大の研究戦略 Presentation 科学技術創成研究院公開,東工大すずかけ台キャンパス,横浜, 10.10.2019. @misc{Motomura-IIR-2019,
title = {[Invited] AIチップ: 世界の研究動向と東工大の研究戦略},
author = {本村 真人},
year = {2019},
date = {2019-10-10},
address = {科学技術創成研究院公開,東工大すずかけ台キャンパス,横浜},
keywords = {Invited Talks},
pubstate = {published},
tppubtype = {presentation}
}
|
109. | Tatsuya Kaneko, Kentaro Orimo, Itaru Hida, Shinya Takamaeda-Yamazaki, Masayuki Ikebe, Masato Motomura, Tetsuya Asai A Study on a Low Power Optimization Algorithm for An Edge-AI Device Journal Article In: Nonlinear Theory and Its Applications, vol. E10-N, no. 4, 2019. @article{motomura_00004,
title = {A Study on a Low Power Optimization Algorithm for An Edge-AI Device},
author = {Tatsuya Kaneko and Kentaro Orimo and Itaru Hida and Shinya Takamaeda-Yamazaki and Masayuki Ikebe and Masato Motomura and Tetsuya Asai},
year = {2019},
date = {2019-10-01},
journal = {Nonlinear Theory and Its Applications},
volume = {E10-N},
number = {4},
keywords = {Journal Papers},
pubstate = {published},
tppubtype = {article}
}
|
110. | 本村 真人 [Invited] AI関連半導体技術の動向 Presentation HAB研セミナー,京都テルサ,京都, 30.08.2019. @misc{Motomura-HAB-2019,
title = {[Invited] AI関連半導体技術の動向},
author = {本村 真人},
year = {2019},
date = {2019-08-30},
address = {HAB研セミナー,京都テルサ,京都},
keywords = {Invited Talks},
pubstate = {published},
tppubtype = {presentation}
}
|
111. | 本村 真人 [Invited] AIチップの世界動向と日本がとるべき戦略 Presentation EPFCシンポジウム,川崎ソリッドスクエア,川崎, 04.07.2019. @misc{Motomura-EPEC-2019,
title = {[Invited] AIチップの世界動向と日本がとるべき戦略},
author = {本村 真人},
year = {2019},
date = {2019-07-04},
address = {EPFCシンポジウム,川崎ソリッドスクエア,川崎},
keywords = {Invited Talks},
pubstate = {published},
tppubtype = {presentation}
}
|
112. | Yuka Oba, Kota Ando, Tetsuya Asai, Masato Motomura, Shinya Takamaeda-Yamazaki DeltaNet: Differential Binary Neural Network Proceedings Article In: IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP), New York, USA, 2019. @inproceedings{motomura_00039b,
title = {DeltaNet: Differential Binary Neural Network},
author = {Yuka Oba and Kota Ando and Tetsuya Asai and Masato Motomura and Shinya Takamaeda-Yamazaki},
year = {2019},
date = {2019-07-01},
booktitle = {IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP)},
address = {New York, USA},
keywords = {Conference Papers},
pubstate = {published},
tppubtype = {inproceedings}
}
|
113. | Tatsuya Kaneko, Masayuki Ikebe, Shinya Takamaeda-Yamazaki, Masato Motomura, Tetsuya Asai Hardware-Oriented Algorithm and Architecture for Generative Adversarial Networks Journal Article In: Journal of Signal Processing, vol. 23, no. 4, pp. 151-154, 2019. @article{motomura_00005,
title = {Hardware-Oriented Algorithm and Architecture for Generative Adversarial Networks},
author = {Tatsuya Kaneko and Masayuki Ikebe and Shinya Takamaeda-Yamazaki and Masato Motomura and Tetsuya Asai},
year = {2019},
date = {2019-07-01},
journal = {Journal of Signal Processing},
volume = {23},
number = {4},
pages = {151-154},
keywords = {Journal Papers},
pubstate = {published},
tppubtype = {article}
}
|
114. | 平山 侑樹, 浅井 哲也, 本村 真人, 高前田 伸也 決定論的変分推論に基づくベイジアンCNNの検討 Book Section In: 人工知能学会 - 2019年度研究会優秀賞, 2019. @incollection{award-hirayama20190622,
title = {決定論的変分推論に基づくベイジアンCNNの検討},
author = {平山 侑樹 and 浅井 哲也 and 本村 真人 and 高前田 伸也},
year = {2019},
date = {2019-06-22},
booktitle = {人工知能学会 - 2019年度研究会優秀賞},
keywords = {Awards},
pubstate = {published},
tppubtype = {incollection}
}
|
115. | 池田 泰我, 植吉 晃大, 安藤 洸太, 廣瀨 一俊, 浅井 哲也, 本村 真人, 高前田 伸也 効率的なDNN計算のための無効ニューロン予測手法の評価 Book Section In: 電子情報通信学会 DC研究会 - 若手優秀講演賞, 2019. @incollection{award-ikeda20190611,
title = {効率的なDNN計算のための無効ニューロン予測手法の評価},
author = {池田 泰我 and 植吉 晃大 and 安藤 洸太 and 廣瀨 一俊 and 浅井 哲也 and 本村 真人 and 高前田 伸也},
year = {2019},
date = {2019-06-11},
booktitle = {電子情報通信学会 DC研究会 - 若手優秀講演賞},
keywords = {Awards},
pubstate = {published},
tppubtype = {incollection}
}
|
116. | Tatsuya Kaneko, Masayuki Ikebe, Shinya Takamaeda-Yamazaki, Masato Motomura, Tetsuya Asai Hardware-Oriented Algorithm and Architecture for Generative Adversarial Networks Proceedings Article In: RISP International Workshop on Nonlinear Circuits, Communications and Signal Processing, Honolulu, USA, 2019. @inproceedings{motomura_00044b,
title = {Hardware-Oriented Algorithm and Architecture for Generative Adversarial Networks},
author = {Tatsuya Kaneko and Masayuki Ikebe and Shinya Takamaeda-Yamazaki and Masato Motomura and Tetsuya Asai},
year = {2019},
date = {2019-03-01},
booktitle = {RISP International Workshop on Nonlinear Circuits, Communications and Signal Processing},
address = {Honolulu, USA},
keywords = {Conference Papers},
pubstate = {published},
tppubtype = {inproceedings}
}
|
117. | Shunya Suzuki, Seunggoo Rim, Shinya Takamaeda-Yamazaki, Masayuki Ikebe, Masato Motomura, Tetsuya Asai Experimental Demonstration of Physical Reservoir Computing with Nonlinear Electronic Devices Proceedings Article In: RISP International Workshop on Nonlinear Circuits, Communications and Signal Processing, Honolulu, USA, 2019. @inproceedings{motomura_00045b,
title = {Experimental Demonstration of Physical Reservoir Computing with Nonlinear Electronic Devices},
author = {Shunya Suzuki and Seunggoo Rim and Shinya Takamaeda-Yamazaki and Masayuki Ikebe and Masato Motomura and Tetsuya Asai},
year = {2019},
date = {2019-03-01},
booktitle = {RISP International Workshop on Nonlinear Circuits, Communications and Signal Processing},
address = {Honolulu, USA},
keywords = {Conference Papers},
pubstate = {published},
tppubtype = {inproceedings}
}
|
118. | Koyo Minamikawa, Shinya Takamaeda-Yamazaki, Masayuki Ikebe, Masato Motomura, Tetsuya Asai FPGA-Based FORCE Learning Accelerator towards Real-Time Online Reservoir Computing Proceedings Article In: RISP International Workshop on Nonlinear Circuits, Communications and Signal Processing, Honolulu, USA, 2019. @inproceedings{motomura_00046b,
title = {FPGA-Based FORCE Learning Accelerator towards Real-Time Online Reservoir Computing},
author = {Koyo Minamikawa and Shinya Takamaeda-Yamazaki and Masayuki Ikebe and Masato Motomura and Tetsuya Asai},
year = {2019},
date = {2019-03-01},
booktitle = {RISP International Workshop on Nonlinear Circuits, Communications and Signal Processing},
address = {Honolulu, USA},
keywords = {Conference Papers},
pubstate = {published},
tppubtype = {inproceedings}
}
|
119. | 本村 真人 コンピューティングアーキテクチャ Book JST CRDS 研究開発の俯瞰報告書 2019年版, 2019. @book{motomura-jstcrds-2019,
title = {コンピューティングアーキテクチャ},
author = {本村 真人},
year = {2019},
date = {2019-03-01},
publisher = {JST CRDS 研究開発の俯瞰報告書 2019年版},
keywords = {Books},
pubstate = {published},
tppubtype = {book}
}
|
120. | Masato Motomura [Invited] Intelligence at the Edge: Frontiers for Energy-Efficient Hardware Architectures Presentation Riken International Workshop on Neuromorphic Computing (R-WoNC), Kobe, Japan, 01.03.2019. @misc{motomura_00043,
title = {[Invited] Intelligence at the Edge: Frontiers for Energy-Efficient Hardware Architectures},
author = {Masato Motomura},
year = {2019},
date = {2019-03-01},
address = {Riken International Workshop on Neuromorphic Computing (R-WoNC), Kobe, Japan},
keywords = {Invited Talks},
pubstate = {published},
tppubtype = {presentation}
}
|
121. | Masato Motomura [Invited] AI Computing: The Promised Land for Hardware? Presentation Multimedia Workshop, Tokyo, Japan, 01.03.2019. @misc{motomura_00041,
title = {[Invited] AI Computing: The Promised Land for Hardware?},
author = {Masato Motomura},
year = {2019},
date = {2019-03-01},
address = {Multimedia Workshop, Tokyo, Japan},
keywords = {Invited Talks},
pubstate = {published},
tppubtype = {presentation}
}
|
122. | Tatsuya Kaneko, Masayuki Ikebe, Shinya Takamaeda-Yamazaki, Masato Motomura, Tetsuya Asai Ternarized Backpropagation: A Hardware-Oriented Optimization Algorithm for Edge-Oriented AI Devices Proceedings Article In: RIEC International Symposium on Brain Functions and Brain Computer, Sendai, Japan, 2019. @inproceedings{motomura_00047,
title = {Ternarized Backpropagation: A Hardware-Oriented Optimization Algorithm for Edge-Oriented AI Devices},
author = {Tatsuya Kaneko and Masayuki Ikebe and Shinya Takamaeda-Yamazaki and Masato Motomura and Tetsuya Asai},
year = {2019},
date = {2019-02-01},
booktitle = {RIEC International Symposium on Brain Functions and Brain Computer},
address = {Sendai, Japan},
keywords = {Conference Papers},
pubstate = {published},
tppubtype = {inproceedings}
}
|
123. | Seunggoo Rim, Shunya Suzuki, Shinya Takamaeda-Yamazaki, Masayuki Ikebe, Masato Motomura, Tetsuya Asai Approach to Reservoir Computing with Schmitt Trigger Oscillator-Based Analog Neural Circuits Proceedings Article In: Japan-Korea Joint Workshop on Complex Communication Sciences, Pyengonchang, Korea, 2019. @inproceedings{motomura_00049,
title = {Approach to Reservoir Computing with Schmitt Trigger Oscillator-Based Analog Neural Circuits},
author = {Seunggoo Rim and Shunya Suzuki and Shinya Takamaeda-Yamazaki and Masayuki Ikebe and Masato Motomura and Tetsuya Asai},
year = {2019},
date = {2019-01-01},
booktitle = {Japan-Korea Joint Workshop on Complex Communication Sciences},
address = {Pyengonchang, Korea},
keywords = {Conference Papers},
pubstate = {published},
tppubtype = {inproceedings}
}
|
124. | Ryutaro Doi, Jaehoon Yu, Masanori Hashimoto Sneak Path Free Reconfiguration with Minimized Programming Steps for Via-switch Crossbar Based FPGA Journal Article In: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, pp. 1-1, 2019, ISSN: 1937-4151. @article{8935433,
title = {Sneak Path Free Reconfiguration with Minimized Programming Steps for Via-switch Crossbar Based FPGA},
author = {Ryutaro Doi and Jaehoon Yu and Masanori Hashimoto},
issn = {1937-4151},
year = {2019},
date = {2019-01-01},
journal = {IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems},
pages = {1-1},
keywords = {Journal Papers},
pubstate = {published},
tppubtype = {article}
}
|
125. | Thiem Van Chu, Kenji Kise LEF: An Effective Routing Algorithm for Two-Dimensional Meshes Journal Article In: IEICE Transactions on Information and Systems, vol. E102-D, no. 10, pp. 1925–1941, 2019. @article{thiem-ieice2019,
title = {LEF: An Effective Routing Algorithm for Two-Dimensional Meshes},
author = {Thiem Van Chu and Kenji Kise},
year = {2019},
date = {2019-01-01},
journal = {IEICE Transactions on Information and Systems},
volume = {E102-D},
number = {10},
pages = {1925--1941},
keywords = {Journal Papers},
pubstate = {published},
tppubtype = {article}
}
|
126. | Salita Sombatsiri, Seiya Shibata, Yuki Kobayashi, Hiroaki Inoue, Takashi Takenaka, Takeo Hosomi, Jaehoon Yu, Yoshinori Takeuchi Parallelism-Flexible Convolution Core for Sparse Convolutional Neural Networks on FPGA Journal Article In: vol. 12, pp. 22–37, 2019. @article{sombatsiri2019parallelism,
title = {Parallelism-Flexible Convolution Core for Sparse Convolutional Neural Networks on FPGA},
author = {Salita Sombatsiri and Seiya Shibata and Yuki Kobayashi and Hiroaki Inoue and Takashi Takenaka and Takeo Hosomi and Jaehoon Yu and Yoshinori Takeuchi},
year = {2019},
date = {2019-01-01},
volume = {12},
pages = {22--37},
keywords = {Journal Papers},
pubstate = {published},
tppubtype = {article}
}
|
127. | Tai-Yu Cheng, Jaehoon Yu, Masanori Hashimoto Minimizing Energy for Neural Network Training with Logarithm-Approximate Floating-Point Multiplier Proceedings Article In: International Symposium on Power and Timing Modeling, Optimization and Simulation, pp. 91–96, 2019. @inproceedings{cheng-patmos-2019,
title = {Minimizing Energy for Neural Network Training with Logarithm-Approximate Floating-Point Multiplier},
author = {Tai-Yu Cheng and Jaehoon Yu and Masanori Hashimoto},
year = {2019},
date = {2019-01-01},
booktitle = {International Symposium on Power and Timing Modeling, Optimization and Simulation},
pages = {91--96},
keywords = {},
pubstate = {published},
tppubtype = {inproceedings}
}
|
128. | Kodai Ueyoshi, Kota Ando, Kazutoshi Hirose, Shinya Takamaeda-Yamazaki, Mototsugu Hamada, Tadahiro Kuroda, Masato Motomura QUEST: Multi-Purpose Log-Quantized DNN Inference Engine Stacked on 96-MB 3-D SRAM Using Inductive Coupling Technology in 40-nm CMOS Journal Article In: IEEE Journal of Solid-State Circuits, vol. 54, no. 1, pp. 186-196, 2019. @article{motomura_00006,
title = {QUEST: Multi-Purpose Log-Quantized DNN Inference Engine Stacked on 96-MB 3-D SRAM Using Inductive Coupling Technology in 40-nm CMOS},
author = {Kodai Ueyoshi and Kota Ando and Kazutoshi Hirose and Shinya Takamaeda-Yamazaki and Mototsugu Hamada and Tadahiro Kuroda and Masato Motomura},
year = {2019},
date = {2019-01-01},
journal = {IEEE Journal of Solid-State Circuits},
volume = {54},
number = {1},
pages = {186-196},
keywords = {Journal Papers},
pubstate = {published},
tppubtype = {article}
}
|
129. | 本村 真人 深層学習プロセッサの展望 Book 映像メディア学会誌「データ科学を支えるアクセラレーション技術」特集, 2019. @book{motomura-jstcrds-2019b,
title = {深層学習プロセッサの展望},
author = {本村 真人},
year = {2019},
date = {2019-01-01},
publisher = {映像メディア学会誌「データ科学を支えるアクセラレーション技術」特集},
keywords = {Books},
pubstate = {published},
tppubtype = {book}
}
|
2018
|
130. | Kota Ando, Kodai Ueyoshi, Yuka Oba, Kazutoshi Hirose, Ryota Uematsu, Takumi Kudo, Masayuki Ikebe, Tetsuya Asai, Shinya Takamaeda-Yamazaki, Masato Motomura Dither NN: An Accurate Neural Network with Dithering for Low Bit-Precision Hardware Proceedings Article In: International Conference on Field-Programmable Technology (FPT), Naha, Japan, 2018. @inproceedings{motomura_00050,
title = {Dither NN: An Accurate Neural Network with Dithering for Low Bit-Precision Hardware},
author = {Kota Ando and Kodai Ueyoshi and Yuka Oba and Kazutoshi Hirose and Ryota Uematsu and Takumi Kudo and Masayuki Ikebe and Tetsuya Asai and Shinya Takamaeda-Yamazaki and Masato Motomura},
year = {2018},
date = {2018-12-01},
booktitle = {International Conference on Field-Programmable Technology (FPT)},
address = {Naha, Japan},
keywords = {Conference Papers},
pubstate = {published},
tppubtype = {inproceedings}
}
|
131. | Prasoon Ambalathankandy, Takeshi Shimada, Shinya Takamaeda-Yamazaki, Masato Motomura, Tetsuya Asai, Masayuki Ikebe Analysis of Smoothed LHE Methods for Processing Images with Optical Illusions Proceedings Article In: IEEE International Conference on Visual Communications and Image Processing, Taichung, Taiwan, 2018. @inproceedings{motomura_00052,
title = {Analysis of Smoothed LHE Methods for Processing Images with Optical Illusions},
author = {Prasoon Ambalathankandy and Takeshi Shimada and Shinya Takamaeda-Yamazaki and Masato Motomura and Tetsuya Asai and Masayuki Ikebe},
year = {2018},
date = {2018-12-01},
booktitle = {IEEE International Conference on Visual Communications and Image Processing},
address = {Taichung, Taiwan},
keywords = {Conference Papers},
pubstate = {published},
tppubtype = {inproceedings}
}
|
132. | Prasoon Ambalathankandy, Shinya Takamaeda-Yamazaki, Masato Motomura, Tetsuya Asai, Masayuki Ikebe, Hotaka Kusano Real-time HDTV to 4K and 8K-UHD Conversions Using Anti-Aliasing Based Super Resolution Algorithm on FPGA Journal Article In: Microprocessors and Microsystems, vol. 60, 2018. @article{motomura_00007,
title = {Real-time HDTV to 4K and 8K-UHD Conversions Using Anti-Aliasing Based Super Resolution Algorithm on FPGA},
author = {Prasoon Ambalathankandy and Shinya Takamaeda-Yamazaki and Masato Motomura and Tetsuya Asai and Masayuki Ikebe and Hotaka Kusano},
year = {2018},
date = {2018-12-01},
journal = {Microprocessors and Microsystems},
volume = {60},
keywords = {Journal Papers},
pubstate = {published},
tppubtype = {article}
}
|
133. | Masato Motomura [Invited] Structure-Oriented Computing: Where Software Redefines Hardware Architecture Presentation Future Chips Forum, Beijing, China, 01.12.2018. @misc{motomura_00051,
title = {[Invited] Structure-Oriented Computing: Where Software Redefines Hardware Architecture},
author = {Masato Motomura},
year = {2018},
date = {2018-12-01},
address = {Future Chips Forum, Beijing, China},
keywords = {Invited Talks},
pubstate = {published},
tppubtype = {presentation}
}
|
134. | Masato Motomura [Invited] Intelligence at the Edge: Frontiers for Energy-Efficient Hardware Architectures Presentation International IoT Solid-State Circuits Workshop, Hshinchu, Taiwan, 01.11.2018. @misc{motomura_00055,
title = {[Invited] Intelligence at the Edge: Frontiers for Energy-Efficient Hardware Architectures},
author = {Masato Motomura},
year = {2018},
date = {2018-11-01},
address = {International IoT Solid-State Circuits Workshop, Hshinchu, Taiwan},
keywords = {Invited Talks},
pubstate = {published},
tppubtype = {presentation}
}
|
135. | Tatsuya Kaneko, Masayuki Ikebe, Shinya Takamaeda-Yamazaki, Masato Motomura, Tetsuya Asai A Study on Ternary Back Propagation Algorithm for Embedded Egde-AI Processing Proceedings Article In: Joint Workshop of UCL-ICN, NTT, UCL-Gatsby and AIBS: Analysis and Synthesis for Human/Artificial Cognition and Behaviour, Okinawa, Japan, 2018. @inproceedings{motomura_00057,
title = {A Study on Ternary Back Propagation Algorithm for Embedded Egde-AI Processing},
author = {Tatsuya Kaneko and Masayuki Ikebe and Shinya Takamaeda-Yamazaki and Masato Motomura and Tetsuya Asai},
year = {2018},
date = {2018-10-01},
booktitle = {Joint Workshop of UCL-ICN, NTT, UCL-Gatsby and AIBS: Analysis and Synthesis for Human/Artificial Cognition and Behaviour},
address = {Okinawa, Japan},
keywords = {Conference Papers},
pubstate = {published},
tppubtype = {inproceedings}
}
|
136. | Kazutoshi Hirose, Ryota Uematsu, Kota Ando, Kodai Ueyoshi, Masayuki Ikebe, Tetsuya Asai, Masato Motomura, Shinya Takamaeda-Yamazaki Quantization Error-Based Regularization for Hardware-Aware Neural Network Training Journal Article In: Nonlinear Theory and Its Applications, vol. E9-N, no. 4, pp. 453-465, 2018. @article{motomura_00008,
title = {Quantization Error-Based Regularization for Hardware-Aware Neural Network Training},
author = {Kazutoshi Hirose and Ryota Uematsu and Kota Ando and Kodai Ueyoshi and Masayuki Ikebe and Tetsuya Asai and Masato Motomura and Shinya Takamaeda-Yamazaki},
year = {2018},
date = {2018-10-01},
journal = {Nonlinear Theory and Its Applications},
volume = {E9-N},
number = {4},
pages = {453-465},
keywords = {Journal Papers},
pubstate = {published},
tppubtype = {article}
}
|
137. | Takumi Kudo, Kodai Ueyoshi, Kota Ando, Kazutoshi Hirose, Ryota Uematsu, Yuka Oba, Masayuki Ikebe, Tetsuya Asai, Masato Motomura, Shinya Takamaeda-Yamazaki Area and Energy Optimization for Bit-Serial Log-Quantized DNN Accelerator with Shared Accumulators Proceedings Article In: IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, Hanoi, Vietnam, 2018. @inproceedings{motomura_00061,
title = {Area and Energy Optimization for Bit-Serial Log-Quantized DNN Accelerator with Shared Accumulators},
author = {Takumi Kudo and Kodai Ueyoshi and Kota Ando and Kazutoshi Hirose and Ryota Uematsu and Yuka Oba and Masayuki Ikebe and Tetsuya Asai and Masato Motomura and Shinya Takamaeda-Yamazaki},
year = {2018},
date = {2018-09-01},
booktitle = {IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip},
address = {Hanoi, Vietnam},
keywords = {Conference Papers},
pubstate = {published},
tppubtype = {inproceedings}
}
|
138. | Masanori Hashimoto, Yuki Nakazawa, Jaehoon Yu Interconnect Delay Analysis for RRAM Crossbar Based FPGA Proceedings Article In: IEEE Computer Society Annual Symposium on VLSI (ISVLSI), pp. 522-527, 2018. @inproceedings{yu-isvlsi-2018,
title = {Interconnect Delay Analysis for RRAM Crossbar Based FPGA},
author = {Masanori Hashimoto and Yuki Nakazawa and Jaehoon Yu},
year = {2018},
date = {2018-07-08},
booktitle = {IEEE Computer Society Annual Symposium on VLSI (ISVLSI)},
pages = {522-527},
keywords = {Conference Papers},
pubstate = {published},
tppubtype = {inproceedings}
}
|
139. | Taro Fujii, Takao Toi, Teruhito Tanaka, Katsumi Togawa, Toshiro Kitaoka, Kengo Nishino, Noritsugu Nakamura, Hiroki Nakahara, Masato Motomura New Generation Dynamically Reconfigurable Processor Technology for Accelerating Embedded AI Applications Proceedings Article In: Symposia on VLSI Technology and Circuits, Hawaii, USA, 2018. @inproceedings{motomura_00062,
title = {New Generation Dynamically Reconfigurable Processor Technology for Accelerating Embedded AI Applications},
author = {Taro Fujii and Takao Toi and Teruhito Tanaka and Katsumi Togawa and Toshiro Kitaoka and Kengo Nishino and Noritsugu Nakamura and Hiroki Nakahara and Masato Motomura},
year = {2018},
date = {2018-06-01},
booktitle = {Symposia on VLSI Technology and Circuits},
address = {Hawaii, USA},
keywords = {Conference Papers},
pubstate = {published},
tppubtype = {inproceedings}
}
|
140. | Masato Motomura [Invited] Hardware-Oriented Approaches for Accelerating “AI” Workloads Presentation Symposium on VLSI Circuits, Short Course, Hololulu, USA, 01.06.2018. @misc{motomura_00063,
title = {[Invited] Hardware-Oriented Approaches for Accelerating “AI” Workloads},
author = {Masato Motomura},
year = {2018},
date = {2018-06-01},
address = {Symposium on VLSI Circuits, Short Course, Hololulu, USA},
keywords = {Invited Talks},
pubstate = {published},
tppubtype = {presentation}
}
|
141. | Takeshi Shimada, Masayuki Ikebe, Prasoon Ambalathankandy, Shinya Takamaeda-Yamazaki, Masato Motomura, Tetsuya Asai Sparse Disparity Estimation Using Global Phase Only Correlation for Stereo Matching Acceleration Proceedings Article In: IEEE International Conference on Acoustics, Speech and Signal Processing, Alberta, Canada, 2018. @inproceedings{motomura_00071,
title = {Sparse Disparity Estimation Using Global Phase Only Correlation for Stereo Matching Acceleration},
author = {Takeshi Shimada and Masayuki Ikebe and Prasoon Ambalathankandy and Shinya Takamaeda-Yamazaki and Masato Motomura and Tetsuya Asai},
year = {2018},
date = {2018-04-01},
booktitle = {IEEE International Conference on Acoustics, Speech and Signal Processing},
address = {Alberta, Canada},
keywords = {Conference Papers},
pubstate = {published},
tppubtype = {inproceedings}
}
|
142. | Kota Ando, Kodai Ueyoshi, Kentaro Orimo, Haruyoshi Yonekawa, Shimpei Sato, Hiroki Nakahara, Shinya Takamaeda-Yamazaki, Masayuki Ikebe, Tetsuya Asai, Tadahiro Kuroda, Masato Motomura BRein Memory: A Single-Chip Binary/Ternary Reconfigurable In-Memory Deep Neural Network Accelerator Achieving 1.4TOPS at 0.6W Journal Article In: IEEE Journal of Solid-State Circuits, vol. 53, no. 4, pp. 983-994, 2018. @article{motomura_00009,
title = {BRein Memory: A Single-Chip Binary/Ternary Reconfigurable In-Memory Deep Neural Network Accelerator Achieving 1.4TOPS at 0.6W},
author = {Kota Ando and Kodai Ueyoshi and Kentaro Orimo and Haruyoshi Yonekawa and Shimpei Sato and Hiroki Nakahara and Shinya Takamaeda-Yamazaki and Masayuki Ikebe and Tetsuya Asai and Tadahiro Kuroda and Masato Motomura},
year = {2018},
date = {2018-04-01},
journal = {IEEE Journal of Solid-State Circuits},
volume = {53},
number = {4},
pages = {983-994},
keywords = {Journal Papers},
pubstate = {published},
tppubtype = {article}
}
|
143. | Ryota Uematsu, Kota Ando, Kodai Ueyoshi, Kazutoshi Hirose, Masayuki Ikebe, Tetsuya Asai, Shinya Takamaeda-Yamazaki, Masato Motomura Exploring CNN Accelerator Design Space on a Dynamically Reconfigurable Hardware Platform Proceedings Article In: Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI), Matsue, Japan, 2018. @inproceedings{motomura_00072,
title = {Exploring CNN Accelerator Design Space on a Dynamically Reconfigurable Hardware Platform},
author = {Ryota Uematsu and Kota Ando and Kodai Ueyoshi and Kazutoshi Hirose and Masayuki Ikebe and Tetsuya Asai and Shinya Takamaeda-Yamazaki and Masato Motomura},
year = {2018},
date = {2018-03-01},
booktitle = {Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI)},
address = {Matsue, Japan},
keywords = {Conference Papers},
pubstate = {published},
tppubtype = {inproceedings}
}
|
144. | Naoto Iwamaru, Shinya Takamaeda-Yamazaki, Masayuki Ikebe, Masato Motomura, Tetsuya Asai A Novel Iris-Center Detection Algorithm towards Gaze Estimation Targeting Molecular Cellular Automata Proceedings Article In: International Workshop on Molecular Architectonics, Osaka, Japan, 2018. @inproceedings{motomura_00074,
title = {A Novel Iris-Center Detection Algorithm towards Gaze Estimation Targeting Molecular Cellular Automata},
author = {Naoto Iwamaru and Shinya Takamaeda-Yamazaki and Masayuki Ikebe and Masato Motomura and Tetsuya Asai},
year = {2018},
date = {2018-03-01},
booktitle = {International Workshop on Molecular Architectonics},
address = {Osaka, Japan},
keywords = {Conference Papers},
pubstate = {published},
tppubtype = {inproceedings}
}
|
145. | Kodai Ueyoshi, Kota Ando, Kazutoshi Hirose, Shinya Takamaeda-Yamazaki, Junichiro Kadomoto, Tomoki Miyata, Mototsugu Hamada, Tadahiro Kuroda, Masato Motomura QUEST: A 7.49-TOPS Multi-Purpose Log-Quantized DNN Inference Engine Stacked on 96MB 3D SRAM using Inductive-Coupling Technology in 40nm CMOS Proceedings Article In: International Solid-State Circuits Conference (ISSCC 2018), San Francisco, US, 2018. @inproceedings{motomura_00076,
title = {QUEST: A 7.49-TOPS Multi-Purpose Log-Quantized DNN Inference Engine Stacked on 96MB 3D SRAM using Inductive-Coupling Technology in 40nm CMOS},
author = {Kodai Ueyoshi and Kota Ando and Kazutoshi Hirose and Shinya Takamaeda-Yamazaki and Junichiro Kadomoto and Tomoki Miyata and Mototsugu Hamada and Tadahiro Kuroda and Masato Motomura},
year = {2018},
date = {2018-02-01},
booktitle = {International Solid-State Circuits Conference (ISSCC 2018)},
address = {San Francisco, US},
keywords = {Conference Papers},
pubstate = {published},
tppubtype = {inproceedings}
}
|
146. | Aoi Tanibata, Alexandre Schmid, Shinya Takamaeda-Yamazaki, Masayuki Ikebe, Masato Motomura, Tetsuya Asai Proto-Computing Architecture over A Digital Medium Aiming at Real-Time Video Processing Journal Article In: Complexity, vol. 2018, pp. 3618621-1-11, 2018. @article{motomura_00010,
title = {Proto-Computing Architecture over A Digital Medium Aiming at Real-Time Video Processing},
author = {Aoi Tanibata and Alexandre Schmid and Shinya Takamaeda-Yamazaki and Masayuki Ikebe and Masato Motomura and Tetsuya Asai},
year = {2018},
date = {2018-02-01},
journal = {Complexity},
volume = {2018},
pages = {3618621-1-11},
keywords = {Journal Papers},
pubstate = {published},
tppubtype = {article}
}
|
147. | Ryutaro Doi, Jaehoon Yu, Masanori Hashimoto Sneak Path Free Reconfiguration of Via-switch Crossbars Based FPGA Proceedings Article In: pp. 68:1–68:8, 2018. @inproceedings{doi2018sneak,
title = {Sneak Path Free Reconfiguration of Via-switch Crossbars Based FPGA},
author = {Ryutaro Doi and Jaehoon Yu and Masanori Hashimoto},
year = {2018},
date = {2018-01-01},
pages = {68:1--68:8},
keywords = {Conference Papers},
pubstate = {published},
tppubtype = {inproceedings}
}
|
148. | Kenshi Ito, Jaehoon Yu, Masanori Hashimoto Adapting Soft Cascade to MAC Operations of Convolutional Neural Networks Proceedings Article In: International Symposium on Multimedia and Communication Technology, pp. 101–104, 2018. @inproceedings{ito2018adapting,
title = {Adapting Soft Cascade to MAC Operations of Convolutional Neural Networks},
author = {Kenshi Ito and Jaehoon Yu and Masanori Hashimoto},
year = {2018},
date = {2018-01-01},
booktitle = {International Symposium on Multimedia and Communication Technology},
pages = {101--104},
keywords = {Conference Papers},
pubstate = {published},
tppubtype = {inproceedings}
}
|
149. | Koichi Mitsunari, Jaehoon Yu, Takao Onoye, Masanori Hashimoto Hardware Architecture for High-Speed Object Detection Using Decision Tree Ensemble Journal Article In: IEICE_J_FECACS, vol. 101, no. 9, pp. 1298–1307, 2018, ((被引用件数: 1)). @article{mitsunari2018hardware,
title = {Hardware Architecture for High-Speed Object Detection Using Decision Tree Ensemble},
author = {Koichi Mitsunari and Jaehoon Yu and Takao Onoye and Masanori Hashimoto},
year = {2018},
date = {2018-01-01},
journal = {IEICE_J_FECACS},
volume = {101},
number = {9},
pages = {1298--1307},
note = {(被引用件数: 1)},
keywords = {Journal Papers},
pubstate = {published},
tppubtype = {article}
}
|
150. | Koichi Mitsunari, Jaehoon Yu, Masanori Hashimoto Hardware Architecture for Fast General Object Detection Using Aggregated Channel Features Proceedings Article In: pp. 55-58, 2018. @inproceedings{mitsunari2018hardware-asscc,
title = {Hardware Architecture for Fast General Object Detection Using Aggregated Channel Features},
author = {Koichi Mitsunari and Jaehoon Yu and Masanori Hashimoto},
year = {2018},
date = {2018-01-01},
pages = {55-58},
keywords = {Conference Papers},
pubstate = {published},
tppubtype = {inproceedings}
}
|